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22ec592 RTL Design Verification Methodologies Qus

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18 views

22ec592 RTL Design Verification Methodologies Qus

hdl

Uploaded by

aravind.a.r.ece
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Prince Shri Venkateshwara Padmavathy Engineering College, Ponmar, Chennai-127

CIAT 2
Branch/Year/Semester: ECE/III/V Date :
22EC592 RTL DESIGN VERIFICATION
Subject Code/Name: Regulation: 2022
METHODOLOGIES
Max.Marks: 100 Duration: 3 hrs

Course Outcomes:
CO1 : Analyze and Verify the digital circuits using hardware description language Verilog HDL
CO2 :
Able to identify the key concepts of Object-Oriented Programming.
CO3 : To learn Hardware Descriptive Language SYSTEM VERILOG
CO4 : Understanding of System Verilog’s randomization, assertion, and coverage features
CO5 :
Design and verify the communication between a test bench and a design under test (DUT) in
System Verilog.
K1 – Remember K2 – Understand K3 – Apply K4 – Analyze K5 – Evaluate K6 -
Create

Answer ALL Questions.


PART A – (10 x 2 = 20 marks)
1. Difference between static function and function 2 CO-1 K-2
2. What is the need of virtual interfaces? 2 CO-1 K-1
3. Define polymorphism? 2 CO-2 K-1

4. Which is best to use to model transaction? Struct or class why? 2 CO-2 K-1

5. List the system tasks that will be used in functional coverage. 2 CO-3 K-2

6. What is the use of packages? How will you access anything from package 2 CO-3 K-1

7. Extract the use of pre and post randomizes method 2 CO-4 K-1

8. Difference between immediate and concurrent Assertions? 2 CO-4 K-2

9. Summarize the use of generator component in SV 2 CO-5 K-2

10. Classify the functionality of monitor component in SV based TB? 2 CO-5 K-2

PART B – (05 x 13 = 65 marks)


11.a) Evaluate the verification process in System Verilog 13
CO-1 K-5
OR
11.b) Relate the communication between test bench and DUT with suitable
diagrams and system Verilog programs 13 CO-1 K-4
12.a) Explain waiting for an event trigger and using event in a loop 13 CO-2 K-4
OR
12.b) Write the use of $cast. How it is used in system Verilog with Inheritance 13 CO-2 K-6
explain with one program
13.a) Analyze the various array methods with examples 13 CO-3 K-5
OR
Collaborate is the use of rand case and rand sequence explain with suitable
13.b)
system Verilog programs 13 CO-3 K-5
14.a) Evaluate the factors in Randomization in system Verilog 13 CO-4 K-5
OR
14.b) Categorize the different types of various System Verilog Assertions with 13 CO-4 K-4
examples

15.a) What is System Verilog mail box? Explain exchange of objects using mail 13 CO-5 K-6
box with suitable examples
OR
15.b) Illustrate about the System Verilog threads? Defend the different types of 13 CO-5 K-4
fork join in System Verilog

PART C – (01 x 15 = 15 marks)


16. a) i)Write any four random number functions with example 15 CO-3 K-6
ii) Judge about the specify time values used in system Verilog
OR

16.b) Design a code for labeling cross coverage Bins and give its summary 15
report CO-4 K-6

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