MBIST

As an indispensable DFT design content in current design, mem bist is becoming

more and more important. This chapter mainly introduces the components of mem
bist, the principles of testing and precautions.

1. mem bist implementation

1.1 The following figure shows the most basic MBIST solution components. The
dotted part is the most basic content, which must be included in any MBIST
solution. The others are optional. Other software algorithms, such as mem repair,
diagnostics, and yield learning, are designed by specific companies and
corresponding designers.

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1.2 The figure above is a specific mbist controller functional schematic diagram
 TAP: ijtag related content, a standard interface.
 TMB: Mem bist controller, contains all the signal generators for mem test, one
TMB can control multiple mems.
 BAP: bist access port, provides control signals to TMB, collects GO/DONE signals
in TMB. MEM interface can be accessed through BAP.
 SIB: Segment insertion bit, similar to a key to open a door, used for signal shift
and update to control the test of certain mems. Increase flexibility.
 Mem Interface: As the interface between mem controller and mem, used for
data transmission, each mem will instantiate the corresponding mem interface.

1.3 The following figure shows the principle diagram of TMB and a MEM interface.
The detailed operation steps are as follows:
1. TMB contains FSM, which is turned on by MBIST_EN and configured by
BIST_SETUP. FSM controls SIGNAL GEN signal, one is sent to a non-func port in
mux in mem interface, and the other is data sent to COMP and compared with
data passing through RAM. At the same time, SIGNAL_GEN will feedback signal
to control FSM to perform the next operation.
2. The test data is sent to the interface, then output by SRAM and sent back to
COMP in TMB for comparison with the original data. If the data comparison is
correct, MBIST_GO is pulled high, otherwise if the data comparison is wrong,
MBIST_GO becomes low. At the same time, COMP will send CMP_STAT signal at
the beginning of the comparison.
3. When the FMS controls the corresponding MEM comparison, it outputs the
MBIST_DONE signal.
4. MBIST_GO and MBIST_DONE signals in TMB can be observed during simulation.
They are used for debugging.

It should be noted that

In the figure, COMP exists in both the mem interface and TMB. This is because both
are reasonable, but each has its own advantages and disadvantages. How to place it
in a specific design requires specific analysis based on the design.

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In the MEM interface:Although the gate count is increased, the signal fed back to
the TMB is only a GO signal, which reduces the PR effort.
When in TMB:COMP is shared, reducing gate count. The size of COMP depends on
the maximum width of all mems and increases PR effort.

1.4 Scannable Mem Interface

As shown in the figure below, the dark blue block is the logic inserted in the mem
interface for scan.
We know that ijtag is mainly used for design pad port testing, mabist is mainly used
for mem testing, and scan is mainly used for func logic testing. Why do we have to
insert scan logic in the mem interface?

I. When scan does not include mem, mem is blackbox, which is mem bypass mode
under scan mode:
 OBSFF, or observation flip-flop, is needed at this time, because the end of FUNC
ADDR is an SRAM considered black box, and this data cannot be observed, which
will result in the final result not being observed along the FUNC ADDR in scan
mode, which will reduce coverage, so OBSFF is increased.
 BYPASSFF works normally at this time, bypassing mem, giving it to the LV_TM
mux and transmitting it out for observation.
II. When the scan includes mem, a special mem lib will be used, which is the mem
no bypass mode under scan mode:
 At this time, the BYPASS logic is not needed, the data is read in normally, and
then read out normally, and finally the 0 port is selected after passing through
LV_TM, which is equivalent to a scan test on mem. The mem lib read in at this
time is a special mem lib used for dft.
 This will of course increase the scan test time, but it will also improve coverage.

2. Tessent mbist test flow

2.1 Test FLow
1. Mem test is initated when the following are true: MBIST_EN =1 &&
BIST_SETUP=10 and is completed in the standby phase.

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2. Clock cycle before test is indicated by rising edge of MBIST_EN, which is

completed in the standby stage.
3. If an error is found during test, MBIS_GO =0 and keep for the remainder of test,
or MBIST_GO keep 1 after initialize phase.
4. If test completed，MBIST_DONE =1.

2.2 Test Results

1) DONE =1 & GO =1: test finished and pass.
2) DONE =0 & GO =1: test not complete but no errors until now, can be caused by
using a slower clock than specified.
3) DONE =1 & GO =0: test finished but at least one mem test failed.
4) DONE =0 & GO =0: test not complete and at least one mem test failed.

As an indispensable DFT design content in current design, mem bist is becoming

more and more important. This chapter mainly introduces the flow of mem bist, how
to implement mbist in tessent, and some commands and modes in tessent.

Overview
 Overview flow
The entire flow is divided into the following parts. The general content explanation
can be seen in the description in the figure.

 Contexts and Modes

The entire implementation process in the flow can be divided into three types
according to the system mode: setup, analysis, and insertion. According to the
context classification, it can be divided into DFT and pattern.From the perspective of
DFT, in the run dft process, it is divided into:
setup : including environment setup and some settings, for insert dft logic
analysis : perform design rule check , insert scan and test point and do
corresponding analysis
insertion : RTL or gate-level editing, that is, dft insertionFrom
the perspective of Contexts:
setup : environment setup and some settings, prepare for gen pattern

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analysis : perform drc check and generate patterns

About command settings:

SETUP> set_contest dft -rtl

1. Load design and specify requirements

1.1 Load design
Load design:

SETUP> read_verilog xxx.v

SETUP> read_verilog -f xxx.list
SETUP> set_current_design top.v
SETUP> set_design_source -format verilog -y <path> -extensisons <ext>
SETUP> read_verilog top.v
Read library:
Use tessent library , mentor atpg library tessent membist models read in and
processed as Tessent Core Descriptions (TCD), and store them in the tsdb database.
Regarding reading the library, if you have not read it before, you can directly read it
with read_cell_library. If you have stored tcd before, you can directly

SETUP> set_design_sources -format tcd_memory

Elaborate design:
 If set_current_design is set before, the elab operation will be automatically
triggered. If only Verilog is read before, the root design needs to be
set.set_current_designIt is set after reading the design and lib.
 During the elab process, some designs can be allowed to be missing, but for
those modules that do not contain mem or mem-related elements,
add_black_box needs to be set.

Optional Data:
A controller (TMB) can only contain mem in one power domain, and different mem
in a power domain can be connected to different controllers.
Use upf information to declare the controller, and read the corresponding upf
through read_upf xxx.upf.
If the mem has laid out the floor plan, the controller can be declared by reading in
def. Read it in through read_def xxx.def.

Report command:
report_design_sources can report the design and the read-in library information.
report_memory_instances can report the corresponding mem information.

Tcl base scripts are also supported.

SETUP> join [lsort [get_name_list [get_mem_inst]]] \n

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1.2 specify requirements

Design Level
Declares the level where the design is located. Different levels of design require
different settings.
*Chip: Declared as the top layer, it means that all ports need to have a pad buffer, a
TAP controller, and a BISR controller. If the pad needs to do boundary scan testing,
the corresponding logic also needs to be inserted.
*Sub_Sys: It may not be necessary to do TAP and BISR controllers. You only need to
put in the related small logic, do synthesis and timing.

Memory BIST Options

 set_dft_specification_requirement -memory_test on|off
 After the above command settings, there will also be -mem_bist on|off -
mem_bisr_chain on|off -mem_bisr_controller on | off settings according to
design requirements.

Memory Instance Options

 set_memory_instance_options <mem_instances> [***]
 By setting the relevant properties of the mem that has been checked by drc, and
create dft specification

add inputs constraints

For some special primary inputs, such as scan signals related to scan, they need to be
set to fixed values.
 add_input_constraints scan_en -C0
 add_input_constraints scan_mode -C0
 add_input_constraints pll_bypass -C0

For example, set_attribute_value

defines some signals on the top. For example, define TAP in the TOP as shown below.

 set_attribute_value tck_p -name function -value tck

 set_attribute_value tdi_p -name function -value tdi

The set clock

tessent tool will trace the clock from the CK pin of the mem to the clock source. The
clock must be defined using add_clock

SETUP> add_clock CLK -period 10ns -label RAM_CLK_100M

The clock can also be divided and multiplied.

SETUP> add_clock CLK_DIV -label RAM_CLK_mul_500M -reference PLL/OUT -

freq_multiplier 5

DRCs

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When all the above constrants are set, check them through check_design_rules. If
there is no error in DRCs, the sys mode will be set to analysis mode, otherwise it will
return to setup mode.
If there is a problem with DRCs, debug it through analyze_drc_violation .
So far, the content about Load design and specify requirements has been introduced.

2. Create and Process DFT Specification

This step will create a DFT specification through the design and constraint of the first
step. Then make targeted modifications. Then the corresponding BIST circuit and
IJTAG circuit will be generated.

2.1 Create DFT specification

A dft specification is generated by design level, specification requirements,
mem_instance_options, defaultspecification, design, etc. You can review the existing
dft specification by using the report_config_data method to print out the text or the
display_specification method to use the gui interface. More details are introduced in
the following chapters.

2.2 Process DFT specification

 process_dft_spec is used to use the previous dft specification to generate and
insert RTL bist logic.
 -no_insertion: Only generate bist rtl logic without inserting it into rtl

The tessent tool will store the process content in ./tsdb_outdir by default, and all
modified designs will be saved in the corresponding directory.
IJTAG ICL and PDL files will also be stored accordingly. As shown in the figure below,
the tsdb_outdir directory basically stores all our DFT-related content.

3. Extract ICL
 The BIST logic inserted in the above content is inserted using the IEEE standard
engineering. The ICL step extracts the relevant content as a backup. ICL:

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instrument connectivity language. ICL is extracted through the process_dft_spec

step.
 ICL describes the ports and basic components of the test module/hardware.
extract_icl verifies the connectivity of the ICL module and generates the ICL file
for the corresponding design level.
 To ensure the ICL extraction process is pass, otherwise it will affect the
generation of test patterns. After ICL passes, the ICL description file of the
current design is generated to generate patterns. If there are errors, you can
debug ICL extraction errors through DFTvisualizer.
 Generally, errors may be caused by some IPs that use the self-written DFT
specification instead of the DFT specification automatically generated by the
tool.

4. Patterns Specification
The tool generates test patterns for BIST signoff simulation (simulated testbench),
and then ATE test of subsequent chip return. (Simulated testbench and machine
usage files)

 create_patterns_specification signoff | manufacturing -replace generates a

preview file of the corresponding pattern, but is not actually generated, similar
to create dft specification.
 process_patterns_specification eats the pattern preview file and performs real
pattern generation, similar to process dft specification.

5. Simulation Validation
This is the last step in the design flow, which simulates the testbench.
 run_testbench_simulations, based on the test case, simulates the generated
pattern
 check_testbench_simulations brief summary.

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