PG016 Video Time Controllerv6.1
PG016 Video Time Controllerv6.1
Controller v6.1
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Appendix B: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Upgrading in Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Features Simulation
Models
Encrypted RTL, VHDL or Verilog Structural
Overview
All video systems require management of video timing signals, which are used to
synchronize processes. The Video Timing Controller serves the function of both detecting
and generating these timing signals.
The input side of this core automatically detects horizontal and vertical synchronization
pulses, polarity, blanking timing and active video pixels. While on the output, it generates
the horizontal and vertical blanking and synchronization pulses used with a standard video
system including support for programmable pulse polarity. The core is commonly used with
the Video in to AXI4-Stream core to detect the format and timing of incoming video data or
with the AXI4-Stream to Video out core to generate outgoing video timing for downstream
sinks such as a video monitor.
Video systems may utilize different combinations of blank, synchronization or active signals
with various polarities to synchronize processing and control video data. The Video Timing
Controller simplifies working with video timing signals by providing a highly programmable
and flexible core that allows detection and generation of the various timing signals within
a video system.
Feature Summary
The Video Timing Controller core supports the AXI4-Lite interface and a constant-mode
interface. The AXI4-Lite interface allows the core to be easily incorporated into a Vivado
project. The Constant interface utilizes core parameters configurable by the Graphical User
Interface (GUI) to setup the core for fixed-mode operation. These configurable options
allow the Video Timing Controller core to be easily integrated with AXI4 based processor
systems, with non-AXI4-compliant processors systems with some additional logic, and in
systems without a processor.
The Video Timing Controller core supports detecting video frame sizes up to 8192 clocks by
8192 lines (including horizontal and vertical blanking). The detection typically requires
three to five input video frames to detect and lock. The Video Timing Controller core
automatically detects the timing involved with horizontal/vertical blanks and syncs. The
timing of the active_video and the active_chroma signals are also detected. This
allows the user to easily determine the video frame size via the core register (AXI4-Lite)
interface. The minimum set of signals used for detection is either vertical blank, horizontal
blank and active video or vertical sync, horizontal sync and active video. The polarities of
each input signal is also detected and reported via the register interface to allow easy use
of each signal once the polarity is known.
The core also supports generating and regenerating (matching the detected input) video
frame sizes up to 8192 clocks by 8192 lines (including blanking time). The output can be the
same format or a different format as the detected input. This allows detecting one format
and generating a different format. The output can also be synchronized to the detected
input and has separate signal polarity settings as well. This allows regenerating the input
with different signal polarities or with slight timing adjustments (such as delayed or shorted
active video).
The Video Timing Controller core supports up to 16 frame sync output signals. These are
toggled high for one clock cycle during each frame. These frame syncs allow triggering
timing critical hardware processes at different times during a frame.
Applications
• Video Surveillance
• Industrial Imaging
• Video Conferencing
• Machine Vision
• Video Systems requiring timing detection or timing generation
For more information, visit the Video Timing Controller product web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.
Product Specification
Standards
The Video Timing Controller core is compliant with the AXI4-Lite interconnect standards.
Refer to the Video IP: AXI Feature Adoption section of the Vivado AXI Reference Guide
(UG1037) [Ref 1] for additional information.
Performance
The following sections detail the performance characteristics of the Video Timing
Controller core.
Maximum Frequencies
This section contains typical clock frequencies for the target devices. The maximum
achievable clock frequency can vary. The maximum achievable clock frequency and all
resource counts can be affected by other tool options, additional logic in the FPGA device,
using a different version of Xilinx tools and other factors.
Latency
The Video Timing Controller core does not read or generate data, and therefore, does not
have a specific data latency.
The Video Timing Controller core monitors and generates control signals. The output
control signals can be configured to be the same as the input with no latency, or the output
signals can be configured to incur a multi-clock or multi-line delay.
Throughput
The Video Timing Controller core does not read or generate data, and does not have a
specific throughput.
Resource Utilization
For details about resource utilization, visit Performance and Resource Utilization.
Port Descriptions
The Video Timing Controller (VTC) core uses the AXI4-Lite industry standard control
interface to connect to other system components. The following sections describe the
various interfaces available with the core. Some signals are optional and not present for all
configurations of the core. The AXI4-Lite interface and the IRQ pin are present only when
the core is configured via the GUI with an AXI4-Lite control interface. The INTC_IF interface
is present only when the core is configured via the GUI with the INTC interface enabled.
Figure 2-1 illustrates an I/O diagram of the VTC core.
field_id_in field_id_out
vblank_in vblank_out
vsync_in vsync_out
Video Timing hblank_in hblank_out Video Timing
(input) hsync_in hsync_out (output)
Interface active_video_in active_video_out Interface
active_chroma_in active_chroma_out
s_axi_aclk irq
s_axi_aclken
s_axi_aresetn intc_if[31:0]
s_axi_awaddr[8:0]
s_axi_awvalid fsync_out[15:0]
s_axi_awready
s_axi_wdata[31:0]
s_axi_wstrb[31:0]
s_axi_wvalid
Optional
AXI4-Lite s_axi_wready
Control s_axi_bresp[1:0]
Interface s_axi_bvalid
s_axi_bready
s_axi_araddr[8:0]
s_axi_arvalid
s_axi_arready
s_axi_rdata[31:0]
s_axi_rresp[31:0]
s_axi_rvalid
s_axi_rready
clk
clken
resetn
gen_aclken
det_aclken
fsync_in
Core Interfaces
Control Interface
Video systems commonly use an integrated processor system to dynamically control the
parameters within the system. This is especially important when several independent image
processing cores are integrated into a single FPGA. The Video Timing Controller core can be
configured with an AXI4-Lite interface.
The signals not included in the AXI4-Lite interface are specified in Table 2-1.
Notes:
1. All ports are little-endian.
The clk, clken and resetn , det_clken, and gen_clken signals are shared between the
core and the Video Timing interfaces. The AXI4-Lite control interface has its own set of
clock, clock enable and reset pins: S_AXI_ACLK, S_AXI_ACLKEN and S_AXI_ARESETn.
Setting clken low (de-asserted) halts the operation of the core despite rising edges on the
clk pin. Internal states are maintained, and output signal levels are held until clken is
asserted again. When clken is de-asserted, core inputs are not sampled, except resetn,
which supersedes clken. This clock must be running for AXI4-Lite registers to be read and/
or written, since all core registers reside within the core clock domain. This clock enable
must be asserted high for AXI4-Lite registers to be read and/or written, since all core
registers reside within the core clock domain. If the clock enable is deasserted, the AXI4-Lite
interface asserts the slave error response (0x2) for all addresses.
AXI4-Lite Interface
The AXI4-Lite interface creates a core that can be easily added to an Vivado Project as a
processor peripheral. This section describes the I/O signals associated with the Video
Timing Controller AXI4-Lite interface.
Notes:
1. The function and timing of these signals are defined in the AMBA AXI Protocol Version: 2.0 Specification.
2. For signals S_AXI_RRESP[1:0] and S_AXI_BRESP[1:0], the core does not generate the Decode Error ('11') response.
Other responses such as '00' (OKAY) and '10' (SLVERR) are generated by the core based upon certain conditions.
Notes:
1. The function and timing of these signals are defined in the AMBA AXI Protocol Version: 2.0 Specification.
2. For signals S_AXI_RRESP[1:0] and S_AXI_BRESP[1:0], the core does not generate the Decode Error ('11') response.
Other responses such as '00' (OKAY) and '10' (SLVERR) are generated by the core based upon certain conditions.
The DET_ENABLE bit allows enabling the detector independently from the generator. The
internal detector enable is a logical "OR" between the DET_ENABLE and SW_ENABLE bits in
the control register. The internal logic that controls the detector sub-core enable is shown
in Figure 2-5. The SW_ENABLE bit allows setting one bit to '1' to enable both the detector
and the generator. To enable the detector or the generator only, the SW_ENABLE bit must
be set to '0' and the detector/generator ENABLE bits (Control Register bits [3:2]) set
independently.
X-Ref Target - Figure 2-5
The internal generator enable is a logical "OR" between the GEN_ENABLE and SW_ENABLE
bits in the control register. The internal logic that controls the generator sub-core enable is
shown in Figure 2-6.
Notes:
1. Writing a '1' to a bit in the STATUS register will clear the corresponding interrupt when set. Writing a '1' to a bit that is
cleared, will have no effect.
Notes:
1. Writing a '1' to a bit in the ERROR register will clear the corresponding bit when set. Writing a '1' to a bit that is cleared, will
have no effect.
Notes:
1. Setting a bit high in the IRQ_ENABLE register enables the corresponding interrupt. Bits that are low mask the
corresponding interrupt from triggering.
Table 2‐13: Detector Horizontal Frame Size Register (Address Offset 0x0030)
DETECTOR
0x0030 Read
HSIZE
Name Bits Description
RESERVED 31:13 Reserved
FRAME_HSIZE 12:0 Detected Horizontal Frame Size. The width of the frame with
blanking in number of pixels/clocks.
Table 2‐14: Detector Vertical Frame Size Register (Address Offset 0x0034)
DETECTOR
0x0034 Read
VSIZE
Name Bits Description
RESERVED 31:29 Reserved
FIELD1_VSIZE 28:16 Detected Vertical Field 1 Size. The height with blanking in number
of lines of field 1.
FRAME_VSIZE 12:0 Detected Vertical Frame or Field 0 Size. The height of the frame with
blanking in number of lines.
Table 2‐16: Detector Frame/Field 0 Vertical Blank Cycle Register (Address Offset 0x003C)
DETECTOR
0x003C Read
F0_VBLANK_H
Name Bits Description
RESERVED 31:29 Reserved
F0_VBLANK_HEND 28:16 Detected Vertical Blank Horizontal End
End Cycle index of vertical blank. Denotes the first cycle
vblank_in is de-asserted.
RESERVED 15:13 Reserved
F0_VBLANK_HSTART 12:0 Detected Vertical Blank Horizontal Start
Start Cycle index of vertical blank. Denotes the first cycle
vblank_in is asserted.
Table 2‐17: Detector Frame/Field 0 Vertical Sync Line Register (Address Offset 0x0040)
DETECTOR
0x0040 F0_VSYNC_V Read
Table 2‐18: Detector Frame/Field 0 Vertical Sync Cycle Register (Address Offset 0x0044)
DETECTOR
0x0044 F0_VSYNC_H Read
Table 2‐19: Detector Field 1 Vertical Blank Cycle Register (Address Offset 0x0048)
DETECTOR
0x0048 Read
F1_VBLANK_H
Name Bits Description
RESERVED 31:29 Reserved
F1_VBLANK_HEND 28:16 Detected Field 1 Vertical Blank Horizontal End
End Cycle index of vertical blank for field 1.
Denotes the first cycle
vblank_in is de-asserted.
RESERVED 15:13 Reserved
F1_VBLANK_HSTART 12:0 Detected Field 1 Vertical Blank Horizontal Start
Start Cycle index of vertical blank for field 1.
Denotes the first cycle
vblank_in is asserted.
Table 2‐20: Detector Field 1 Vertical Sync Line Register (Address Offset 0x004C)
Table 2‐21: Detector Field 1 Vertical Sync Cycle Register (Address Offset 0x0050)
DETECTOR
0x0050 F1_VSYNC_H Read
Table 2‐22: Generator Active Size Register for Field 0 (Address Offset 0x0060)
GENERATOR
0x0060 Read/Write
ACTIVE_SIZE
Name Bits Description
RESERVED 31:29 Reserved
ACTIVE_VSIZE 28:16 Generated Vertical Active Frame Size. The height of the frame
without blanking in number of lines.
RESERVED 15:13 Reserved
ACTIVE_HSIZE 12:0 Generated Horizontal Active Frame Size. The width of the frame
without blanking in number of cycles (1).
Notes:
1. Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels
per clock.
Table 2‐26: Generator Horizontal Frame Size Register (Address Offset 0x0070)
GENERATOR
0x0070 Read/Write
HSIZE
Name Bits Description
RESERVED 31:13 Reserved
FRAME_HSIZE 12:0 Generated Horizontal Frame Size. The width of the frame with
blanking in number of cycles (1).
Notes:
1. Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels
per clock.
Table 2‐27: Generator Vertical Frame Size Register (Address Offset 0x0074)
GENERATOR
0x0074 VSIZE Read/Write
Table 2‐29: Generator Frame/Field 0 Vertical Blank Cycle Register (Address Offset 0x007C)
GENERATOR
0x007C Read/Write
F0_VBLANK_H
Name Bits Description
RESERVED 31:29 Reserved
F0_VBLANK_HEND 28:16 Generated Vertical Blank Horizontal End
End Cycle index of vertical blank. Denotes the first cycle
vblank_in is de-asserted.
RESERVED 15:13 Reserved
F0_VBLANK_HSTART 12:0 Generated Vertical Blank Horizontal Start
Start Cycle index of vertical blank. Denotes the first cycle
vblank_in is asserted.
Table 2‐30: Generator Frame/Field 0 Vertical Sync Line Register (Address Offset 0x0080)
GENERATOR
0x0080 F0_VSYNC_V Read/Write
Table 2‐31: Generator Frame/Field 0 Vertical Sync Cycle Register (Address Offset 0x0084)
GENERATOR
0x0084 F0_VSYNC_H Read/Write
Table 2‐32: Generator Field 1 Vertical Blank Cycle Register (Address Offset 0x0088)
GENERATOR
0x0088 Read
F1_VBLANK_H
Name Bits Description
RESERVED 31:29 Reserved
F1_VBLANK_HEND 28:16 Generated Field 1 Vertical Blank Horizontal End
End Cycle index of vertical blank for field 1.
Denotes the first cycle
vblank_in is de-asserted.
RESERVED 15:13 Reserved
F1_VBLANK_HSTART 12:0 Generated Field 1 Vertical Blank Horizontal Start
Start Cycle index of vertical blank for field 1.
Denotes the first cycle
vblank_in is asserted.
Table 2‐33: Generator Field 1 Vertical Sync Line Register (Address Offset 0x008C)
Table 2‐34: Generator Field 1 Vertical Sync Cycle Register (Address Offset 0x0090)
GENERATOR
0x0090 F1_VSYNC_H Read
Table 2‐35: Generator Active Size Register for Field 1 (Address Offset 0x0094)
FRAME SYNC 0
0x0100 Read/Write
CONFIG
Name Bits Description
RESERVED 31:29 Reserved
ACTIVE_VSIZE 28:16 Generated Vertical Active Frame Size. The height of the frame
without blanking in number of lines.
RESERVED 15:13 Reserved
ACTIVE_HSIZE 12:0 Generated Horizontal Active Frame Size. The width of the frame
without blanking in number of cycles (1).
Notes:
1. Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels
per clock.
Table 2‐36: Frame Sync 0-15 Configuration Registers (Address Offsets 0x0100 - 0x013C)
FRAME SYNC 0
0x0100 CONFIG Read/Write
Frame Sync 1-15 Config Registers (address offset 0x0100 - 0x013c) have the same format as the Frame Sync 0
Config Register.
Basic Architecture
The Video Timing Controller core contains three modules: the video timing detector, the
video timing generator and the interrupt controller. See Figure 3-1.
Either the detector or the generator module can be disabled at instantiation with the GUI to
save resources.
X-Ref Target - Figure 3-1
The blanking and active period definitions were discussed in Chapter 1, Overview. In
addition to these definitions, the period from the start of blanking (or end of active video)
to the start of synchronization is called the front porch. The period from the end of
synchronization to the end of blanking (or start of active video) is called the back porch. The
total horizontal period (including blanking and active video) can also be defined, and
similarly the total vertical period.
Figure 3-2 shows the start of the horizontal front porch (Hblank Start), synchronization
(Hsync Start), back porch (Hsync End) and active video (SAV). It also shows the start of the
vertical front porch (Vblank Start), synchronization (Vsync Start), back porch (Vsync End)
and active video (SAV). The total number of horizontal clock cycles is HSIZE and the total
number of lines is the VSIZE.
X-Ref Target - Figure 3-2
Figure 3‐2: Example Video Frame and Timing Signals with Front and Back Porch
These definitions of video frame periods are used for both Video Timing Detection and
Video Timing Generation.
IMPORTANT: Note that pixels-per-clock for video data and timing is non-existent in the Video Timing
Controller. There is only a single set of timing signals for the video data bus. This means that horizontal
timing settings can be detected and generated only for a multiple of the pixels-per-clock configured in
the system. For example, given a video format where the active line is 1920, the system configured with
a video data bus operating at 4 pixels-per-clock, the detected and generated timing for the active line
would be (1920 pixels / 4 pixels-per-clock) = 480 clock (cycles). Similarly, all other horizontal
components (i.e. hsync, hblank) would be effected, while the vertical components do not change.
The detected polarity of each input signal is shown by bits 0-5 of the Detection Polarity
Register (address offset 0x2C). High denotes active-High polarity, and low denotes
active-Low polarity. Bits 8 and 9 of the Detection Encoding Register shows the number of
lines skipped between each active chroma line. Bit 8 High denotes that every other line is
skipped (4:2:0), and low denotes that no lines are skipped (4:4:4 or 4:2:2). Bit 9 High denotes
that every other pixel is skipped, and low denotes that no pixels are skipped.
The polarity of each output signal can be set by bits 0-5 of the Generator Polarity Register
(Address Offset 0x006C). High denotes active-High polarity, and low denotes active-Low
polarity. Bits 8 and 9 of the Control Register also sets the number of lines skipped between
each active chroma line. Bit 8 High denotes that every other line is skipped (4:2:0), and low
denotes that no lines are skipped (4:4:4 or 4:2:2). Bit 9 High denotes that every other pixel
is skipped, and low denotes that no pixels are skipped.
The Video Timing Controller has bits in the Control Register called Source Selects to select
the internal detection registers or the external input generation registers. These bits allow
the detected timing (if enabled) to control the generated outputs or allow the host
processor to override each value independently via the generation registers at address
offset 0x0060 - 0x0084, as described in Table 2-3.
Table 3-1 through Table 3-6 show example settings of the input control busses and the
resultant video timing output signals.
Notice that in Table 3-1 the Control Register bit 2 is set to enable generation, that all source
selects are set to 1 to select the Generation Registers and that the polarity bits are all set to
1 to configure the outputs for active-High polarity.
IMPORTANT: All signals are shown active-High. The polarities of the output signals can be changed at
any time via the GENERATOR POLARITY REGISTER (0x006C).
The following C code shows how to configure the register values in Table 3-1 using the
Video Timing Controller driver.
XVtc_Config *VtcCfgPtr;
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
SignalCfg.V0Total = 7;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 3;// Active Video Height
SignalCfg.V0SyncStart = 4;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 5;// Active Video Height + FP Width + Sync Width
Notice that in Table 3-2 the Generator Encoding Register bits [3:0] are set to 0 to configure
the number of lines skipped between each active chroma line to be 0. This configures the
Active Chroma output signal for 4:4:4 or 4:2:2 mode in which every line contains valid
chroma samples.
The following C code shows how to configure the register values in Table 3-2 using the
Video Timing Controller driver.
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
Vertical Generation Configuration Example with Active Chroma for YUV 4:2:0
Active for Even Lines
Programming the vertical generation registers to the values shown in Table 3-3 will result in
the video timing signal outputs shown in Figure 3-5.
Notice that in Table 3-3 the Generator Encoding Register bits [3:0] are set to 0b0011 to
configure the number of lines skipped between each active chroma line to be one line. This
configures the Active Chroma output signal for 4:2:0 mode in which only every other line
contains valid chroma samples.
The following C code shows how to configure the register values in Table 3-3 using the
Video Timing Controller driver.
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
Vertical Generation Configuration Example with Active Chroma for YUV 4:2:0
Active for Odd Lines
Programming the vertical generation registers to the values shown in Table 3-4 will result in
the video timing signal outputs shown in Figure 3-6.
Notice that the Generator Encoding Register bits [3:0] are set to 0b0011, as in the previous
example. Bits [9:8] of the Generator Encoding Register is set to 1 instead of 0. This
configures the Active Chroma output signal for 4:2:0 mode, but with the opposite line set.
Table 3‐4: Example Vertical Generation Register Inputs (Alternate 4:2:0 Chroma)
Register Address Register Name Value
0x0060 Generator Active Size 0x0004_0003
The following C code shows how to configure the register values in Table 3-4 using the
Video Timing Controller driver.
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 1;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
Notice that all polarities bits are High in the Detection Polarity Register, signifying that all
inputs are detected to have an active-High polarity.
Notice, in the Control Register, that bit 2 is set to enable generation, bit 3 is set to enable
detection and bit 5 is set to enable synchronizing the generated output to the detected
inputs.
The Horizontal Size (ACTIVE_HSIZE_SRC) Source Select (bit 9 of the Control Register) is
set to 1. All other source selects are low, signifying that all other detection registers should
be used.
Also notice that the polarity of the output horizontal synchronization has been changed to
active-Low by clearing bit 3 of the Generator Polarity Register.
X-Ref Target - Figure 3-7
IMPORTANT: All generated outputs remain synchronized to the inputs. The only changes
made to the output are to the horizontal synchronization polarity and to the active video
start and stop times.
The following C code shows how to configure the register values in Table 3-6 using the
Video Timing Controller driver.
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
SourceSelect.VChromaSrc = 0;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 0;
SourceSelect.VSyncSrc = 0;
SourceSelect.VFrontPorchSrc = 0;
SourceSelect.VTotalSrc = 0;
SourceSelect.HActiveSrc = 0;
SourceSelect.HBackPorchSrc = 0;
SourceSelect.HSyncSrc = 0;
SourceSelect.HFrontPorchSrc = 0;
SourceSelect.HTotalSrc = 0;
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
Synchronization
Generation of the video timing output signals can be synchronized to the detected video
timing input signals or generated independently by setting the SYNC_ENABLE field in the
control register or selecting the GUI option to synchronize the generator to detector or
fsync_in. Synchronization allows the generator to follow the phase of the detector
timing. Synchronization of the output to the input allows the developer to override each
individual timing signal with different settings such as signal polarity or start time. For
example, the active video signal could be regenerated shifted one cycle earlier or later. This
provides a flexible method for regenerating video timing output signals with different
settings while remaining synchronized to the input timing.
The Video Timing Controller also has a GUI parameter, called Auto Generation Mode, to
control the behavior of the generated outputs based on the detected inputs. When the Auto
Generation Mode parameter is set, the generated video timing outputs will change based
on the detected inputs. If this parameter is not set, then the video timing outputs will be
generated based on only the first detected input format. (If the detector loses lock, the
generated outputs will continue to be generated.) To change output timing while Auto
Generation Mode is set, timing detection must first be disabled by clearing bit 1 in the
Control Register and then re-enabling, if any of the Source Select bits are low.
Frame Syncs
The Video Timing Controller has a frame synchronization output bus. Each bit can be
configured to toggle high for any one clock cycle during each video frame. Each bit is
independently configured for horizontal and vertical clock cycle position with the Frame
Sync Configuration Registers (address offsets 0x0100 - 0x013c).
Interrupts
The Video Timing Controller has an active-High interrupt output port named "irq". This
output is set high when an interrupt occurs and set low when the interrupt event has been
cleared. The Video Timing Controller also contains three 32-bit registers for configuring
and reporting status of interrupts: the Interrupt Status/Clear, the Interrupt Enable and the
Interrupt Clear Registers. A logical AND is performed on the Interrupt Enable Register and
the Interrupt Status Register to set the interrupt output high. The Interrupt Clear Register is
used to clear the Interrupt Status Register. Writing a '1' to a bit in the Interrupt Status
Register clears the corresponding interrupt when set. Writing a '1' to a bit that is cleared,
will have no effect.
Use Model
This section illustrates likely usage scenarios for the Xilinx® Video Timing Controller core.
Video-In
AXI4 AXI AXI4
MM Stream
To
VDMA Source
AXI4-Stream Video
Timing
Signals
AXI4
Stream
Video fsync
AXI4 AXI
Processor
External External MM VDMA AXI4
Stream
1 Video
Memory Memory
AXI4 AXI Timing AXI4
Controller MM Lite
Interconnect Controller
(DDR3 AXI4 Video
SDRAM) (AXI DDRX) AXI4 AXI Stream
MM
Processor
VDMA
AXI4 2 fsync
Stream Generated
Video
Timing
AXI4-Stream Signals
AXI4 AXI AXI4
MM Stream
To
VDMA
Video-Out
To Display
To detect the timing of the source video, the timing signals are connected to the Video
Timing Controller Detection Module. Both the timing and the signal polarity of the timing
signals are captured and easily read by the host processor.
Video timing signals are generated to control a AXI4-Stream to Video-Out module and an
external display. The timing of these output signals is controlled by the host processor. The
Video Timing Controller can be configured in real-time to replicate the source video format
or to slightly change the format on the output, for example, in cases where the input signals
are positive polarity yet the display requires negative polarity synchronization signals. The
Video Timing Controller can also be reconfigured in real-time to output a completely
different format from the input source.
Two Frame Sync outputs are generated to control Video Processor 1 and Video Processor 2.
These outputs could be used to control when Video Processor 2 starts processing relative to
when Video Processor 1 starts processing. These Frame Syncs can be reconfigured in
real-time as well.
The Video Timing Controller is connected to a Host Processor in this example. The AXI4-Lite
Interface allows for easy connection between status/control registers and the host
processor. In addition, the Video Timing Controller interrupt output can also be used to
synchronize the software with hardware events.
If the video system requires that only complete video frames are sent from the Video-In To
AXI4-Stream core, then the Video Timing Controller must be configured to drive the
axis_enable input with bit 8 of the INTC_IF bus. This bus must be enabled with the "Include
INTC Interface".
X-Ref Target - Figure 3-9
Video Timing
Controller field_id_out
(Generator) vblank_out
vsync_out
fsync_in hblank_out Video Timing
hsync_out (output)
active_video_out Interface
active_chroma_out
fsync_out
Video Timing
Controller field_id_out
(Generator) vblank_out
vsync_out
vsync fsync_in hblank_out Video Timing
vblank hsync_out (output)
Interface
active_video_out
active_chroma_out
Select
In this example, the bottom timing generator can be synchronized to the top timing
controller, a separate vsync or separate vblank signal. This is controlled by the mux "Select"
signal.
IMPORTANT: The timing generator can be offset from the input by configuring the Generator Global
Delay Register (Address Offset 0x140)].
Once the fsync_in input is selected, the pixel or line offset delay of the synchronized
generator can be configured with the Generator Global Delay Register.
Clocking
The Video Timing Controller core has two clock sources, CLK and S_AXI_ACLK, one for
each clock domain. The Video Timing Controller core also has four clock enable sources:
CLK, DET_CLKEN, GEN_CLKEN and S_AXI_ACLKEN.
CLK
The input and output video timing interfaces use the CLK clock signal as their shared clock
reference.
S_AXI_ACLK
The AXI4-Lite interface uses the S_AXI_ACLK pin as its clock source. The CLK pin is not
shared between the AXI4-Lite and video timing interfaces. The Video Timing Controller core
contains clock-domain crossing logic between the CLK (video timing) and S_AXI_ACLK
(AXI4-Lite) clock domains. The core automatically ensures that the AXI4-Lite transactions
completes even if the video processing is stalled with RESETn, CLKEN or with the video
clock not running.
CLKEN
The Video Timing Controller core has multiple enable options: the CLKEN pin (hardware
clock enable), and the software enable option provided via the AXI4-Lite control interface
(when present).
The CLKEN pin cannot ensure synchronization internally to video timing processing
therefore de-asserting CLKEN for extended periods of time may lead to generating
incomplete frames or lengthening the period needed to detect incoming video frame
timing.
• Multi-cycle path designs (high speed clock division without clock gating),
• Standby operation of subsystems to save on power
• Hardware controlled bring-up of system components
DET_CLKEN
The Video Timing Controller core also has a separate clock enable input pin to control the
detector. This clock enable allows halting the detector independently from the generator.
GEN_CLKEN
The Video Timing Controller core also has a separate clock enable input pin to control the
generator. This clock enable allows halting the generator independently from the detector.
S_AXI_ACLKEN
The S_AXI_ACLKEN is the clock enable signal for the AXI4-Lite interface only. Driving this
signal low only affects the AXI4-Lite interface and does not halt the video timing processing
in the CLK clock domain.
Resets
The Video Timing Controller core has two reset pins, RESETn and S_AXI_ARESETn, one
for each clock domain. Both resets are active-Low.
RESETn
The Video Timing Controller core has two reset sources: the RESETn pin (hardware reset),
and the software reset provided via the AXI4-Lite control interface (when present). The
software reset is available via the control register at address offset 0x0000, bit 31.
IMPORTANT: RESETn is not synchronized internally to the video timing processing. De-asserting
RESETn while frame timing is being process can lead to incomplete frames (from the generator).
The external reset pulse needs to be held for at least 32 CLK cycles to reset the core. The
RESETn signal only resets the video timing interfaces and processing of the core. The
AXI4-Lite interface is unaffected by the RESETn signal to allow the video timing processing
core to be reset without halting the AXI4-Lite interface. However, if the RESETn is asserted
low during an AXI4-Lite register read or write, the AXI4-Lite interface asserts the slave error
response (0x2) for all addresses.
IMPORTANT: When a system with multiple-clocks and corresponding reset signals are being reset, the
reset generator has to ensure all signals are asserted/de-asserted long enough so that all interfaces
and clock-domains are correctly reinitialized.
S_AXI_ARESETn
The S_AXI_ARESETn signal is synchronous to the S_AXI_ACLK clock domain, but is
internally synchronized to the CLK clock domain. The S_AXI_ARESETn signal resets the
entire core including the AXI4-Lite and video timing interfaces.
Protocol Description
The Video Timing Controller core register interface is compliant with the AXI4-Lite
interface.
For details, see the sections, “Working with IP” and “Customizing IP for the Design” in the
Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 3] and the “Working with the
Vivado IDE” section in the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 5].
If you are customizing and generating the core in the Vivado IP Integrator, see the Vivado
Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref 7] for
detailed information. IP Integrator might auto-compute certain configuration values when
validating or generating the design. To check whether the values do change, see the
description of the parameter in this chapter. To view the parameter value you can run the
validate_bd_design command in the Tcl console.
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the
current version.
The GUI displays a representation of the IP symbol on the left side and the parameter
assignments on the right side, described as follows:
• Component Name: The component name is used as the base name of output files
generated for the module. Names must begin with a letter and must be composed
from characters: a to z, 0 to 9 and “_”.
Note: The name v_tc_v6_1 is not allowed.
• Optional Features:
° Include INTC Interface: When selected, the core generates the optional INTC_IF
port, which gives parallel access to signals indicating frame processing status and
error conditions. For more information, refer to Interrupts in Chapter 2.
- Interlaced Video Support: When selected, the core is generated with interlaced
video detection and/or generation enabled.
- Synchronize Generator to Detector or to fsync_in: When selected, the timing
generator automatically synchronizes to the detector or to the fsync_in input
port. Otherwise, the generator runs in free-run mode.
• Options:
° Maximum Clocks per Line: This parameter sets the maximum number of clock
cycles per video line that the Video Timing Controller can generate or detect.
Values of 128, 256, 512, 1024, 2048, 4096 and 8192 are valid.
° Maximum Lines per Frame: This parameter sets the maximum number of lines per
video frame that the Video Timing Controller can generate or detect. Values of 128,
256, 512, 1024, 2048, 4096 and 8192 are valid.
° Frame Syncs: This parameter sets the number of frame synchronization outputs to
generate and supports up to 16 independent outputs.
° Enable Generation: This parameter enables or disables the video timing outputs.
° Enable Detection: This parameter enables or disables the detecting the timing of
the video inputs.
° Generation Options:
- Field ID Generation: This parameter enables or disables generating the field ID
output.
- Vertical Blank Generation: This parameter enables or disables generating the
vertical blank output.
- Horizontal Blank Generation: This parameter enables or disables generating
the horizontal blank output.
- Vertical Sync Generation: This parameter enables or disables generating the
vertical synchronization output.
- Horizontal Sync Generation: This parameter enables or disables generating the
horizontal synchronization output.
- Active Video Generation: This parameter enables or disables generating the
active video output.
- Active Chroma Generation: This parameter enables or disables generating the
active chroma output.
- Auto Generation Mode: When enabled, this parameter will cause the generated
video timing outputs to change based on the detected inputs. If this parameter
is disabled, the video timing outputs will be generated based on only the first
detected input format. The output for the generated synchronization signals will
continue even if the detection block loses lock. This parameter is available only
if both the Enable Generation and Enable Detection parameters are enabled.
Note: This parameter has an effect only if one or more of the source select
control register bits are set to low.
° Detection Options:
- Field ID Detection: This parameter enables or disables detecting the field id
input.
° Video Format:
- Video Mode: This parameter sets the default video format and controls the
Horizontal, Vertical and Horizontal Fine Adjustment settings below. Values of
720p, 480p, 576p, 1080p, 352x288p, 352x576p, 480x576p, 544x575p, 704x576p,
704x480p, 640x480p, 800x600p, 1024x768p, 1280x1024p, 1600x1200p or
Custom are valid. The interlaced video modes of 1080i, 480i and 576i are also
available when the Interlaced Support parameter is checked. Video Modes are
removed or added to this list based upon the sizes selected in the Max Clocks
per Line and Max Lines per Frame parameters.
- Chroma Format: This parameter sets the default value of the video format in
the GENERATOR ENCODING register at address offset 0x68. This controls the
behavior of the active_chroma_out output port.
- Chroma Parity: This parameter sets the default value of the chroma parity in the
GENERATOR ENCODING register at address offset 0x68. This controls the
behavior of the active_chroma_out output port.
° Horizontal Settings:
- Active Size: This parameter sets the default number of clock cycles per frame
(without blanking) in the GENERATOR ACTIVE_SIZE register at address offset
0x060.
- Frame Size: This parameter sets the default number of clock cycles per frame
(with blanking) in the GENERATOR HSIZE register at address offset 0x70.
- Sync Start: This parameter sets the default value of the clock cycle count during
which the horizontal sync starts in the GENERATOR HSYNC register at address
offset 0x78.
- Sync End: This parameter sets the default value of the clock cycle count during
which the horizontal sync ends in the GENERATOR HSYNC register at address
offset 0x78.
- Sync Start: This parameter sets the Field 1 default value of the line count during
which the vertical sync starts in the GENERATOR F1_VSYNC_V register at
address offset 0x8C.
- Sync End: This parameter sets the Field 1 default value of the line count during
which the vertical sync ends in the GENERATOR F1_VSYNC_V register at
address offset 0x8C.
° Active Polarity:
- Field ID: This parameter sets the polarity of the field_id_out signal. Values
of Active High or Active Low are valid. This parameter is enabled when the
Interlaced Video Support and Interlaced parameters are enabled.
- Vblank: This parameter sets the polarity of the vblank_out signal. Values of
Active High or Active Low are valid.
- Hblank: This parameter sets the polarity of the hblank_out signal. Values of
Active High or Active Low are valid.
- Vsync: This parameter sets the polarity of the vsync_out signal. Values of
Active High or Active Low are valid.
- Hsync: This parameter sets the polarity of the hsync_out signal. Values of
Active High or Active Low are valid.
- Active Video: This parameter sets the polarity of the active_video_out
signal. Values of Active High or Active Low are valid.
- Active Chroma: This parameter sets the polarity of the active_chroma_out
signal. Values of Active High or Active Low are valid.
- Frame Sync # Horizontal Position: These parameters set the default value of
the clock cycle count during which Frame Sync # is active in the FRAME SYNC
0-15 CONFIG registers at address offset 0x100-0x13c.
- Frame Sync # Vertical Position: These parameters set the default value of the
line count during which Frame Sync # is active in the FRAME SYNC 0-15
CONFIG registers at address offset 0x100-0x13c.
Note: The parameter values within the Constant/Default Timing Generation Options will also be
the values used during timing generation when the Include AXI4-Lite Register Interface parameter is
disabled. These parameter values will be used when the core is in constant mode when it does not
have an AXI4-Lite interface.
In simulation, look at the VTC output. Note that the pixel clock for 720p should be
74.5 MHz, equivalent to a period of 13.4 ns.
By default, the blanking signal rises at the same clock edge the last active video signal (of
a frame) falls and falls at the same clock edge the first active video signal (of a frame) rises.
Also by default, the vsync signals rises and falls at the same clock edge as a rising edge of
the 6th rising edge of the hblank signal.
X-Ref Target - Figure 4-6
Both behaviors are because only the Vertical timing in Lines count are configured, not in
pixel count, defined in the video timing specifications.
But, for whatever reason, you might want to slightly change the configuration to move the
Vertical blanking or Sync signals. Use the Horizontal Fine Adjustment Settings to do so.
Now check the VTC outputs in simulation and regenerate the IP output products.
Notice that the blanking signal rises 67 ns after the active out signal falls. This correspond
to 5 pixel clock periods. Taking the time from the last hblank signals of the active frame
(indicating the last line), it corresponds to 1285 pixel clock periods (active size + 5).
X-Ref Target - Figure 4-8
Notice that blanking signal falls 67 ns before the active out signal rises. This correspond to
5 pixel clock periods. Taking the time from the last hblank signals during the vertical
blanking, it corresponds to 1645 pixel clock periods (horizontal frame size - 5).
Notice that the vsync signal rises when the 5th falling edge of the hblank signal when the
vertical blanking signals occur.
And the vsync signal falls 5 clock cycles before the rising edge of a hblank.
X-Ref Target - Figure 4-12
In summary, the Horizontal Fine adjustment allows you to move the Vertical timing signals
in clock cycle precision while it is usually defined in Line precision.
Output Generation
Vivado generates the files necessary to build the core and place those files in the
<project>/<project>.srcs/sources_1/ip/<core> directory.
File Details
The Vivado tools output consists of some or all the following files.
Required Constraints
The only constraints required are clock frequency constraints for the video clock, clk, and
the AXI4-Lite clock, s_axi_aclk. Paths between the two clock domains should be
constrained with a max_delay constraint and use the datapathonly flag, causing setup
and hold checks to be ignored for signals that cross clock domains. These constraints are
provided in the XDC constraints file included with the core.
Simulation
This chapter contains information about simulating IP in the Vivado® Design Suite
environment. For comprehensive information about Vivado simulation components, as well
as information about using supported third party tools, see the Vivado Design Suite User
Guide: Logic Simulation (UG900) [Ref 6].
Test Bench
This chapter contains information about the provided test bench in the Vivado® Design
Suite environment.
• axi4lite_mst.v
• axi4s_video_mst.v
• axi4s_video_slv.v
• ce_generator.v
• tb_<IP_instance_name>.v
• DUT
• axi4lite_mst
The AXI4-Lite master module, which initiates AXI4-Lite transactions to program core
registers.
• axi4s_video_mst
The AXI4-Stream master module, which generates ramp data and initiates AXI4-Stream
transactions to provide video stimuli for the core and can also be used to open stimuli
files and convert them into corresponding AXI4-Stream transactions.
a. Add define macro for the stimuli file name and directory path
define STIMULI_FILE_NAME<path><filename>.
b. Comment-out/remove the following line:
MST.is_ramp_gen(`C_ACTIVE_ROWS, `C_ACTIVE_COLS, 2);
and replace with the following line:
MST.use_file(`STIMULI_FILE_NAME);
• axi4s_video_slv
The AXI4-Stream slave module, which acts as a passive slave to provide handshake
signals for the AXI4-Stream transactions from the core output, can be used to open the
data files and verify the output from the core.
a. Add define macro for the golden file name and directory path
define GOLDEN_FILE_NAME “<path><filename>”.
b. Comment out the following line:
SLV.is_passive;
and replace with the following line:
SLV.use_file(`GOLDEN_FILE_NAME);
• ce_gen
Simulation
A highly parameterizable test bench was used to test the Video Timing Controller core.
Testing included the following:
• Register accesses
• Processing of multiple frames of data
• Testing of various frame sizes including 1080p, 720p, and 480p
• Varying instantiations of the core
• Varying the polarity of input and output signals
• Varying the horizontal offset of the vertical timing signals
• Regenerating the input on the output
• Testing of various interrupts
Hardware Testing
The Video Timing Controller core has been tested in a variety of hardware platforms at
Xilinx® to represent a variety of parameterizations, including the following:
• A test design was developed for the core that incorporated a MicroBlaze™ processor,
AXI4 Interconnect and various other peripherals. The software for the test system
included live video input for the Video Timing Controller core. The Video Timing
Controller, in addition to live video, was also connected in loopback allow the
generator to feed the detector for a robust loopback test. Various tests could be
supported by varying the configuration of the Timing Controller core or by loading a
different software executable. The MicroBlaze processor was responsible for:
° Initializing the HDMI/DVI input and output cores for live video.
° Configuring the Video Timing Controller for various input frame sizes and checking
the detection/generation loopback connection for correct video detection
Upgrading
This appendix contains information about migrating from an ISE design to the Vivado
Design Suite, and for upgrading to a more recent version of the IP core. For customers
upgrading their IP core, important details (where applicable) about any port changes and
other impact to user logic are included.
Parameter Changes
The Video Timing Controller v5.00.a added parameters for configuring the core in constant
mode, thus the core can be initialized to generate timing after reset without a processor or
software.
Port Changes
The Video Timing Controller v5.00.a removed all GPP interface ports. The Video Timing
Controller v4.00.a.0 added the ability to operate on video frame sizes up to 8192 x 8192.
Previous versions supported 4096 x 4096 maximum. If the maximum sizes of 8192 are
selected, some GPP ports will be 13 bits wide where on previous versions of the core, these
ports were 12 bits.
The Video Timing Controller v4.00.a also added the ability to detect and generate vertical
signals with a horizontal offset. In order to report the horizontal start cycle of these vertical
signals, the Video Timing Controller v4.00.a added the following new ports:
• gen_v0blank_hstart
• gen_v0blank_hend
• gen_v0sync_hstart
• gen_v0sync_hend
• det_v0blank_hstart
• det_v0blank_hend
• det_v0sync_hstart
• det_v0sync_hend
Other Changes
Migrating to the AXI4-Lite Interface
The Video Timing Controller v4.00.a changed from the PLB processor interface to the
AXI4-Lite interface. As a result, all of the PLB-related connections have been replaced with
an AXI4-Lite interface. For more information, see the AXI Reference Guide [Ref 1].
Functionality Changes
The Video Timing Controller v5.00.a AXI4-Lite register definitions changed from the
previous version, simplifying the address map. The Video Timing Controller v5.00.a also
added parameters for configuring the core in constant mode, thus the core can be
initialized to generate timing after reset without a processor or software. The Video Timing
Controller v3.0 added the ability to operate on video frame sizes up to 8192 x 8192.
Previous versions supported 4096 x 4096 maximum.
The Video Timing Controller v3.0 also added the ability to detect and generate vertical
signals with a horizontal delay offset.
Debugging
This appendix includes details about resources available on the Xilinx Support website and
debugging tools.
Documentation
This product guide is the main document associated with the Video Timing Controller. This
guide, along with documentation related to all products that aid in the design process, can
be found on the Xilinx Support web page or by using the Xilinx Documentation Navigator.
Download the Xilinx Documentation Navigator from the Downloads page. For more
information about this tool and the features available, open the online help after
installation.
Answer Records
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that users have access to the
most accurate information available.
Answer Records for this core are listed below, and can also be located by using the Search
Support box on the main Xilinx support web page. To maximize your search results, use
proper keywords such as
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
AR 54541
http://Xilinx Support web page/answers/54541.htm
Technical Support
Xilinx provides technical support in the Xilinx Support web page for this LogiCORE™ IP
product when used as described in the product documentation. Xilinx cannot guarantee
timing, functionality, or support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
Xilinx provides premier technical support for customers encountering issues that require
additional assistance.
To contact Xilinx Technical Support, navigate to the Xilinx Support web page.
1. Open a WebCase by selecting the WebCase link located under Support Quick Links.
• A block diagram of the video system that explains the video source, destination and IP
(custom and Xilinx) used.
Note: Access to WebCase is not available in all cases. Please login to the WebCase tool to see your
specific support options.
Debug Tools
There are many tools available to address Video Timing Controller design issues. It is
important to know which tools are useful for debugging various situations.
Example Design
The Video Timing Controller is delivered with an example test bench. Information about the
example test bench can be found in Chapter 6, Example Design for the Vivado Design Suite.
functionality in the Vivado IDE that is used for logic debugging and validation of a design
running in Xilinx FPGA devices in hardware.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores,
including:
Reference Boards
Various Xilinx development boards support Video Timing Controller. These boards can be
used to prototype designs and establish that the core can communicate with the system.
° KC705
° ZC702
License Checkers
If the IP requires a license key, the key must be verified. The Vivado tool flows have a
number of license check points for gating licensed IP through the flow. If the license check
succeeds, the IP may continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:
• RDS
• RDI
• Bitgen
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This
section provides debug steps for common issues. The ChipScope tool is a valuable resource
to use in hardware debug. The signal names mentioned in the following individual sections
can be probed using the ChipScope tool for debugging the specific problems.
Many of these common issues can also be applied to debugging design simulations. Details
are provided on General Checks
General Checks
Ensure that all the timing constraints for the core were properly incorporated from the
example design and that all constraints were met during implementation.
• Does it work in post-place and route timing simulation? If problems are seen in
hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all
clock sources are active and clean.
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by
monitoring the LOCKED port.
• If your outputs go to 0, check your licensing. The evaluation version of the core will
time out after running for 8 hours at 75 MHz.
YUV
Interface Debug
AXI4-Lite Interfaces
Table C-1 describes how to troubleshoot the AXI4-Lite interface.
Assuming the AXI4-Lite interface works, the second step is to bring up the AXI4-Stream
interfaces.
Other Interfaces
Table C-2 describes how to troubleshoot third-party interfaces.
Additional Resources
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see the
Xilinx Support website at:
https://www.xilinx.com/support/documentation/sw_manuals/glossary.pdf.
For a comprehensive listing of Video and Imaging application notes, white papers,
reference designs and related IP cores, see the Video and Imaging Resources page at:
https://www.xilinx.com/esp/video/refdes_listing.htm#ref_des.
• From the Vivado IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other
topics, which you can use to learn key concepts and address frequently asked questions. To
access the Design Hubs:
• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.
References
These documents provide supplemental material useful with this user guide:
Revision History
The following table shows the revision history for this document.