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DDVH Testbench Codes

Testbench code for n bit alu

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raiedhamane369
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10 views

DDVH Testbench Codes

Testbench code for n bit alu

Uploaded by

raiedhamane369
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

Half Adder :

module Half_Adder_tb( );
reg a,b;
wire s,c;
Half_Adder dut (.a(a),.b(b),.s(s),.c(c));
initial
begin
a=1'b0;b=1'b0;
#10;
a=1'b0 ; b=1'b1;
#10;
a=1'b1 ; b=1'b0;
#10;
a=1'b1 ; b=1'b1;
#10;
end
endmodule
4-bit Full Adder:
module FA_4bit_tb();
reg [3:0]a;
reg [3:0]b;
reg cin;
wire [3:0]s;
wire cout;
FA_4bit dut(.a(a),.b(b),.cin(cin),.s(s),.cout(cout));
initial
begin
a=4'b0000;b=4'b0111;cin=0; #5;
a=4'b0011;b=4'b0001;cin=1; #5;
a=4'b1011;b=4'b0001;cin=1; #5;
a=4'b1111;b=4'b1001;cin=0; #5;
$stop;
end
endmodule
D Flip-Flop:
module D_FF_rst_tb();
reg clk,rst,D;
wire Q;
D_FF_rst dut (.D(D),.clk(clk),.rst(rst),.Q(Q));
initial
begin
clk=0;
forever
#5 clk=~clk;
end
initial
begin
rst=0; #10;
rst=1; #20;
end
initial
begin
D=1'b1; #30;
D=1'b0; #20;
end
endmodule
Up-Down Counter:
module up_down_tb( );
reg clk,reset,select;
wire [3:0]count;
up_down dut (.clk(clk),.reset(reset),.select(select),.count(count));
initial
begin
clk=0;
forever
#5 clk=~clk;
end
initial
begin
reset=1; #20;
reset=0;
end
initial
begin
select=0; #100;
select=1;
end
endmodule
8:1 Mux:
module mux8_1_tb( );
reg [7:0] a;
reg [2:0] s;
wire y;
mux8_1 dut (.a(a), .s(s), .y(y) );
initial
begin
a = 8'b10101010;
s = 3'b000; #10;
s = 3'b001;#10;
s = 3'b010;#10;
s = 3'b100;#10;
s = 3'b111;#10;
$stop;
end
endmodule
Decoder:
module tb_Dec2_4();
reg [1:0] A;
reg en;
wire [3:0] D;
Dec2_4 dut (.A(A), .D(D), .en(en));
initial
begin
en = 0;#10;
en = 1;
A = 2'b00; #10;
A = 2'b01; #10;
A = 2'b10; #10;
A = 2'b11; #10;
$stop;
end
endmodule
4-bit Counter:
module Counter_tb();
reg clk;
reg rst;
wire [3:0]Q;
Counter dut(.clk(clk),.rst(rst),.Q(Q));
initial
begin
clk = 0;
forever
#5 clk = ~clk;
end
initial
begin
rst = 0;#10;
rst = 1;#100;
#50;
$stop;
end
endmodule

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