3.3.

5 RISC & CISC processors

3.3.5 RISC processors
• show understanding of the differences between RISC and CISC processors
• show understanding of the importance/use of pipelining and registers in RISC processors
• show understanding of interrupt handling on CISC and RISC processors

Resources:
https://www.youtube.com/watch?v=BJpMmq9gQE8
https://www.youtube.com/watch?v=a4kgtygCZBc
Notes on CISC:

http://en.wikipedia.org/wiki/Complex_instruction_set_computer

Notes on RISC:

http://en.wikipedia.org/wiki/RISC

Detailed notes on CPU and multi-processors (including pipelining):

http://en.wikipedia.org/wiki/CPU#Microprocessors

RISC versus CISC explanations:

http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/

www.eastaughs.fsnet.co.uk/cpu/further-ciscrisc.htm

www.teach-ict.com/as_as_computing/ocr/H447/F453/3_3_3/parallel_processors/miniweb/pg7.htm

Simple quiz:

www.eastaughs.fsnet.co.uk/cpu/further-quiz.htm

How microprocessors work:

http://computer.howstuffworks.com/microprocessor.htm
RISC Processor

CISC Processor
What is The Difference
Between RISC and CISC
Architecture?
The architecture of the Central Processing Unit (CPU) operates the capacity to function from
“Instruction Set Architecture” to where it was designed. The architectural design of the CPU is
Reduced instruction set computing (RISC) and Complex instruction set computing (CISC).

CISC has the capacity to perform multi-step operations or addressing modes within one
instruction set. It is the CPU design where one instruction works several low-level acts.

For instance, memory storage, loading from memory, and an arithmetic operation. Reduced
instruction set computing is a Central Processing Unit design strategy based on the vision that
basic instruction set gives a great performance when combined with a
microprocessor architecture which has the capacity to perform the instructions by using some
microprocessor cycles per instruction.
RISC
(reduced instruction set computer) is a microprocessor that is designed to perform a smaller
number of types of computer instructions so that it can operate at a higher speed (perform
more millions of instructions per second, or MIPS).

RISC Architecture
The term RISC stands for ‘’Reduced Instruction Set Computer’’. It is a CPU design plan based
on simple orders and acts fast.

RISC Architecture

This is small or reduced set of instructions. Here, every instruction is expected to attain very
small jobs. In this machine, the instruction sets are modest and simple, which help in
comprising more complex commands. Each instruction is of the similar length; these are
wound together to get compound tasks done in a single operation. Most commands are
completed in one machine cycle. This pipelining is a crucial technique used to speed up
RISC machines.

What is CISC?
A complex instruction set computer is a computer where single instructions can perform
numerous low-level operations like a load from memory, an arithmetic operation, and a
memory store or are accomplished by multi-step processes or addressing modes in single
instructions, as its name proposes “Complex Instruction Set ”.

CISC Architecture
The term CISC stands for ‘’Complex Instruction Set Computer’’. It is a CPU design plan based
on single commands, which are skilled in executing multi-step operations.

CISC Architecture

CISC computers have small programs. It has a huge number of compound instructions,
which takes a long time to perform. Here, a single set of instruction is protected in several
steps; each instruction set has additional than 300 separate instructions. Maximum
instructions are finished in two to ten machine cycles. In CISC, instruction pipelining is not
easily implemented.
 RISC CISC
1. RISC stands for Reduced Instruction Set Computer. 1. CISC stands for Complex Instruction Set Computer.

2. RISC processors have simple instructions taking about 2. CSIC processor has complex instructions that take up
one clock cycle. The average clock cycle per instruction multiple clocks for execution. The average clock cycle
(CPI) is 1.5 per instruction (CPI) is in the range of 2 and 15.

3. Performance is optimized with more focus on

3. Performance is optimized with more focus on software hardware.

4. It has no memory unit and uses a separate hardware to 4. It has a memory unit to implement complex
implement instructions.. instructions.

5. It has a hard-wired unit of programming. 5. It has a microprogramming unit.

6. The instruction set is reduced i.e. it has only a few

instructions in the instruction set. Many of these 6. The instruction set has a variety of different
instructions are very primitive. instructions that can be used for complex operations.

7. CISC has many different addressing modes and can

7. The instruction set has a variety of different thus be used to represent higher-level programming
instructions that can be used for complex operations. language statements more efficiently.

8. Complex addressing modes are synthesized using the

software. 8. CISC already supports complex addressing modes

9. Multiple register sets are present 9. Only has a single register set

10. RISC processors are highly pipelined 10. They are normally not pipelined or less pipelined

11. The complexity of RISC lies with the compiler that

executes the program 11. The complexity lies in the microprogram

12. Execution time is very less 12. Execution time is very high

13. Code expansion can be a problem 13. Code expansion is not a problem

14. Decoding of instructions is simple. 14. Decoding of instructions is complex

15. It does not require external memory for calculations 15. It requires external memory for calculations

16. The most common RISC microprocessors are Alpha, 16. Examples of CISC processors are the System/360,
ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power VAX, PDP-11, Motorola 68000 family, AMD and Intel
Architecture, and SPARC. x86 CPUs.

17. RISC architecture is used in high-end applications

such as video processing, telecommunications and image 17. CISC architecture is used in low-end applications
processing. such as security systems, home automation, etc.
Difference between RISC and CISC Architecture

Difference between RISC and CISC

Parallel Processing
https://www.youtube.com/watch?v=tZQOjC1V8LE

Define parallel processing (the simultaneous use of several processors to perform a single
job).
Compare this to the Von Neumann computer.

Provide pre-determined scenarios of the use of parallel processing (e.g. weather forecasting,
processing live images from a satellite, artificial intelligence). (W)

Resources:
Link to notes on parallel processing (sections 1–6):
www.teach-
ict.com/as_as_computing/ocr/H447/F453/3_3_3/parallel_processors/miniweb/index.htm
Question 1
Describe the differences between reduced instruction set computing processors (RISC) and
complex instruction set computing processors (CISC)

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Question 2
Describe the importance and use of pipelining and registers in RISC processors
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Question 3
Describe interrupt handling on CISC and RISC processors
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November 2018 Paper 32 Question 5

Answer
Answer
Answer
Answer

NOVEMBER 2017 PAPER 31/33

Marking scheme
NOVEMBER 2017 PAPER 32
Marking Scheme: November 2017 P 32 Q 2
 NOVEMBER 2015 PAPER 31/33
4 (a) Three descriptions and two types of processor are shown below. Draw a line to connect
each description to the appropriate type of processor.

[3]
Marking Scheme: November 2015 P 31/33 Q 4
JUNE 2019 PAPER 32
ANSWER
ANSWER