06 A15 5C4 2C8 806 4EAA68 2DAAFB BA0 22B

A 4 2
6A 15C C42 2C80 064 EA6 682 DA FBAA02 22B4 445
15 42 C8 64 EA 82 DA FB 02 2B 45 270
15 C42 C8 064 EA 682 DA FB A02 2B 445 270 6A
C 0 6 A 4 1
5C 42C C80 64E EA6 82DDAF FBA 022 2B4 452 2706 6A1 5C4
4 8 6 4 A 8 2 A B 0 B 4 5 7 0 A 5
C4 2C 06 EA 68 DA FB A0 22B 44 27 6A 15 C42 2C8
2 8 4 2 2 5 0 C 0

Q6.
Q5.
Q.4
42 C80 064E EA6 682DDA FBAA02 2B4 4452 270 6A1 15C 42C C806 64E

Q. 3
Q. 2
Q. 1
C8 64 A 82 A FB 0 2B 45 70 6A 5C 42 80 4E A6
C8 064 EA 682 DA FB A0 22B 445 270 6A 15C 42 C80 64E A6 82D
0 6 A 2 4 1 C
80 64E EA6 82DDAF FBA 022 2B4 452 2706 6A1 5C4 42C 806 64EAA68 82D AFB

B)
B)
B)
B)
B)

A)
A)
A)
A)
A)
64 A 82 A BA 02 B 45 70 A 5C 2C 80 4E 6 2D AF A
06 EA 68 DA FB 0 2B 44 27 6A 15 42 8 64 A 82 A B 02
4E 6 2D F A 2 4 52 0 1 C C 06 E 68 D F A 2
4E A6 82D AF BA 022 2B4 452 706 6A1 5C4 42C 806 4EAA68 2DAAFB BA0 022B B44
Max Marks: 60

A6 82D AF BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D F A 22 44 527

82 A BA 02 2B 45 70 6A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06
DA FB 0 2B 44 27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A1
FB A0 22B 44 527 06A 15C C42 C80 064 EA6 682 DA FBA 02 2B4 445 270 6A1 5C

diagram.
A0 22B 44 527 06A 15 42 C8 64 EA 82 DA FB 02 2B 45 270 6A 5C 42C
22 44 527 06 15 C4 C8 064 EA 682 DA FB A0 2B 445 27 6A 15C 42 80
B4 52 06 A1 C 2C 06 E 68 D F A 22 44 27 06 15 4 C8 64
45 70 A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06 A1 C4 2C 06 EA
27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A 5C 2C 80 4E 6
06 15 C4 C8 06 EA 68 DA FB 0 2B 44 27 6A 15 42 8 64 A 82
Instructions to the Students:

A1 C 2C 06 4E 68 2D F A 22 44 52 06 15 C4 C8 06 EA 68 DA

architecture style.
5C 42C 80 4E A6 2D AF BA 022 B4 52 706 A1 C4 2C 06 4EA 68 2D FB

(a) Half-adder
42 80 64E A6 82D A BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D AF A

Define and explain:

C8 64 A 82 A FB 0 2B 45 70 6A 5C 42 80 4E A6 2D AF BA 02
06 EA 68 DA FB A0 22B 44 27 6A 15 42 C8 64 A 82 A B 02 2B
Subject Name: Digital Logic design

4E 6 2D F A 22 4 52 06 1 C4 C 06 EA 68 DA FB A0 2B 44
A6 82D AF BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D F A 22 44 527
82 A BA 02 2B 45 70 6A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06
DA FB 0 2B 44 27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A1

F1 (A,B,C)= ∑ m(0, 2,6,7 )

FB A0 22B 44 527 06A 15C C42 C80 064 EA6 682 DA FBA 02 2B4 445 270 6A1 5C

F2(A,B,C)= ∑ m(1, 3,4,5,7 )

A0 22B 44 527 06A 15 42 C8 64 EA 82 DA FB 02 2B 45 270 6A 5C 42C
22 44 527 06 15 C4 C8 064 EA 682 DA FB A0 2B 445 27 6A 15C 42 80
B4 52 06 A1 C 2C 06 E 68 D F A 22 44 27 06 15 4 C8 64
45 70 A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06 A1 C4 2C 06 EA
based is mentioned in ( ) in front of the question.

27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A 5C 2C 80 4E 6
06 15 C4 C8 06 EA 68 DA FB 0 2B 44 27 6A 15 42 8 64 A 82
A1 C 2C 06 4E 68 2D F A 22 44 52 06 15 C4 C8 06 EA 68 DA
Implement following using multiplexer

5C 42C 80 4E A6 2D AF BA 022 B4 52 706 A1 C4 2C 06 4EA 68 2D FB

42 80 64E A6 82D A BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D AF A
C8 64 A 82 A FB 0 2B 45 70 6A 5C 42 80 4E A6 2D AF BA 02
Draw and explain Universal shift Register.

06 EA 68 DA FB A0 22B 44 27 6A 15 42 C8 64 A 82 A B 02 2B
Simplify following expression using K-Map

4E 6 2D F A 22 4 52 06 1 C4 C 06 EA 68 DA FB A0 2B 44
A6 82D AF BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D F A 22 44 527
82 A BA 02 2B 45 70 6A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06
2. Use of non-programmable scientific calculators is allowed.

DA FB 0 2B 44 27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A1
FB A0 22B 44 527 06A 15C C42 C80 064 EA6 682 DA FBA 02 2B4 445 270 6A1 5C
A0 22B 44 527 06A 15 42 C8 64 EA 82 DA FB 02 2B 45 270 6A 5C 42C
Date:10/12/2018

22 44 527 06 15 C4 C8 064 EA 682 DA FB A0 2B 445 27 6A 15C 42 80

Course: B. Tech. in Electronics and Telecommunication Engineering

f (A,B,C,D) = ∑m (1,4,7,12,13, 14,15) + d (0, 5, 8)

3. Assume suitable data wherever necessary and mention it clearly.

(b) Half-subtractor

B4 52 06 A1 C 2C 06 E 68 D F A 22 44 27 06 15 4 C8 64
Design 3-bit synchronous up counter using JK flip flop.

45 70 A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06 A1 C4 2C 06 EA
27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A 5C 2C 80 4E 6

4452706A15C42C8064EA682DAFBA022B
06 15 C4 C8 06 EA 68 DA FB 0 2B 44 27 6A 15 42 8 64 A 82

Draw Asynchronous 4 bit up counter with clock waveform.

A1 C 2C 06 4E 68 2D F A 22 44 52 06 15 C4 C8 06 EA 68 DA
5C 42C 80 4E A6 2D AF BA 022 B4 52 706 A1 C4 2C 06 4EA 68 2D FB
End Semester Examination – Winter 2018

42 80 64E A6 82D A BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D AF A

Write VHDL code for Mux 4:1 using dataflow and behavioural
C8 64 A 82 A FB 0 2B 45 70 6A 5C 42 80 4E A6 2D AF BA 02

Implement given Boolean functions using PLA, PAL and PROM

06 EA 68 DA FB A0 22B 44 27 6A 15 42 C8 64 A 82 A B 02 2B
Draw state diagram for given sequential circuit shown in figure 1.

4E 6 2D F A 22 4 52 06 1 C4 C 06 EA 68 DA FB A0 2B 44

i)Fan in and Fan out ii) Noise immunity iii) Propagation Delay
A6 82D AF BA 02 B4 452 70 A1 5C 2C 806 4E 68 2D F A 22 44 527

Explain in brief the operation of CMOS NAND Gate with schematic

82 A BA 02 2B 45 70 6A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06

Draw combinational circuit for Binary Parallel Adder and Subtractor.

DA FB 0 2B 44 27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A1

************************The End**************************
FB A0 22B 44 527 06A 15C C42 C80 064 EA6 682 DA FBA 02 2B4 445 270 6A1 5C
A0 22B 44 527 06A 15 42 C8 64 EA 82 DA FB 02 2B 45 270 6A 5C 42C
22 44 527 06 15 C4 C8 064 EA 682 DA FB A0 2B 445 27 6A 15C 42 80
B4 52 06 A1 C 2C 06 E 68 D F A 22 44 27 06 15 4 C8

(3)
(4)
(2)
(2)
45 70 A 5C 42C 80 4E A6 2D AF BA 022 B4 52 06 A1 C4 2C 06

(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(1,2)
(1,2)

27 6A 15 42 8 64 A 82 A BA 02 B 45 70 A 5C 2C 80
(COs)

06 15 C4 C8 06 EA 68 DA FB 0 2B 44 27 6A 15 42 8 64
DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE

A1 C 2C 06 4E 68 2D F A 22 44 52 06 15 C4 C8 06
5C 42C 80 4E A6 2D AF BA 022 B4 52 706 A1 C4 2C 06 4E
42 80 64E A6 82D A BA 02 B4 452 70 A1 5C 2C 806 4E
C8 64 A 82 A FB 0 2B 45 70 6A 5C 42 80 4E A6
06 EA 68 DA FB A0 22B 44 27 6A 15 42 C8 64 A
4E 6 2D F A 22 4 52 06 1 C4 C 06 EA 68
A6 82D AF BA 02 B4 452 70 A1 5C 2C 806 4E 68

06
06
06
06
06
06
12
06
06
06
06
Sem: III

82 A BA 02 2B 45 70 6A 5C 42C 80 4E A6 2
1. The level question/expected answer as per OBE or the Course Outcome (CO) on which the question is

DA FB 0 2B 44 27 6A 15 42 8 64 A 82
Duration: 3 Hr.

Marks
Subject Code: BTEXC305

FB A0 22B 44 527 06A 15C C42 C80 064 EA6 682 D

http://www.batuonline.com
A0 22B 44 527 06A 15 42 C8 64 EA 82 DA
22 44 527 06 15 C4 C8 064 EA 682 DA
B4 52 06 A1 C 2C 06 E 68 D F
45 70 A 5C 42C 80 4E A6 2D AF
27 6A 15 42 8 64 A 82 A B
0 1 C C 06 E 68 D F