This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2499194, IEEE
Transactions on Power Electronics

A Multi-Mode 1 MHz PFC Front End with Digital

Peak Current Modulation
Ryan Fernandes, Student Member, IEEE and Olivier Trescases, Senior Member, IEEE
Department of Electrical and Computer Engineering, University of Toronto
10 King’s College Road, Toronto, ON, M5S 3G4, Canada

DBridge LB IL DBoost
Abstract—This work presents a novel mixed-signal control Iline Vout
Vline
scheme for a boost Power Factor Correction (PFC) rectifier. The V V
+ x +
+ EMI + in c[n]
digital controller modulates the inductor peak current to produce Vac Cin Mn Cout Rload
Filter
a low-distortion ac line current in Discontinuous Conduction - - - -
Mode (DCM) and Continuous Conduction Mode (CCM), without Vn Vss
the need for average current sensing. A Lookup Table (LUT)
optimizes efficiency at low input currents, by allowing operation
at 125-500 kHz DCM based on calculated thresholds. At high Fig. 1. Power stage of the boost PFC rectifier.
input currents, the converter operates at 1 MHz CCM for reduced
inductor footprint. An analog off-time generator with a digital Iline
frequency locked loop facilitates CCM operation, eliminating the Vline
need for slope compensation in the current loop and reduces +
frequency variations. The LUT is programmed with an adaptive Vac
output voltage of 250/450 V for low/high mains line voltage (85- -
265 Vrms ) to optimize efficiency over a broad range of conditions. Vn
The 150 W PFC prototype operates up to 1 MHz with a peak
efficiency of 95% and a THD of 5%. Fig. 2. Two-stage PFC system application.
Index Terms—ac-dc power conversion, switched mode power
supplies, current control, frequency locked loops, digital control,
digital modulation.
B. Conduction Modes
Corresponding Author Boost PFC rectifiers have been demonstrated with a vari-
Ryan Fernandes ety of operating modes, including Discontinuous Conduction
Tel: +1 647 618 6190 Mode (DCM) [2,3], Continuous Conduction Mode (CCM) [4,
E-mail: [email protected] 5], Boundary Conduction Mode (BCM) [6,7] and Mixed Con-
duction Mode (MCM) [8–10]. Ideal inductor waveforms for
I. I NTRODUCTION
DCM, BCM, and CCM are shown in Fig. 3. The peak and
Power Factor Correction (PFC) is required for nearly all average inductor current are defined as Ipeak and Iavg , re-
modern grid-connected loads. Industry standards such as IEC spectively.
61000-3-2 and IEEE Std 519 [1] dictate the harmonic regula- Converters designed for CCM operation have the highest
tion limits, including Total Harmonic Distortion (THD). One switching losses due to hard-switching of the MOSFET, which
approach to reduce the volume of conventional boost PFC rec- is partially compensated by reduced inductor core loss due
tifiers is to employ new wide-bandgap devices, such as 600V to low ripple current. BCM based converters have reduced
Gallium Nitride (GaN) switches, to permit higher switching turn-on losses due to Zero Voltage Switching (ZVS) [11].
frequencies and smaller passive components. Maintaining a However, BCM results in a moderately large Ipeak , because
high efficiency and low THD while scaling up the switching Ipeak = 2Iavg , which increases the inductor saturation current
frequency is a major challenge that is addressed in this work requirement and the core loss. DCM based converters have the
by utilizing a new digital control design that eliminates the largest peak current, as Ipeak > 2Iavg , resulting in the highest
need for average current sensing. core loss.
A. Architecture of the Boost PFC Rectifier In MCM operation the converter dynamically switches be-
tween two or more modes throughout the ac line cycle to opti-
The classical boost PFC rectifier is comprised of a boost mize loss, inductor requirements, and EMI filter design. MCM
converter fed by a bridge rectifier and an Electromagnetic In- converters have been proposed mainly for light-load efficiency
terference (EMI) filter, as shown in Fig. 1. The boost converter improvements by reducing the switching frequency [12], and
shapes the line current to be sinusoidal and in phase with the implementing burst-mode control [13]. Reduction of filter size
line voltage, Vac , while regulating the output load voltage, is possible with increased frequency in CCM at high line
Vout . The boost PFC front-end is typically used as part of a currents.
two-stage isolated architecture, as shown in Fig. 2.

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Transactions on Power Electronics
t t

1
iL iL L i
average current is regulated to track a sinusoidal reference, is
popular with both DCM and CCM operation. Peak Current
Mode Control (PCMC) requires a modulation algorithm to
correct for the inherent non-linearity between the peak and
average inductor current. However, there are a number of ad-
vantages in using PCMC over ACMC:
t t
Vt x • In terms of on-chip integration at low power levels, where
(a) the power MOSFET is integrated with the controller: a
iL iL senseFET can be used for peak current sensing on the
Rs
low-side MOSFET [19], without explicitly monitoring the
average inductor current. This was recently demonstrated
td,MOS for a GaN cascode structure [20].
• Conventional ACMC has a lower bandwidth than PCMC.
One technique to improve bandwidth comparable to that
t t of PCMC has the side effect of trequiring slope compen-
sation in CCM, a limitation shared by PCMC [21].
(b)
iL • When a frequency transition occurs (for example from
500 kHz DCM to 1 MHz CCM) for MCM operation, a
change in duty cycle is required to maintain the same av-
erage current. In ACMC, this disturbance requires a feed-
back response. However, in a digital modulation scheme,
the peak current can be calculated cycle-by-cycle with
t t t consideration of the switching frequency to obtain the de-
sired average current, using feed-forward. This minimizes
(c) the transient response. The effect is most pronounced for
Fig. 3. Inductor current (blue) and average inductor current (orange) for the transitions to and from DCM, where Ipeak ≥ 2Iavg .
following conduction modes: (a) DCM, (b) BCM, and (c) CCM.
Predictive current mode control is one form of modulation
that aims to predict the next duty cycle by using the current
C. Control Methods operating conditions and a target average current as modeled
in [22,23] and applied in [24, 25]. This method involves sens-
Several PFC control techniques have been demonstrated, in-
ing the average inductor current to avoid subharmonic oscilla-
cluding average current mode [14], peak current mode [15,16],
tions, which increases the system cost, as it cannot be easily
duty cycle [17], and predictive current mode control [10, 18].
t integrated on-chip, unlike [20], which has the current sensor
An inductor current waveform is shown in Fig. 4 to demon-
integrated with the PFC switch using a senseFET. Furthermore,
strate the impact of increasing the peak current, average cur-
the method used in [24] relies on sampling the current in
rent and duty cycle over 3 cycles.
the middle of the conduction interval to estimate the average
current, which is not easily scalable above 1 MHz.
iL ipeak[n+1] ipeak[n+2]
ipeak[n] Another modulation approach is to calculate the theoretical
duty cycle that is required to achieve an average current on
a cycle-by-cycle basis, based on steady-state boost converter
equations [3, 26]. This approach allows for DCM and CCM
iavg[n] iavg[n+1] iavg[n+2] operation without average current sensing.
The well-known advantages of digital control in the context
of PFC are described in [18]. However, there are numerous
t practical challenges including quantization effects and pro-
d[n] d[n+1] d[n+2] cessing delays that increase THD [18]. Mixed-signal imple-
mentations of current mode control, as targeted in this work,
t Fig. 4. Peak current (red), average current (green) and duty cycle (purple) relax this resolution requirement by having an analog peak
for an inductor current waveform. current loop, a digital current modulation algorithm and a
digital voltage loop for output voltage regulation.
Duty cycle iL control is most popular with BCM by using The goal of this iLwork is to demonstrate a novel 150 W
constant on-time modulation to obtain unity PF. In BCM, Ipeak
boost PFC rectifier front-end with the following attributes:
= 2Iavg , which implies that a sinusoidal Ipeak or ipeakconstant
[n+1] on- ipeak[n+1]
• Switching frequency up to 1 MHz to leverage future
time results in unity PF. The off-time is determined by a ZVSm
detection circuit. ipeak[n]
a wide-bandgap semiconductors
ipeak[n] and increase power den-
Average Current Mode Control (ACMC), where the sensed sity. This allows the boost inductor footprint to bemreduced
1 m2
m1 m2

Toff
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Transactions on Power Electronics

well below the industry standard of 30x30 mm. detection resolution, as it is implemented on a FPGA rather
• Mixed-signal control compatible with future on-chip im- than a micro-controller.
plementation with the GaN driver in [20], to achieve low
THD current line shaping by modulating the peak current Sine Wave Line Synchronization

in DCM and CCM on a cycle-by-cycle basis, without RMS

average current sensing. Vsin[n] Vin,HR[n]

• MCM operation with optimal mode transition thresholds

Digital Phase Locked Loop
using a Lookup Table (LUT) to improve efficiency at low
currents and reduce filter size at high currents. Combined fline
Sine
LUT
Min
Detector
Counter

with a SiC diode, efficiency is targeted within 2-3% of Phase eline[n] Integrator

competing products with up to 1 MHz operation. Vin[n]

Detector

Min Counter
• CCM operation that produces low THD, which requires Detector
accurate peak current control and low frequency variation, phase[n]

which is not possible with slope compensation.

The paper is organized as follows. The architecture and dig- Fig. 6. Sine wave line synchronization.
ital control optimization of the boost PFC rectifier are covered
in Section II. The digital peak current modulation strategy is The designed digital PLL is composed of a sine LUT, min-
described in Section III. The hardware design is covered in imum detector, and compensator, as shown in Fig. 6. The sine
Section IV. The detailed measurements for the experimental LUT contains an internal sinusoidal digital voltage, which can
prototype are presented in Section V. have its frequency and phase modified through the control
II. A RCHITECTURE AND D IGITAL C ONTROL signals fline and phase[n], respectively. The minimum detec-
O PTIMIZATION tor includes a counter that spans an entire line period, with
the purpose of storing the counter value at which a minimum
The converter specifications are summarized in Table I. A
voltage is detected. The counter positions of the minimum
block diagram of the converter is shown in Fig. 5. The detailed
detected voltages of Vsin [n] and Vin [n] are subtracted to obtain
operation of the critical functional blocks is described in this
the error signal, eline [n]. The error signal is processed by an
section.
integrator to produce phase[n], which is fed into the phase
TABLE I input of the sine LUT. This phase locking process is presented
C ONVERTER S PECIFICATIONS in Fig. 7. As Vsin [n] and Vin [n] phase align, their counters
converge.
Specification Value Unit
Input Voltage, Vline 85-265 Vrms Vin Ncount[n]

Output Voltage, Vout 250/450 V Vsin[n] Vin[n] Vin[n]

Output Power, Pout 150 W
Switching Frequency, fs 0.125-1 MHz Vsin[n]
Line Frequency, fline 50-60 Hz t t

Conduction Mode DCM/CCM - Fig. 7. Phase locking of input voltage and internally generated sine reference.
Control Method Peak Current Mode -
Controller Implementation Digital (FPGA) - The upper bound to the gain of the integrator is determined
by the minimal phase offset, θ that is allowed. The displace-
ment PF is defined as
A. Line Voltage Synchronization
A digital Phase Locked Loop (PLL) is designed to syn- P Fdp = cos(θ). (1)
chronize a high resolution sinusoidal reference, Vsin [n] with
To obtain a worst-case displacement PF of 0.9999, a max-
Vin (t), as shown in Fig. 6. This process increases the ac-
imum step size of 0.8 degrees is required. A smaller step
curacy for calculations requiring the input voltage, without
size increases accuracy at the expense of a slower settling
requiring a high resolution ADC to accurately sense Vin (t).
time. A true RMS calculation is performed on Vin [n] and the
PLLs are commonly used in photo-voltaic (PV) inverters for
result is multiplied by Vsin [n] to reconstruct a high-resolution,
grid synchronization and anti-islanding [27, 28]. Digital PLLs
sinusoidal input voltage, Vin,HR [n]. The specifications of the
have been used in power management IC applications [29,30].
input ADC are relaxed, since the inherent bit resolution is
The designed digital PLL for PFC line synchronization re-
not critical for an RMS calculation against a digital sinusoidal
sembles [31], but has a faster sampling time and better phase
reference, whereas in a traditional design the input voltage

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Transactions on Power Electronics

Input Filter Power Stage

Iline LDM1 LB IL DBoost
DBridge
Vline Vout
+ LCM CCM1
+ Vin Vx + +
Vac Ve Mn Rload
CDM1 CDM2 Cin
- - Isense(t) Cout
LDM2 Rs -
CCM2 -
Vn Vss

Voltage Sensing

Vin[n] Vout[n]
ADC ADC

kVin(t)

Digital PFC Voltage Loop

Vin,HR[n] Vref250
fmode[n] Pcmd[n] +
fline
Ipeak[n]
Vref450
Ipeak_d[n]
Current Loop Vsel
Vsel setccm[n]
fmode[n] Digital Mode Switching
clock Vout[n]
R
S
SET
Q fmode[n]
Vin,HR[n]
iDAC
Ipeak(t) S
R Q Ipeak[n]
setdcm[n] CLR

Ndiv[n]
Vsel
fmode[n]

set
Ndiv[n]
clock

Vsel
c[n] fline

Fig. 5. Simplified converter architecture.

sensing accuracy is important to extract the proper wave shape THD vs Number of Bits
of the input voltage. Voltage sensing of the input is generally 25
inaccurate due to distortion of the sensing network since large
20
MΩ resistors are used to reduce sensing power consumption,
which lowers the input current into the voltage amplifier. It
THD (%)

15
is noted that from the Point of Common Coupling (PCC),
10
the voltage THD can be as high as 5-8% based on IEEE
Standard 519-1992 and IEC-61000-2-4, reducing the accuracy 5

of this method slightly. To quantify the benefits of having an 0

internal high resolution reference, the distortion power factor 0 2 4 6 8 10 12 14
Number of Bits (N)
is defined:
(a)
1
P Fds = √ . (2) Distortion PF vs Number of Bits
1 + T HD2
1.005
A plot of the THD and distortion PF versus Number of
Distortion Power Factor

1
Bits (N) used for the DAC is shown in Fig. 8. In this work,
0.995
12 bits are used for the DAC, while the internal resolution for
0.99
calculations is 16 bits to avoid round off error. Vin [n] on its
own would produce a THD of 0.32% at the maximum input 0.985

current because it reduces the effective resolution to 8-bits. 0.98

By creating a high resolution reference, Vin,HR [n], full 12-bit 0.975

0 2 4 6 8 10 12 14
precision is obtained, for a THD of 0.02% at the maximum
Number of Bits (N)
input current. Reduced resolution of the ADC and DAC can
be used if a smaller digital core and lower cost components (b)
are desired, while maintaining acceptable THD. Fig. 8. The effect of number of bits used in the peak current DAC on
(a) THD, and (b) distortion power factor.

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Transactions on Power Electronics

TABLE II
B. Frequency and Mode Switching THD R ESULTS F ROM A C LIPPED S INE WAVE
To take advantage of digital control for improved efficiency
and size reduction, an adaptive frequency and mode-switching Line Voltage Clipping Voltage THD
scheme is implemented. This scheme increases fs at heavy 85 Vrms 20 V 1.61%
loads in order to reduce the inductor peak current, which
120 Vrms 20 V 0.60%
translates to size reduction, and reduces fs at light loads to
optimize efficiency by lowering the switching losses. 230 Vrms 40 V 0.67%
An advantage of reducing fs is that there is a higher Ipeak 265 Vrms 40 V 0.44%
to maintain the same Iavg , which reduces the bandwidth and
noise requirements on the current sensor [32]. The minimum
peak current setting on the DAC is clamped at 100 mA, since 2) At 125 kHz and 250 kHz there is a peak current limit
lower currents cannot accurately be resolved by the current of 1 A and 1.2 A, respectively, as shown in Fig. 10 that
sensor used in this design. The determination of the switch- has been imposed by the design.
ing frequency and mode of operation is processed through a 3) For a given frequency, input voltage and output voltage
FSM, as shown in Fig. 9. The selection of fs is based on the there is a maximum peak current to retain DCM opera-
operating conditions, which comprises of Vin , Vout and Ipeak . tion.
When Vin (t) is less than 20 V or 40 V for an output voltage
of 250 V or 450 V, respectively, the converter enters the first Peak Current Threshold Levels of each Frequency
1.4
mode of operation; constant peak current mode. At these input
voltages the boost ratio is above ten, and the corresponding 1.2
di/dt levels are too low to overcome the capacitance of the
Vx node in a switching cycle. As such, the power that is 1
consumed in this region is wasted with the only purpose of
Peak Current (A)
decreasing THD and improving zero crossing detection for 0.8

line synchronization. The other frequency modes are 125 kHz

0.6
DCM, 250 kHz DCM, 500 kHz DCM, and 1 MHz CCM.
0.4
Frequency Switching
fs = 125kHz
0.2 fs = 250kHz
Vout[n-1] Finite State Machine
z-1 fs = 500kHz
Constant fs fs = 1MHz
Vout[n] dvdt
+ Peak 0
0 20 40 60 80 100 120 140 160 180 200
Vs>0.1Vo Input Voltage (V)
Ip>Im Ip>Im
Ipeak[n] 500 kHz fmode[n] (a)
125 kHz 250 kHz
DCM DCM DCM
Vin,HR[n] Peak Current Threshold Levels of each Frequency
Ip>Im Ndiv[n] 2.5

1 MHz
CCM
2

Imax[n]
Vsel LUT
Peak Current (A)

1.5

Fig. 9. Frequency mode switching block.

1

A dead-zone in inductor current near the zero crossings of

fs = 125kHz
the line voltage leads to higher THD, as summarized in Table 0.5
fs = 250kHz
II. The THD caused by a dead-zone in current is significant fs = 500kHz
fs = 1MHz
but tolerable and the gain in efficiency from not switching in 0
0 50 100 150 200 250 300 350 400
this region outweighs the THD increase. Input Voltage (V)
A LUT determines the peak current thresholds for transi- (b)
tioning between frequencies after constant peak current mode
Fig. 10. Peak current thresholds for frequency mode-switching for Vout of
has been exited, due to reaching a sufficiently high input volt- (a) 250 V, and (b) 450 V.
age. The peak current thresholds that separate the frequency
modes are bound by the following three conditions: The first condition is based on the maximum expected Ipeak
1) The maximum peak current command of the DAC for for the designed system. Allowing a higher Ipeak than required
the implemented current sensing corresponds to a 3 A decreases the current sensor gain and increases the bandwidth
limit. requirement. There is a trade-off in adjusting the peak cur-

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Transactions on Power Electronics

rent limits of the second condition, for example lower peak iL iL

iP3
current limits produce lower efficiency and lower THD. The
third condition being met corresponds to switching controls iP2
schemes from DCM to CCM, where the source of the set
signal in the RS latch changes due to the fmode signal. In
DCM, the set signal is connected to a clock source while in
CCM it is generated by an off-time generator as shown in iP1
Fig. 5. The peak current threshold of BCM, which determines
t
the boundary of DCM and CCM is defined as
1 2 3 4 3 2 1
(Vout (Vout − Vin )((Vin Ts ) − (Ipeak LB ))2 )
Ipeak,BCM = 3T L ) . Fig. 11. MCM operation. The conditions 1-4 represent constant peak mode,
(Vin s B
125 kHz, 250 kHz, and 1 MHz CCM, respectively. The corresponding peak
(3) current thresholds (purple) are represented by iP1 , iP2 , and iP3 . The inductor
As can be deduced from (3), the BCM peak current thresh- current (blue) and average current (orange) are shown.
old is dependent on fs , Vout and Vin . As shown in Fig. 10, two
LUTs are used to account for the dual output modes (250/450 iL iL iL iL iL iL
V) of the converter, with entries for 125 kHz, 250 kHz, 500
kHz, and 1 MHz pre-calculated in MATLAB. Isense
iL ipeak_delayed
The frequency and mode transition process of the FSM is
summarized for a given line cycle: Vx
ipeak_desired
1) As Vin (t) starts from 0 V the converter enters constant R
S Q
SET

Ipeak t t t t
peak current mode.
2) When Vin (t) reaches 20/40 V for output voltages of (a) set S
R Q
(b) CLR
Rs
250/450 V, respectively, iL the converter enters 125
iL kHz iL
DCM. iL iL iL iL
3) Vin (t) increases and the calculated peak current exceeds iP3iP3 t
td,comp td,logic td,driver td,MOS
the threshold limit, the converter switches to 250 kHz iP2iP2
DCM.
4) This process continues to 500 kHz and to 1 MHz, and
in the reverse direction as the line voltage drops. t iP1iP1 t t
This process can be seen in Fig. 11 in detail for a given (c) t t
output power, and in Fig. 12 over multiple output powers. Fig. 12. Inductor current (blue) and average current (orange) for (a) low
1 1 power, 2 2 (b) clk
3 medium
3 4 4 3 3 2 2 1 1
If the condition in Fig. 3 is exceeded by the converter for power, and (c) high power.
iL i iL iL
any frequency, increasing
iP3 the frequency by transitioning to the Ipeak_calculate L
Controller Signals

next mode positions iP2 the converter deeper into CCM, and the Ipeak_result
converter transitions immediately through all the states up to requiring adaptive slope compensation for different load condi-
fs = 1 MHz CCM. A doubling of frequency occurs from 500 Itions. freq_calculate
More importantly, slope compensation distorts the actual
kHz DCM to 1 MHz iP1 CCM, which reduces the ripple current
peak current
IDAC_sample and increases the non-linearity in the average
current, which reduces the Isense
Iaccuracy
sense of a modulation algorithm.
in half. Once a transition occurs there is an inherent hysteresis
iL iL ipeak_delayed
ipeak_delayed t The I DAC_clk
result is that a universal ramp leads t
to higher THD [35],
preventing oscillation between modes, as the peak current will VxVx
ipeak_desired
ipeak_desired V
but allowing for a variable ramp is difficult to implement
generally increase 1along2 the line 3 cycle. 4 3 2 1 ADC_sample
R S
S RQ Q
SET SET

without I aI large
VADC_clkpeakpeak L i LUT or intensive computation and calibration
t iL
C. DCM Operation to minimize the setsetTHD S R
R S impact
Q Q [34].
CLR
Rs Rs
CLR

In DCM the set signal in the SR-latch is determined by The goal of this work is to 1) avoid the instability of PCMC,
the system clock. A simple clock divider from the 50 MHz and 2)t minimize t any deviation from the calculated peak current
t td,comp td,logic
t td,driver
td,driver td,MOS
td,MOS
system clock accurately creates the DCM frequencies of 125 to obtain a d,comp sinusoidald,logicaverage current and low THD. Slope
kHz (divide by 400), 250 kHz (divide by 200),Isense and 500 kHz compensation cannot meet goal 2), as it actively modifies
iL iby
(divide 100). The signal Ndiv [n] from the LUT, multiplexes the peak current command every cycle with a compensating
peak_delayed
t
these clocks to create the setDCM [n] signal. Vx ramp, resulting in poor control of the average current. As such
ipeak_desired
SET

clkclk an analog Off-Time Generator (OTG) is adopted to prevent

SR Q
D. CCM Operation Ipeak
set IR sIpeak_calculate
instability, as shown in Fig.13. However, the traditional OTG
RS Q peak_calculate
The need for slope-compensation to prevent oscillations at has frequency variations when losses are considered, which
Controller Signals
Controller Signals

CLR

Ipeak_result
Ipeak_result
duty cycles greater than 50% is a major limitation of CCM results in an inaccuracy of the generated peak current, failing
t I freqI_ _calculate
calculate
freq
PCMC. As demonstrated in [33] and [34], tslope-compensation
td,comp d,logic td,driver td,MOS goal 2). The operation of the analog OTG for PFC applica-
IDAC_sample
IDAC_sample
can be used in PFC, however the implementation is complex, tions in this work follows from [26], with the addition of
I I DAC_clk
DAC_clk

VADC_sample
VADC_sample
VADC_clk
VADC_clk t t
clk
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Ipeak_calculate
nals

I
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Transactions on Power Electronics ipeak[n]
ipeak[n] d[n] d[n+1]
t
t

iL iL iL
iL
a current-mode DAC instead of a fixed current source, to
ipeak[n+1] ipeak[n+2] ipeak[n+1]
actively
ipeak[n+1] compensate for frequency variations. By doing so, iL ipeak[n] ipeak[n+1]
ipeak[n] m1 m2 ipeak[n]
the calculated peak current command produces an accurate
sinusoidal average current and both goals are met. iavg[n] iavg[n+2]
iavg[n+1]

Off-Time Generator ipeak[n] t

ipeak[n] d[n] d[n+1] d[n+2]
Ifreq,nom
Digital Frequency Locked loop t t
Vsel t
fccm (a)
iL
iL iL iL
Counter Integrator Ifreq,adj Ifreq
ipeak[n+1]
clock
D
SET
Q + + iiDAC
ipeak[n+1]
peak[n+2]
ipeak[n+1]
iL ipeak[n] ipeak[n+1]
setccm ma
CLR Q ipeak[n] m1 m2 ipeak[n] ipeak[n]
Voff
m1 m2
iavg[n] iavg[n+1] Cotg
iavg[n+2]

ipeak[n] t
d[n] d[n+1] d[n+2]
fmode[n]
kVin(t)
c[n]

t t t

(b)
Fig. 13. iL generator.
Off-time iL
ipeak[n+1] ipeak[n+1] ipeak[n+1]
ma
ipeak[n] Ifm1 themoff-time
2
is made proportionalipeakto
[n] the input voltage by ipeak[n]
m1 m2
a scaling factor K1 , the off-time is defined as m1 m2

Toff
Tof f = K1 Vin , (4)
then the switching frequency
t is constant and K1 is chosen t t
to ensure 1 MHz operation as given by, (c)
Fig. 14. Inductor current during a transient for peak current mode control
1 (a) with a conventional implementation (b) with slope compensation and
Tsw,CCM = K1 Vout ⇒ fsw,CCM = . (5) (c) with an OTG.
K1 Vout
In the case of the designed off-time generator, a 7-bit cur-
rent DAC produces a current, If req , that is integrated over both load and line dependent and vary along the line cycle
a capacitor, Cotg during the off-time. This process produces itself.
a voltage, Vof f , that is controlled by driving a switch with Unlike [36], which uses the average current as feedback to
c[n]. By comparing Vof f with Vin , the set signal for an off- correct for losses, or [37] that uses an analog PLL, a digital
time that varies along the line cycle is created. By modifying Frequency Locked Loop (FLL) is designed in this work to
(5) to account for the analog implementation of this off-time correct for frequency variations based on a Delay Locked Loop
generator, the switching frequency can be defined as (DLL). The advantage over [36], which ignores some non
resistive losses (diode voltage drops), is that the frequency
If req regulation is more tightly controlled. Compared to [37], the
fsw,CCM = . (6) advantage is that the correction term can be digitally stored
Cotg Vout
and reapplied at the transition from DCM to CCM and CCM
Without slope compensation, a step in Ipeak [n], results in to DCM, to allow for faster locking during mode transitions.
oscillations for D>50%, as shown in Fig. 14(a). Introducing a This scheme adjusts If req into a nominal part, If req,nom
compensating slope of ma can be used to stabilize the inductor created by the feed-forward conventional OTG and a feedback
current, as shown in Fig. 14(b). Alternatively, the use of an term, If req,adj created by the FLL. The FLL measures the
OTG stabilizes the inductor current in one cycle, as shown in switching period through a counter and compares that to a
Fig. 14(c). A fixed off-time prevents oscillations, however any reference delay of 1 us. Any error is corrected for using an
variation in the calculated off-time results in an error in fs . integrator, to adjust If req,adj . If req,adj is allowed to deviate
Accurate frequency regulation is important to achieve low from If req,nom by up to 50%. This allows for fast and accu-
THD, as any variations to fs impacts the accuracy of the peak rate locking of the frequency and prevents stability issues by
current modulation algorithm in CCM. The conventional off- limiting the maximum swing of the FLL. The bandwidth of
time generator [26, 36] has been improved in this work to the FLL is chosen such that it is at least an order of magnitude
suppress frequency variations, which occurs because losses lower than the switching frequency (1 MHz), to avoid coupling
are neglected in (6). For the boost PFC rectifier, the losses are with the converter dynamics. To avoid coupling and to allow

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for fast correction, the sampling frequency of the integrator responds to a higher input current. The worst-case frequency
is chosen to be 20 kHz with a gain of 1. This allows the variation is about +50 % at 150 W for 85 Vrms , if the varia-
frequency to change by 2% every 50 µs, which is fast enough tions are normalized. With the proposed FLL, the frequency
to correct for the frequency variation due to losses. variation is limited to ±2% using the system 50 MHz clock as
To quantify the benefits of the feedback path, the OTG reference, which is a significant improvement. While the AC
imposed switching frequency is modified to include the MOS- losses increase at higher frequencies, the on times significantly
FET conduction loss, Ron , inductor DC loss, RL , boost diode decrease. The current sensor has a limited bandwidth and there
voltage drop, VD , and bridge diode voltage drop, Vbridge as is a minimum on-time of 200 ns. As such, the frequency
follows: locking of the OTG avoids run off in the current that would
occur if a smaller on-time is required than the blanking time
(Vout + VD )(|Vline | − VBridge ) allows.
Tsw,CCM = K1 .
(|Vline | − VBridge ) − Iin,avg (Ron + RL ) III. D IGITAL P EAK C URRENT M ODULATION
(7)
Due to inherent non-linearity, a sinusoidal Ipeak [n] does not
lead to a sinusoidal average current in either DCM or CCM,
1.9
OTG Frequency, Vrms=85V thus Ipeak [n] must be modulated on a cycle-by-cycle basis.
50W Analog modulation schemes have been demonstrated [3,38,
1.8 100W
150W
39], but make simplifying approximations when non-trivial
1.7 operations such as a square root are required, which increases
THD. In addition, these analog signal processing circuits are
Nominalized Frequency

1.6
complicated and inaccurate to implement on-chip in mod-
1.5
ern BCD technologies such as [20]. This motivates the use
1.4 of an accurate all-digital modulation scheme that does not
1.3
significantly distort Ipeak [n] through approximations, and is
accurate to the quantization limit of the DAC, which is 12-bit
1.2
in this design. Digital strategies have been used such as in [40],
1.1 where on-time control for DCM and BCM operation is used.
1 Unlike [40], a FPGA is used for modulation. Unlike [41], this
30 40 50 60 70 80 90
Angle (degrees) work provides cycle-by-cycle control of Ipeak , which results
in improved THD performance.
(a)
OTG Frequency, Vrms=265V The calculation of Ipeak [n] is multiplexed into two parts, a
1.02
50W
CCM calculation and a DCM calculation as shown in Fig. 16.
1.018 100W The inputs into each modulation algorithm are Vsin [n], Vout [n],
150W
1.016
and Pcmd [n]. The signal fmode [n], selects between the CCM
modulation and the DCM modulation algorithms. A peak cur-
Nominalized Frequency

1.014
rent clamp of 3 A prevents overflow of Ipeak [n] when it is
1.012 sent to the DAC.
1.01
PFC Modulation
1.008
DCM
Modulation Ipeak[n]
1.006
Peak Current
Clamp +
1.004 Vin,HR[n] Ipeak_d[n]
CCM
Vout[n]
Pcmd[n] Modulation td/L
1.002
30 40 50 60 70 80 90
Angle (degrees)

(b) fmode[n]

Fig. 15. Resulting fs variation normalized to 1 MHz using an OTG for

CCM if losses are neglected at a Vline of (a) 85 Vrms and (b) 265 Vrms . Fig. 16. PFC Modulation.

As shown in Fig. 15, the frequency variation across line A correction scheme is used to compensate the delay time
voltage (85-265 Vrms ) and load power (50-150 W) is sig- between a reset detection in the current comparator to the
nificant. The frequency variation is heavily tied to the input actual transition edge on the MOSFET. This delay introduces
current, as the worst variation is observed for low line voltages non-linear distortion in the peak current. As shown in Fig. 17,
at 150 W. These plots were created with the assumption that the reset delay is composed of a comparator delay, td,comp ,
during the line cycle the efficiency varies linearly from 70% logic delay, td,logic , driver delay, td,driver , and MOSFET switch-
to 95%. This assumption was made to accurately represent ing delay, td,M OS . The sum of these delays is denoted, td,reset .
switching and core loss that is neglected in (5), which cor-

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iP1
t t
The error in the peak current error resulting from reset delays 2.5
DCM Peak Current
1 2 3 4 3 2 1
is given by iL
50W / 90V
iL
50W / 180V
50W / 270V
2 100W / 90V
Vin 100W / 180V
Ipeak,error = td,reset . (8)
LB 100W / 270V

Peak Current (A)

1.5

Isense
iL ipeak_delayed
1 t
Vx
ipeak_desired
SET
R
S Q
Ipeak 0.5
set S
R CLR Q
Rs

0
t 0 20 40 60 80 100 120 140 160 180
td,comp td,logic td,driver td,MOS Angle (degrees)

(a)
Fig. 17. Peak current reset delays. CCM Peak Current
2.5
50W / 90V
At the maximum input voltage of 375 V for a line voltage 50W / 180V
of 265 Vrms , Iclk peak,error is 0.28 A for td,reset = 75 ns in this 50W / 270V
2 100W / 90V
design, which is 10% of the maximum peak current command.
Ipeak_calculate 100W / 180V
Controller Signals

This highlights the importance of adjusting the peak current to

Ipeak_result 100W / 270V

Peak Current (A)

account for
Ifreq_this
calculatedelay. More accurate peak current correction
1.5

can be done using a temperature sensor or an analog block

IDAC_sample
with an inverseIDAC_clktemperature relationship to provide tempera- 1
ture compensated
VADC_sample delays as in [42, 43], but that is left for a
future moreVADC_clk
integrated solution. t
0.5
A. DCM Modulation
The following modulation equation uses the same method- 0
0 20 40 60 80 100 120 140 160 180
ology as in [3], but is modified to determine the cycle-by-cycle Angle (degrees)
peak current command in DCM as opposed to a duty cycle:
(b)
r √ Fig. 18. Modulation waveforms for a range of output powers and line voltages
Vin Ts Vin 2LB fs Po in (a) DCM at 500 kHz, and (b) CCM at 1 MHz.
IpeakDCM = 1− . (9)
LB Vout Vm
An example of peak currents over a range of load power and
operation is when ∆I → Iavg , which approaches the DCM
input voltages is shown in Fig. 18(a). Note that at high input
case. Additionally, due to the use of the ideal off-time equa-
voltages there is significant bending in Ipeak which can be
tion, the CCM modulation of (10) is not perfect. It is possible
inferred from (9). A more practical reasoning for this effect
in the future to implement the feedback term of the OTG
is understood by examining the inductor current. The rising
into the CCM algorithm for increased accuracy of the Tof f
inductor slope becomes very steep, but the falling inductor
calculation for improved THD performance. However, based
slope becomes very gradual. Therefore there is a large average
on experimental results this effect is small and, as seen in
current at the output for a small peak current. This leads to a
Fig. 15, it is most pronounced at low line voltages.
non-monotonic behavior in Ipeak [n] across the line cycle.
IV. H ARDWARE D ESIGN
B. CCM Modulation
The following derivation follows from the same methodol- The boost PFC rectifier is split into three functional hard-
ogy of [26], to produce an equation that determines the cycle- ware blocks, a FPGA board for digital control, an interface
by-cycle peak current command in CCM: board, and a power-stage board. The FPGA used is a Spartan
3e Starter Board. Using the built-in power analyzer tool by
√ Vin
Xilinx predicts a peak power draw of 0.18 W for the FPGA.
2Po |sin(wt)| 1 Vin (1 − Vout )) A FPGA was used over a micro-controller, as it can process
IpeakCCM = + . (10)
Vm 2 LB fsw many multiplications and divisions in parallel and over a few
An example of peak currents over a range of power and cycles. Furthermore, a FPGA facilitates a simple ASIC im-
input voltages is shown in Fig. 18(b). Note that at high input plementation with HDL reuse. In a micro-controller, integer
voltages there is noticeable bending in Ipeak for the same multiplication is generally done using a general purpose 32-
reasons as in DCM. Consider that the biggest impact for CCM bit multiplier, with two variable numbers this can take up to

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100 cycles, and a division up to 200 cycles for example on the for Vline of 85 Vrms , 120 Vrms , 230 Vrms , and 265 Vrms . A
TI MSP430 [44]. A closeup up of the interface PCB is shown number of PFC reference boards are used for comparison,
in Fig. 19(b). The mixed-signal control circuitry, consumes including 1) a 160 W BCM reference board [45] 2) a 150
approximately 0.8 W, and can be greatly reduced with a future W BCM reference board [46] and 3) a 300 W CCM reference
on-chip implementation. The power-stage PCB, is shown in board [47]. PFC converters operating in CCM in the market
Fig. 19(a). are usually designed for power levels above 150 W, thus a
completely fair comparison is challenging. Recently published
high-frequency PFC demonstrations [24,25,48] do not include
a full characterization of THD and efficiency and thus cannot
be objectively compared.
A. Switching Waveforms
Switching waveforms for the transition between frequency
modes are presented in Fig. 20. The transition between modes
(a) (b)
is fast and smooth and occurs within approximately 3 cycles.
Fig. 19. (a) The power-stage PCB, which measures 5 cm x 4.2 cm, and
It can be inferred from these figures that the DCM ringing
(b) The interface PCB, which measures 15.5 cm x 6.7 cm. frequency is approximately 1.8 MHz. The parasitic inductor
current ringing can be comparable in magnitude to the peak
currents at low power levels, which lowers efficiency and in-
A. Component Selection
creases THD.
The power-stage components were optimized for low loss
at high frequency operation and high output voltages. The B. Current Waveforms
selected parts are shown in Table III, with the relevant loss The inductor current and line current for Vline = 120 Vrms
parameters given. The emphasis for high frequency and high and Vline = 230 Vrms operation are shown in Fig. 21 and
voltage design is in reducing AC loss, as the DC loss at the Fig. 22 respectively. These waveforms are used to qualitatively
specified current range and output power is not high (1.76 demonstrate the effectiveness of the active PFC line shap-
Arms maximum). As such the MOSFET was chosen to have a ing algorithm and frequency mode switching that produces
high Ron , but low output capacitance, COSS , gate-to-source a low THD, sinusoidal input current. At Vline = 120 Vrms
charge, Qgs , and gate to drain charge, Qgd which results in the converter operates mostly in CCM, whereas at Vline =
minimized capacitive switching loss, turn on loss, and turn 230 Vrms the converter operates mostly in DCM until higher
off loss. A Silicon MOSFET was used as an optimized GaN power. There is a noticeable distortion in the line current near
HEMT is not yet available for this low-power specification. A the zero crossings where the converter enters constant peak
SiC diode was chosen for the boost diode because of the zero current mode and stops line shaping. Furthermore, at Vline
reverse recovery time, trr , which improves CCM efficiency. A = 120 Vrms there is an element of distortion caused by the
custom boost inductor was designed using a high grade ferrite decreased accuracy of the CCM modulation algorithm from
core material Ferroxcube 3F4 for reduced high frequency loss. the off-time assumption in (10) as the inductor approaches
TABLE III
saturation.
P OWER S TAGE C OMPONENT S ELECTION
C. Total Harmonic Distortion
Component Part Number Parameters The measured THD for all load and line conditions is pre-
sented in Fig. 24. Assuming that each harmonic is at its limit
Ron = 900 mΩ, COSS based on the IEC 61000-3-2 specification and unity displace-
= 21 pF, Qgs = 1.6 nC, ment PF, a maximum THD of 33% is allowed, which cor-
MOSFET AOD4260
Qgd = 1.8 nC, Qg = 6 responds to Class C requirements. The THD at Vline = 85
nC, Rg = 18 Ω Vrms is higher than at other line voltages. This is partly due
L = 100 µH, RL = 200 to constant peak current mode which occurs near the zero
Inductor Custom mΩ, Ferroxcube 3F4, crossings and is most notable at Vline = 85 Vrms , summarized
EFD 15 in Table II. Another source of distortion is the use of the ideal
VD = 2.3 V, trr = 0 ns, off-time without considering losses from (10). The inductor
Boost Diode IDD03SG60C approaches saturation near the rated power at Vline = 85 Vrms ,
CR = 60 pF
which results in moderately higher THD. In addition, there is
Bridge Diode GBU8J VD = 1 V noticeable distortion at high line voltages for low power levels.
This effect can be caused by the parasitic ringing magnitude
V. E XPERIMENTAL R ESULTS of IL becoming comparable to Ipeak [n] along the line cycle
at low currents, which can be alleviated by valley switching.
The PCB setup of Fig. 19 was experimentally tested for
loads ranging from 20 W to 150 W at fline = 60 Hz and

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(a) (a)

(b) (b)

(c) (c)

(d) (d)
Fig. 20. Switching waveforms for (a) 125 kHz to 250 kHz transition, (b) 250 Fig. 21. Inductor current and line current waveforms at Vline = 120 Vrms
kHz to 500 kHz transition, (c) 500 kHz to 1 MHz transition, and (d) 1 MHz for Po of (a) 20 W, (b) 50 W, (c) 100 W, and (d) 150 W.
operation.

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(a) (a)

(b) (b)
Fig. 23. Rectified line voltage and line current at Po = 100 W for Vline of
(a) 120 Vrms , and (b) 230 Vrms .

35
85 Vrms
30
120 Vrms
25 230 Vrms
265 Vrms
THD (%)

20
IEC Limits
15

10

0
20 40 60 80 100 120 140 160
(c)
Output Power (W)

Fig. 24. Measured THD.

D. Power Factor
The power factor for all load and line conditions is presented
in Fig. 25. The biggest impact for P Fdp is the capacitor CDM
in the EMI filter. To demonstrate how P Fdp is affected, in
Fig. 23 the line current, Iline is compared against Vin for 120
Vrms and 230 Vrms . Near the zero crossings of the line voltage,
there is capacitive filtering. This causes minor errors in the line
(d) synchronization algorithm because the minimum voltage is not
Fig. 22. Inductor current and line current waveforms at Vline = 230 Vrms necessarily the true zero crossing location of the rectified line
for Po of (a) 20 W, (b) 100 W, (c) 100 W, and (d) 150 W. voltage. In comparison to the reference papers and boards, the
PF results are fairly consistent since a similar CDM is used.
At high line voltages the power factor drops significantly at

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low power levels, due to CDM , this effect is less pronounced boards, using the digital optimization and control techniques
at low line voltages for the posted power levels. discussed in this journal. The sizes of the common mode
chokes and differential inductors are also provided as a ref-
1.05 erence. The differential filter inductance is produced by the
leakage inductance of LCM for [47] and as such does not
1 consume any space, but is also not specified in the data-sheet.
This design produces lower THD levels with a choke that is
Power Factor

0.95
2× smaller and a differential inductance that is 7× smaller
compared to the 160 W reference [45]. This design produces
0.9
85 Vrms comparable THD levels with a choke that is 4.5× smaller and
120 Vrms a differential inductance that is 7× smaller compared to the
0.85
230 Vrms
150 W reference [46].
265 Vrms
0.8
20 40 60 80 100 120 140 160 VI. C ONCLUSION
Output Power (W)
The objective of this work is to implement a high-frequency,
small form-factor, boost PFC rectifier suitable for future on-
Fig. 25. Measured Power Factor. chip implementation. In Sections II and III, a digitally-controlled
boost PFC rectifier, MCM controller is designed specifically
to operate at 1 MHz, without the need for average current
E. Efficiency sensing. The novel contributions include:
In Fig. 26, the efficiency is measured considering PPout in
, to 1) Implementing DCM and CCM modulation algorithms
extract only the real power transfer. Conduction losses become on a FPGA for PCMC, by extending the work from [3,
significant for the Vline = 85 Vrms case, as can be seen by the 26], with cycle-by-cycle calculations for switching fre-
rolling off of efficiency at high power levels. Variations in quencies up to 1 MHz.
the efficiency graphs are due to frequency mode switching. 2) Allowing for a LUT based frequency mode switching
Changes from DCM to CCM have a large impact on losses. scheme to optimize efficiency and EMI performance over
a broad range of line and load conditions.
3) An off-time generator that enables 1 MHz CCM op-
96
eration in a PCMC boost PFC rectifier without slope
94 compensation based on [26].
Efficiency (%)

4) A frequency locked loop that significantly reduces fre-

92
quency variation of the feed-forward off-time genera-
90 85 Vrms
tor. The combination of the feed-forward and feedback
120 Vrms paths allows for fast and accurate frequency regulation
88 230 Vrms to improve THD performance and accuracy of the CCM
86
265 Vrms modulation in [26].
20 40 60 80 100 120 140 160
The prototype achieves a peak efficiency of 95% and oper-
Output Power (W)
ates over a universal mains input of 85-265 Vrms for a rated
power of 150 W. By implementing PCMC with DCM and
Fig. 26. Measured efficiency using real input power, ηP = PPout . CCM modulation algorithms calculated on an FPGA, a low
in
THD and high PF is achieved on a converter that operates
at up to to 1 MHz without any average current sensing. As
F. Result Comparison
a result of the high frequency operation, the boost inductor
A detailed performance comparison is provided in Table IV. size is significantly reduced to 15×15 mm, which improves
The designed boost inductor used in this work is 4-7.6× smaller, the form factor. The proposed mixed-signal control scheme
mainly due to lower inductance and smaller required peak is suitable for on-chip implementation in an advanced BCD
current. As mentioned before, [47] was designed for 300 W, technology similar to [20] for GaN cascode applications.
which explains why the inductor is 7.6× larger than the de-
signed inductor and approximately 2× larger than [45, 46]. VII. ACKNOWLEDGEMENT
Additionally, this design uses a SiC diode, therefore the ef- This work was supported by NXP Semiconductors, the Cana-
ficiency and size are inherently better than [47], due to zero dian Foundation for Innovation and NSERC. The authours
reverse recovery loss. The significance of the 1 MHz opera- thank Yue Wen, HenkJan Bergveld and Matthias Rose for their
tion from this work is that a smaller size is achieved while contributions.
maintaining efficiency within 2-3% with a silicon transistor
and SiC diode. Future GaN devices can provide the same size
reduction, with comparable efficiency to the supplied reference

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TABLE IV
C OMPARISON OF PFC F RONT-E ND C ONVERTERS

Quantity This work [45] [46] [47]

Conduction Mode MCM BCM BCM CCM
Controller Digital Analog Analog Analog
Control Method Peak current Duty cycle Peak current Avg current
Rated Pout 150 W 160 W 150 W 300 W
Vout 250/450 V 390 V 400 V 390 V
Ipeak Requirement at 150 W 2.9 A 5A 5A 3A
Maximum fs 1 MHz 500 kHz 400 kHz 65 kHz
Minimum fs 125 kHz 20 kHz 10 kHz 65 kHz
Efficiency at 150 W for 120 Vrms 94.8% 96.2% 96% 94%
Efficiency at 150 W for 230 Vrms 94.8% 97.8% 97.5% 97%
THD at 150 W for 120 Vrms 4% 10% 6% Not specified
THD at 150 W for 230 Vrms 3.5% 15% 3% Not specified
LB 100 µH 200 µH 450 µH 1.24 mH
LB core size 15×15 mm 30×30 mm 41×40 mm d=46.7 mm
LDM 10 µH 117 µH 300 µH Unknown
LDM core size 7×7 mm d=19 mm d=21 mm Part of LCM
LCM 2 mH 8.5 mH 15 mH 3.9 mH
LCM core size d=14 mm d=20 mm 32×21.5 mm 40×21.5 mm

R EFERENCES verters operating in both continuous and discontinuous conduction

mode,” Industrial Electronics, IEEE Transactions on, vol. 52, no. 1,
[1] S. Sahoo and H. Jariwala, “A new power factor correction technique pp. 88–97, Feb 2005.
using PFC boost converter,” in Environment and Electrical Engineering [10] W.-S. Wang and Y.-Y. Tzou, “Light load efficiency improvement for
(EEEIC), 2012 11th International Conference on, May 2012, pp. 819– AC/DC boost PFC converters by digital multi-mode control method,”
823. in Power Electronics and Drive Systems (PEDS), 2011 IEEE Ninth
[2] B. Gandhi and M. Ezhilmaran, “Achieving high input power factor International Conference on, Dec 2011, pp. 1025–1030.
for DCM boost PFC converters by controlling variable duty cycle,” [11] M. Ivankovic, “CrCM PFC Boost Converter Design,” Infineon, U.S.A.,
in Computation of Power, Energy, Information and Communication 2013, available at http://www.infineon.com.
(ICCPEIC), 2013 International Conference on, April 2013, pp. 18–20. [12] Q. Li, F. Lee, M. Xu, and C. Wang, “Light load efficiency improvement
[3] K. Yao, X. Ruan, X. Mao, and Z. Ye, “DCM boost PFC converter with for PFC,” in Energy Conversion Congress and Exposition, 2009. ECCE
high input PF,” in Applied Power Electronics Conference and Exposition 2009. IEEE, Sept 2009, pp. 3755–3760.
(APEC), 2010 Twenty-Fifth Annual IEEE, Feb 2010, pp. 1405–1412. [13] Y. Jang and M. Jovanovic, “Light-Load Efficiency Optimization
[4] H. Kim, B.-H. Cho, and H. Choi, “An improved modulated carrier Method,” Power Electronics, IEEE Transactions on, vol. 25, no. 1, pp.
control of single-phase CCM boost PFC converter,” in Power Electronics 67–74, Jan 2010.
Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 2014 International, [14] J. Moldaschl, J. Broulim, and L. Palocko, “Boost power factor correction
May 2014, pp. 2575–2579. topology with average current control,” in Applied Electronics (AE),
[5] R. Gupta, H. Krishnaswami, and N. Mohan, “A Unified Analysis of 2014 International Conference on, Sept 2014, pp. 213–216.
CCM Boost PFC for Various Current Control Strategies,” in Power [15] W. Cheng, J. Song, H. Li, and Y. Guo, “Time-Varying Compensation
Electronics, Drives and Energy Systems, 2006. PEDES ’06. International for Peak Current-Controlled PFC Boost Converter,” Power Electronics,
Conference on, Dec 2006, pp. 1–5. IEEE Transactions on, vol. 30, no. 6, pp. 3431–3437, June 2015.
[6] S.-P. Yang, S.-J. Chen, and C.-M. Huang, “Small-signal modeling [16] Y.-J. Ke, Y. fei Zhou, and J. ning Chen, “Control Bifurcation in PFC
and controller design of BCM boost PFC converters,” in Industrial Boost Converter under Peak Current-Mode Control,” in Power Electron-
Electronics and Applications (ICIEA), 2012 7th IEEE Conference on, ics and Motion Control Conference, 2006. IPEMC 2006. CES/IEEE 5th
July 2012, pp. 1096–1101. International, vol. 2, Aug 2006, pp. 1–5.
[7] K.-H. Chou, T.-J. Liang, K.-H. Chen, and J.-S. Lee, “Design and [17] S.-P. Yang, S.-J. Chen, and C.-M. Huang, “Analysis, modeling and
implementation of an interleaved BCM boost PFC control IC,” in Power controller design of CRM PFC boost ac/dc converter with constant on-
Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 2014 time control IC FAN7530,” in Industrial Electronics and Applications
International, May 2014, pp. 3346–3351. (ICIEA), 2014 IEEE 9th Conference on, June 2014, pp. 354–359.
[8] R. Tripathi, S. Das, and G. Dubey, “Mixed-mode operation of boost [18] L. Roggia, F. Beltrame, J. Baggio, H. Hey, and J. Pinheiro, “Implementa-
switch-mode rectifier for wide range of load variations,” Power Elec- tion issues of a digital control system applied to a PFC boost converter,”
tronics, IEEE Transactions on, vol. 17, no. 6, pp. 999–1009, Nov 2002. in Industrial Electronics, 2009. IECON ’09. 35th Annual Conference of
[9] K. De Gusseme, D. M. Van de Sype, A. Van den Bossche, and IEEE, Nov 2009, pp. 1519–1524.
J. Melkebeek, “Digitally controlled boost power-factor-correction con-

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Transactions on Power Electronics

[19] H. Forghani-zadeh and G. Rincon-Mora, “Current-sensing techniques for and Systems (ISCAS), 2011 IEEE International Symposium on, May
DC-DC converters,” in Circuits and Systems, 2002. MWSCAS-2002. The 2011, pp. 233–236.
2002 45th Midwest Symposium on, vol. 2, Aug 2002, pp. II–577–II–580 [37] L. Cheng, J. Ni, Z. Hong, and B. Liu, “A constant off-time controlled
vol.2. boost converter with adaptive current sensing technique,” in ESSCIRC
[20] M. Rose, Y. Wen, R. Fernandes, R. Van Otten, H. J. Bergveld, and (ESSCIRC), 2011 Proceedings of the, Sept 2011, pp. 443–446.
O. Trescases, “A GaN HEMT Driver IC with Programmable Slew Rate [38] M. Chow, K. Siu, C. Tse, and Y.-S. Lee, “A novel method for elimination
and Monolithic Negative Gate-Drive Supply and Digital Current-Mode of line-current harmonics in single-stage PFC switching regulators,”
Control,” IEEE 27th International Symposium on Power Semiconductor Power Electronics, IEEE Transactions on, vol. 13, no. 1, pp. 75–83,
Devices and ICs (ISPSD), 2015. Jan 1998.
[21] Y. Yan, F. Lee, and P. Mattavelli, “Analysis and design of average cur- [39] H. Kim, B.-H. Cho, and H. Choi, “An improved modulated carrier
rent mode control using a describing-function-based equivalent circuit control of single-phase CCM boost PFC converter,” in Power Electronics
model,” Power Electronics, IEEE Transactions on, vol. 28, no. 10, pp. Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 2014 International,
4732–4741, Oct 2013. May 2014, pp. 2575–2579.
[22] Y. Yan, F. Lee, P. Mattavelli, and S. Tian, “Small-signal Laplace- [40] T. Grote, H. Figge, N. Frohleke, J. Bocker, and F. Schafmeister, “Digital
domain model for digital predictive current mode controls,” in Energy control strategy for multi-phase interleaved boundary mode and DCM
Conversion Congress and Exposition (ECCE), 2012 IEEE, Sept 2012, boost PFC converters,” in Energy Conversion Congress and Exposition
pp. 1386–1393. (ECCE), 2011 IEEE, Sept 2011, pp. 3186–3192.
[23] S. He, R. Nelms, and J. Hung, “Small-signal modeling for digital [41] S. F. Lim and A. Khambadkone, “A simple digital DCM control scheme
predictive current mode control in CCM,” in Applied Power Electronics for boost PFC operating in both CCM and DCM,” in Energy Conversion
Conference and Exposition (APEC), 2015 IEEE, March 2015, pp. 2816– Congress and Exposition (ECCE), 2010 IEEE, Sept 2010, pp. 1218–
2820. 1225.
[24] F.-Z. Chen and D. Maksimovic, “Digital Control for Improved Efficiency [42] M. Grigorie, C. de Raad, F. Krummenacher, and C. Enz, “Analog
and Reduced Harmonic Distortion over Wide Load Range in Boost PFC Temperature Compensation for Capacitive Sensor Interfaces,” in Solid-
Rectifiers,” in Applied Power Electronics Conference and Exposition, State Circuits Conference, 1996. ESSCIRC ’96. Proceedings of the 22nd
2009. APEC 2009. Twenty-Fourth Annual IEEE, Feb 2009, pp. 760– European, Sept 1996, pp. 388–391.
766. [43] A. Mukherjee, D. Sarkar, A. Sen, D. Dey, and S. Munshi, “An analog
[25] Z. Lu, M. Wang, and L. Zheng, “A predictive averaged current mode signal conditioning circuit for thermocouple temperature sensor employ-
control for high power factor boost rectifier,” in Electrical Machines and ing thermistor for cold junction compensation,” in Control, Automation,
Systems, 2005. ICEMS 2005. Proceedings of the Eighth International Robotics and Embedded Systems (CARE), 2013 International Confer-
Conference on, vol. 2, Sept 2005, pp. 1228–1231 Vol. 2. ence on, Dec 2013, pp. 1–5.
[26] C. Adragna, S. De Simone, and G. Gattavari, “New Fixed-Off-Time [44] “Efficient Multiplication and Division Using MSP430,”
PWM modulator provides constant frequency operation in boost PFC TI, U.S.A., accessed in July 2015, available at
pre-regulators,” in Power Electronics, Electrical Drives, Automation and http://www.ti.com.cn/cn/lit/an/slaa329/slaa329.pdf.
Motion, 2008. SPEEDAM 2008. International Symposium on, June 2008, [45] “160-W, Wide Mains, PFC Stage Driven by the NCP1611 Evalua-
pp. 656–661. tion Board User’s Manual,” ON Semiconductor, U.S.A., available at
[27] Y. Ko, K. Park, K.-B. Lee, and F. Blaabjerg, “A new PLL system using http://www.onsemi.com/pub link/Collateral/EVBUM2049-D.PDF.
full order observer and PLL system modeling in a single phase grid- [46] “LT8312 Boundary Mode PFC Controller,” Linear Technology, Online,
connected inverter,” in Power Electronics and ECCE Asia (ICPE ECCE), accessed in July 2015, available at http://cds.linear.com/docs/en/demo-
2011 IEEE 8th International Conference on, May 2011, pp. 803–808. board-manual/DC2104AF.PDF.
[28] T. Ostrem, W. Sulkowski, L. Norum, and C. Wang, “Grid Connected [47] “EVALPFC2-ICE1PCS01 300W PFC Evaluation Board with CCM
Photovoltaic (PV) Inverter with Robust Phase-Locked Loop (PLL),” in PFC controller ICE1PCS01,” Infineon, Online, accessed in March
Transmission Distribution Conference and Exposition: Latin America, 2015, available at http://www.infineon.com/dgdl/ICE1pcs01+pfc-
2006. TDC ’06. IEEE/PES, Aug 2006, pp. 1–7. ccm+demo+300w+V2.0.pdf.
[29] T. Almeida and M. Piedade, “High performance analog and digital PLL [48] C. Clark, F. Musavi, and W. Eberle, “Digital DCM Detection and
design,” in Circuits and Systems, 1999. ISCAS ’99. Proceedings of the Mixed Conduction Mode Control for Boost PFC Converters,” Power
1999 IEEE International Symposium on, vol. 4, May 1999, pp. 394–397 Electronics, IEEE Transactions on, vol. 29, no. 1, pp. 347–355, Jan
vol.4. 2014.
[30] R. Fried and Z. Azmanov, “Low-power digital PLL with one cycle
frequency lock-in time and large frequency-multiplication factor for ad-
vanced power management,” in Electronics, Circuits, and Systems, 1996.
ICECS ’96., Proceedings of the Third IEEE International Conference on,
vol. 2, Oct 1996, pp. 1166–1169 vol.2.
[31] L. Torok, L. Mathe, and S. Munk-Nielsen, “Robust control of boost PFC
converter using adaptive PLL for line synchronization,” in Industrial
Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE,
Nov 2013, pp. 7098–7102.
[32] J.-W. Ha, B.-S. Kong, J.-H. Chun, and B.-H. Park, “A fast response
integrated current-sensing circuit for peak-current-mode buck regulator,”
in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014
- 40th, Sept 2014, pp. 155–158.
[33] Y.-J. Ke, Y. fei Zhou, and J. ning Chen, “Control Bifurcation in PFC
Boost Converter under Peak Current-Mode Control,” in Power Electron-
ics and Motion Control Conference, 2006. IPEMC 2006. CES/IEEE 5th
International, vol. 2, Aug 2006, pp. 1–5.
[34] N. Zamani, M. Niroomand, and M. Ataei, “Bifurcation and chaos control
in power-factor-correction boost converter,” in Electrical Engineering
(ICEE), 2014 22nd Iranian Conference on, May 2014, pp. 1307–1312.
[35] M. Jovanovic, “Design trade-offs in continuous current-
mode controlled boost power-factor correction circuits,”
High Frequency Power Conversion Conference (HFPC 92),
Seventh International, accessed in February 2015, available at
http://www.deltartp.com/dpel/dpelconferencepapers/HFPC-92.
[36] M. C. Lee, X. Jing, and P. Mok, “A 14V-output adaptive-off-time boost
converter with quasi-fixed-frequency in full loading range,” in Circuits

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