1802 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO.

4, JULY/AUGUST 2011

A Simple Digital DCM Control Scheme for Boost

PFC Operating in Both CCM and DCM
Shu Fan Lim, Student Member, IEEE, and Ashwin M. Khambadkone, Senior Member, IEEE

Abstract—Digital average current controllers for boost power

factor correctors (PFCs) are usually designed for continuous con-
duction mode (CCM). However, discontinuous conduction mode
(DCM) appears in the inductor current near the zero crossings of
the input current at light loads, resulting in input current distor-
tion. It is caused by inaccurate average current values obtained
in DCM and by the linear CCM PFC controller that is unable
to ensure input current shaping in DCM whereby the converter
exhibits nonlinear characteristic. This paper proposes a simple
digital DCM control scheme that is achieved with minimal changes
to the CCM average current control structure. It is mathematically
and computationally simple. The result of all arithmetic opera-
tions in the proposed current control loop to obtain the desired
control output can be achieved in a single clock cycle, whereas
other DCM control schemes require multiple clock cycles. Good
input current shaping is achieved in both CCM and DCM with the
proposed CCM–DCM digital controller.
Index Terms—Boost power factor corrector (PFC), digital dis-
continuous conduction mode (DCM) current control, DCM, input
current distortion, PFCs.
Fig. 1. Conventional digital CCM average current control with input voltage
feedforward.
I. I NTRODUCTION

D IGITAL control for power factor correctors (PFCs) is

gaining industry attention due to design flexibility. Aver-
age current control is commonly used for boost PFC because
it is less sensitive to switching noise as compared to peak
current and hysteresis current control, and it can be easily
implemented in digital form. With input voltage feedforward,
the output dc voltage becomes less sensitive to variations in
the ac input voltage [1], [2]. Fig. 1 shows a boost PFC with
a conventional digital average current controller designed for
continuous conduction mode (CCM) operation [3]–[5].
At light loads, discontinuous conduction mode (DCM) will
occur in the inductor current. If the CCM average current
controller is used for control in DCM, it will result in input
current distortion. A boost PFC, with specifications and circuit
parameters shown in Fig. 2, is considered for the controller
Fig. 2. Boost PFC specifications and parameters.

Manuscript received September 2, 2010; revised January 5, 2011; ac-

cepted February 19, 2011. Date of publication May 12, 2011; date of design. The digital controller is coded in VHDL and is sim-
current version July 20, 2011. Paper No. 2010-IPCC-357.R1, presented at ulated with circuit models created in Simplorer [6]. Ten-bit
the 2010 IEEE Energy Conversion Congress and Exposition, Atlanta, GA,
September 12–16, and approved for publication in the IEEE T RANSACTIONS analog to digital converters (ADCs) are used in sampling the
ON I NDUSTRY A PPLICATIONS by the Industrial Power Converter Committee averaged inductor current, the rectified input voltage, and the
of the IEEE Industry Applications Society. output voltage. The average inductor current is obtained by
The authors are with the Electrical Machines and Drives Laboratory
(WS2-05-10), Department of Electrical and Computer Engineering, National sampling in the middle of the rising edge of the inductor current
University of Singapore, Singapore 117576 (e-mail: [email protected]; at every switching cycle. The input voltage is sampled together
[email protected]). with the inductor current. The average output voltage is ob-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. tained by averaging two consecutive samples that are sampled
Digital Object Identifier 10.1109/TIA.2011.2153815 every 5 ms.
0093-9994/$26.00 © 2011 IEEE
LIM AND KHAMBADKONE: SIMPLE DIGITAL DCM CONTROL SCHEME FOR BOOST PFC 1803

inductor current in DCM is proportional to the square of the

duty ratio and has a nonlinear characteristic. In Fig. 3, the CCM
controller tries to correct the current error that is caused by
inaccurate average current values obtained in DCM by reducing
the duty ratio to reduce the inductor current. However, the
converter exhibits nonlinear characteristics in DCM, and the
gain of the CCM controller is insufficient to quickly correct
the errors in DCM. This results in poor inductor current track-
ing and input current distortions when the inductor current is in
DCM. When the converter operates fully in DCM, as shown in
Fig. 4, iL is not tracking i∗L at all.
It is important to maintain good input current shaping at
heavy load as well as light load with the increasing focus on
energy efficiency. The 80 PLUS program [7] and the ENERGY
STAR program [8] are two main energy saving programs that
Fig. 3. Simulation results at 230 VAC and 0.4-p.u. load. target computer and server applications. They create a unique
product differentiation opportunity for the manufacturers be-
cause certified power supplies are significantly more efficient
than typical power supplies.
Both the 80 PLUS and ENERGY STAR programs introduce
an active mode efficiency requirement of 80% at 0.2-, 0.5-,
and 1-p.u. loads, with a power factor of 0.9 at 1-p.u. load.
The ENERGY STAR Program Requirements for Computers
(version 4.0) [9] additionally defined power consumption limits
for standby/off mode, sleep mode, and idle mode operations. In
the latest ENERGY STAR Program Requirements for Comput-
ers (version 5.0) [10] that is effective from July 1, 2009, these
efficiency requirements are further tightened to ensure energy
savings in all modes of operation and throughout the complete
load range. The 80 PLUS program also introduces higher effi-
ciency level of certifications, namely 80 PLUS Bronze, Silver,
and Gold, to further distinguish higher efficiency products in
Fig. 4. Simulation results at 230 VAC and 0.1-p.u. load.
2008. A new 80 PLUS Platinum certification is added in 2010,
and it requires power supply units to have an efficiency above
Fig. 3 shows the simulation result at an input voltage of 90% at 0.2-p.u. load, 92% at 0.5-p.u. load, and 89% at 1-p.u.
230 VAC and 0.4-p.u. (per unit) load, with the rated load as load. In addition, it requires a power factor of 0.95 at 0.5-p.u.
the base. CCM and DCM in the inductor current are observed load. In the ENERGY STAR specification for computer servers
in each ac half cycle. A power factor of 0.9805 is obtained. [11], light load power factor requirements of 0.65 at 0.1-p.u.
Fig. 4 shows the simulation result at an input voltage of load and 0.8 at 0.2-p.u. load are already included for power
230 VAC and 0.1-p.u. load. The converter operates fully in supplies with rated power above 500 W. These light load power
DCM. A power factor of 0.6455 is obtained. Input current factor requirements at 0.1- and 0.2-p.u. loads may be applied
distortions are observed in both cases. to power supplies with rated power below 500 W in future
There are two main causes of input current distortion. First, revision. A possible tightening of power factor requirement at
it is due to inaccurate average current values obtained in DCM. light load for power supplies of desktop computers and servers
The inductor current goes to zero before the end of the switch- may be expected.
ing period. Thus, the average is not given by sampling in the From these specifications, there are increasing energy effi-
middle of the rising edge of the inductor current. In Fig. 3, it can ciency and power factor requirements across the complete load
be observed that the sampled inductor current value iL is higher range. With the introduction of light load efficiency and power
than the average current reference i∗L near the zero crossings of factor requirements, it becomes important to improve input
the input current. current shaping at light load. Good input current shaping at light
The second cause of input current distortion is that the load will result in lower total harmonic distortion (THD) in the
linear CCM PFC controller is unable to ensure input current input current. A lower rms current will be drawn from the ac
shaping in DCM whereby the converter exhibits nonlinear mains. This will result in a higher power factor. Efficiency at
characteristics. Consider the case where there are CCM and light load will be improved with lower rms current flowing in
DCM in the inductor current in each ac half cycle. CCM occurs the circuit causing lower device losses. This helps in reducing
near the peak of the input current and has a linear relationship power consumption under light load conditions and in meeting
between the average inductor current and the duty ratio. DCM the light load power factor requirement that may be imposed in
appears near the zero crossings of the input current. The average future revision. The lower THD in the input current will enable
1804 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 4, JULY/AUGUST 2011

the power supplies to meet the IEC61000-3-2 harmonic current In [18], CCM and DCM converter characteristics are taken
emission standard [12], which defines the limits on harmonic into account by feedforward compensation of the duty ratio,
currents that can be injected into the public low-voltage mains where the lower value of the CCM and DCM duty ratios is
supply. Thus, the two causes of input current distortion need to added to the CCM average current controller output. The CCM
be solved to achieve higher power factor and higher efficiency average current controller is only compensating for small values
at light load. of the average inductor current error. This control scheme gives
To achieve good input current shaping over the complete load a smooth transition between CCM and DCM operations. Good
range, a linear CCM controller, a nonlinear DCM controller, input current shaping can be achieved across the complete load
and an operation mode selection circuit are employed in [13]. range. However, this method also requires a division followed
This analog control scheme is based on one-cycle control, by a square root calculation for the DCM duty ratio. For
where the average inductor current is controlled to be propor- implementation on ASIC or FPGA with 10-b ADC inputs and
tional to a carrier signal that is selected by the operating mode 9-b outputs from a division or square root calculation, the result
selection circuit. Carrier signals for CCM and DCM operations of all arithmetic operations in the current control loop to obtain
are generated separately. This control scheme gives a smooth the desired control output can be achieved in approximately 19
transition between CCM and DCM operations within an ac clock cycles. This control method is also parameter dependent.
half cycle, with a slight distortion in the input current during Thus, it is difficult to find an effective and computationally
the transition. When the converter operates fully in DCM, simple DCM controller to compensate for the nonlinearity
the distortion in the input current is worsened. Moreover, this in boost PFC. Other ways to implement DCM control for
dual analog control structure and the operation mode selection boost PFC include pulsewidth modulation (PWM), with fixed
circuit will result in higher development effort, complexity, frequency and duty ratio without an inner current controller.
and cost. The alternative approach is to solve for the duty However, input current distortion still exists because the aver-
cycle directly in the CCM average current control law of one aged equivalent circuit model of the boost PFC in DCM has a
cycle control, as shown in [14]. The digital computation of the nonlinear power source connected between the input and output
duty cycle is simple. For DCM, the control law is modified terminals [1], [2]. Nonlinear control techniques or nonlinear
from CCM based on weighted sum of two consecutive current gain for the changing operating point in one ac half cycle can
samples. However, the input current is distorted near the zero be used for the inner current loop controller in DCM. These are
crossings of the input current. The input current distortion is also computationally intensive.
worsened as the load reduces. This paper proposes a simple DCM control scheme for
In [15], a digital control scheme based on predictive current boost PFC. For input current shaping in DCM, no change is
control with direct calculation of the duty ratio in CCM and made to the CCM feedback average current controller. DCM
DCM is proposed. A mode selection algorithm based on the current control is achieved by changing the CCM feedforward
comparison between the actual duty ratio and the CCM duty controllers using a correction factor. The change in converter
ratio is used to determine the conduction mode of the inductor characteristics between CCM and DCM and the nonlinearity
current. The control scheme gives a smooth transition between in DCM are taken into account by the correction factor. This
CCM and DCM operations within an ac half cycle. Good input simplifies the DCM control design, and it is easy to implement
current shaping can be achieved across the complete load range. digitally. DCM control is achieved with minimal changes to
However, a division followed by a square root calculation is the CCM average current control structure. Compared to other
required in computing the DCM duty ratio, and two divisions DCM control schemes, no separate algorithms are required for
are required in computing the CCM duty ratio. Both division conduction mode selection, the CCM and DCM duty ratios.
and square root digital calculations are time-consuming iter- In addition, no complex and time-consuming duty ratio cal-
ative calculations involving multiple clock cycles. Nine clock culation in DCM is required in this proposed control scheme.
cycles are required to generate a 9-b output from a division or It is mathematically and computationally simple. The result
square root calculation [16], [17]. of all arithmetic operations in the proposed current control
With application-specific integrated circuit (ASIC) or field loop to obtain the desired control output can be achieved in a
programmable gate array (FPGA) implementation of the con- single clock cycle, whereas other DCM control schemes require
trol scheme, both CCM and DCM duty ratio calculations can be multiple clock cycles. The CCM average current controller and
done concurrently. However, the computational time is limited the proposed DCM control scheme provide a smooth transition
by the time required to compute the DCM duty ratio. With between CCM and DCM at light loads in each ac half cycle.
10-b ADC inputs and 9-b output from a division or square Good input current shaping is achievable across the complete
root calculation, the result of all arithmetic operations in the load range with the proposed CCM–DCM digital controller.
current control loop to obtain the desired duty ratio can be This paper also illustrates a simple method to obtain accurate
achieved in approximately 19 clock cycles. The higher amount average current values in DCM.
of computation in the digital algorithm will limit the switching This paper is organized into five sections. Section II il-
frequency to lower values, which, in turn, increase the size lustrates a simple method to obtain accurate average current
of the converter. The switching frequency can be increased values in DCM. Section III derives the proposed DCM control
by increasing the clock frequency. However, this will increase scheme for boost PFC. Section IV shows the performance of the
the cost of the controller. Moreover, this control method is proposed CCM–DCM control scheme. Section V concludes the
parameter dependent. analysis.
LIM AND KHAMBADKONE: SIMPLE DIGITAL DCM CONTROL SCHEME FOR BOOST PFC 1805

The inductor current samples are unaffected by the correc-

tion factor, and they give the average inductor current values.
In DCM,

(d + Δ1 ) < 1. (7)

As shown in Fig. 5, the average inductor current values are

lower than the inductor current samples in DCM. Thus, accurate
average inductor current values can be obtained by correcting
the inductor current samples with the correction factor.

III. P ROPOSED DCM C ONTROL S CHEME

Fig. 5. Inductor voltage and current in DCM.
Average small signal modeling technique is used to model
II. I NDUCTOR C URRENT S AMPLE C ORRECTION IN DCM the boost converter for the inner current control loop design
[1], [20]. The duty cycle d(t), rectified input voltage vg (t), and
Accurate average inductor current values are required for
inductor current iL (t) exhibit large signal variations in every
average current control. However, in DCM, the inductor current ac half cycle. The small signal assumption is valid only for the
goes to zero before the end of the switching period. Thus,
output voltage. When the boost PFC operates in steady state,
sampling in the middle of the rising edge of the inductor current
the output voltage in each switching period Tsw is
does not give the correct average values, as shown in Fig. 5 [19].
Consider the inductor voltage vL and inductor current iL vo (t)Tsw = Vo + v̂o (t) (8)
waveforms shown in Fig. 5 for a switching period Tsw , where
the input voltage vg and the output voltage vo exhibit very where
small variations and appear constant. Let iL,sampled , iL , and
iL,pk be the current sampled in the middle of the rising edge |v̂o (t)|  |Vo |. (9)
of the inductor current, the actual average inductor current, and
the peak of the inductor current, respectively. Sampling in the The average inductor voltage of the boost PFC in CCM
middle of the rising edge of the inductor current in DCM gives during a switching period Tsw is given by
1 d iL (t)Tsw
iL,sampled = iL,pk . (1) L = d(t) vg (t)Tsw
2 dt
 
However, the actual average inductor current is given by + d (t) vg (t)Tsw − vo (t)Tsw (10)
1 (d + Δ1 )Tsw
iL = iL,pk = iL,sampled (d + Δ1 ). (2) where L is the boost inductance. Substituting (8) into (10)
2 Tsw
d iL (t)Tsw
Since L = vg (t)Tsw −vo (t)Tsw +d(t)Vo +d(t)v̂o (t).
dt
(11)
vg dTsw (vo − vg )Δ1 Tsw
iL,pk = = (3)
L L Ignoring the second-order term d(t)v̂o (t) which is much
(d + Δ1 )vg = Δ1 vo + dvo − dvo (4) smaller in magnitude
d iL (t)Tsw
we get L = vg (t)Tsw − vo (t)Tsw + d(t)Vo . (12)
dt
dvo
(d + Δ1 ) = . (5) The averaged control to inductor current transfer function is
vo − v g
iL (s) Vo
The sensed values of the input and output voltages, the Hccm (s) = = . (13)
d(s) sL
resistor divider ratios that are used in sensing the input and
output voltages, and the duty ratio are required in computing Fig. 6 shows the inner current control loop for CCM oper-
the correction factor that is given in (5). The division in the ation. Gci (s) is an average current controller that is designed
correction factor is implemented using a lookup table for fast based on (13), and it ensures that iL tracks i∗L . In (12), the
computation. Accurate average current values can be obtained change in iL is also affected by vg and vo in each switching
in DCM by correcting the inductor current samples, obtained cycle. Gff,vg (s) and Gff,vo (s) are feedforward controllers that
by sampling in the middle of the rising edge of the inductor are used to offset the disturbance caused by vg and vo on
current, using the correction factor given in (5). In CCM iL , respectively. Symmetrical PWM employing a triangular
waveform with a peak value of Vm is used in the control
(d + Δ1 ) = 1. (6) scheme.
1806 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 4, JULY/AUGUST 2011

Fig. 6. Inner current control loop in CCM.

Fig. 8. Proposed CCM–DCM digital controller.

approaches that of Fig. 6. In DCM, (d + Δ1 ) < 1, and the

converter characteristic is given by (14). The change in con-
Fig. 7. Inner current control loop with the proposed DCM control scheme. verter characteristics between CCM and DCM, the nonlinearity
in DCM, and the inductor current sample correction are taken
At light loads, DCM appears near the zero crossings of the into account by the correction factor. This simplifies the DCM
input current. Consider the average inductor voltage of the control design, and it is easy to implement digitally. DCM
boost PFC in DCM during Tsw , as shown in Fig. 5 control is achieved with minimal changes to the CCM average
current control structure. It is mathematically and computation-
d iL (t)Tsw
L = d(t) vg (t)Tsw ally simple. With the use of a lookup table, the division in
dt the correction factor is implemented easily. The result of all
 
+ Δ1 (t) vg (t)Tsw − vo (t)Tsw arithmetic operations in the proposed current control loop to
obtain the desired control output can be achieved in a single
= (d(t) + Δ1 (t)) vg (t)Tsw clock cycle. Fig. 8 shows a boost PFC with the proposed
CCM–DCM digital controller that incorporates the proposed
− (d(t) + Δ1 (t)) vo (t)Tsw DCM control scheme into CCM average current control.
+ d(t) vo (t)Tsw . The compensated current control loop is designed to have a
gain crossover frequency of fc = 3.8 kHz and a phase margin
With (8) and (9), we have of 70◦ . The frequency response of the compensated current
control loop at a sampling rate of 50 kHz is shown in Fig. 9.
d iL (t)Tsw The compensated voltage control loop is designed to have a
L = (d(t) + Δ1 (t)) vg (t)Tsw
dt gain crossover frequency of fc = 25 Hz and a phase margin
− (d(t) + Δ1 (t)) vo (t)Tsw + d(t)Vo . (14) of 65◦ . The frequency response of the compensated voltage
control loop at a sampling rate of 200 Hz is shown in Fig. 10.
Comparing (12) and (14), the disturbances caused by vg and
vo on iL in DCM are affected by the correction factor (d +
IV. P ERFORMANCE OF THE P ROPOSED
Δ1 ) that is given in (5). Thus, DCM control can be achieved
CCM–DCM C ONTROL S CHEME
by keeping the same CCM average current controller Gci (s)
and by compensating the outputs of the CCM feedforward The proposed CCM–DCM digital controller is coded in
controllers Gff,vg (s) and Gff,vo (s) using the correction factor VHDL and is simulated with circuit models using Simplorer.
(d + Δ1 ) that is given in (5). This will effectively offset the Fig. 11 shows the simulation results at an input voltage of
disturbances caused by vg and vo on iL in DCM, while the 230 VAC and 0.4-p.u. load, with CCM and DCM in the inductor
CCM average current controller will compensate for small current observed in each ac half cycle. Fig. 12 shows the
values of the inductor current error. Fig. 7 shows the inner simulation results at an input voltage of 230 VAC and 0.1-p.u.
current control loop with the proposed DCM control scheme. load, where the converter operates fully in DCM.
In CCM, (d + Δ1 ) = 1, and the converter characteristic is Comparing with the case when only the CCM controller is
given by (12). The inner current control loop shown in Fig. 7 used, as shown in Figs. 3 and 4, accurate average inductor
LIM AND KHAMBADKONE: SIMPLE DIGITAL DCM CONTROL SCHEME FOR BOOST PFC 1807

Fig. 12. Simulation results at 230 VAC and 0.1-p.u. load with the proposed
Fig. 9. Frequency response of the compensated inner current control loop. CCM–DCM control scheme.

than the case when only the CCM controller is used, where
power factors of 0.9805 and 0.6455 are obtained for 0.4- and
0.1-p.u. loads, respectively. Thus, with inductor current sample
correction in DCM and with the proposed CCM–DCM control
scheme, good input current shaping and a higher power factor
at light load can be achieved.
The cause of the distortion in the input current during the
transition between CCM and DCM in Fig. 11 is that the correc-
tion factor did not sharply show the change between CCM and
DCM. This is due to quantization of the variables and coeffi-
cients in the calculation of the correction factor. In addition, this
is also because a hysteresis limit is added to prevent oscillation
in the correction factor, and hence the input current, during the
transition between CCM and DCM. When the correction factor
is above a certain threshold, it will be set to one. The THD
of the input current for harmonic frequencies of up to 2 kHz
Fig. 10. Frequency response of the compensated outer voltage control loop.
is 4.05%. This is significantly lower than the IEC61000-3-2
harmonic current requirement of 122.06% for the same input
power. Thus, the distortion in the input current during the
transition between CCM and DCM does not significantly affect
the performance of the proposed CCM–DCM controller.
In Fig. 12, a phase shift in the input current is observed.
The leading phase shift is caused by the electromagnetic in-
terference (EMI) filter capacitance. Since iL is tracking i∗L and
since i∗L is in phase with the rectified input voltage vg , the boost
converter cascaded after a diode bridge rectifier behaves like an
ideal rectifier and appears like a resistor load to the ac input.
At high load, the current flowing into the EMI filter capacitor
Cf is less significant than the current flowing into the rectifier.
Hence, phase shift is not observable, as shown in Fig. 13. At
light load, the current flowing into the rectifier reduces, while
the current flowing into Cf remains approximately the same
Fig. 11. Simulation results at 230 VAC and 0.4-p.u. load with the proposed for the same inductor current switching ripple and switching
CCM–DCM control scheme. frequency. The current flowing into Cf becomes comparable to
the current flowing into the rectifier, and the phase shift in the
current values are obtained in DCM with sample correction. input current becomes obvious. Thus, depending on the target
iL is tracking i∗L closely. There is a smooth transition between power factor at a defined light load, an optimized EMI filter
CCM and DCM operations of the boost converter in each ac design may be required to reduce the phase shift at light load.
half cycle, with minimal distortion in the input current during In order to reduce the phase shift and to improve the input
the transition. Power factors of 0.9929 and 0.9268 are obtained displacement factor at light load, a lower filter capacitance is
for 0.4- and 0.1-p.u. loads, respectively. These are higher required. The improvement in the EMI differential mode filter
1808 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 4, JULY/AUGUST 2011

Fig. 13. Phase shift at light load.

Fig. 15. Simulation results at 230 VAC and 0.4-p.u. load, with −10% offset
in (d + Δ1 ).

Fig. 14. Simulation results at 230 VAC and 0.1-p.u. load with the new
Fig. 16. Nonlinear inductance with respect to the input current.
EMI filter.

should be done without affecting converter stability because the current switching cycle will affect the average current in the
lowering the filter capacitance will increase the output im- next switching cycle. Fig. 15 shows the simulation results at an
pedance of the EMI filter. The output impedance of the EMI input voltage of 230 VAC and 0.4-p.u. load, with a −10% offset
filter should be significantly lower than the input impedance of in (d + Δ1 ). Both input current and output voltage remain
the converter for converter stability [1]. well regulated. With feedforward control to compensate for
A new EMI differential mode filter that gives the same the disturbances caused by vg and vo on iL , the fast current
current ripple attenuation and cutoff frequency is designed. The control loop will correct the small average current errors in
EMI filter capacitance Cf is approximately halved at 0.22 μF, the following switching cycle. Therefore, it is not required to
and the EMI filter inductance Lf is increased to 214 μH. Fig. 14 calibrate and download the lookup table for each manufactured
shows the simulation results at an input voltage of 230 VAC power supply if there is a change in value of the resistor divider
and 0.1-p.u. load with the new EMI filter. The phase shift in ratios due to the tolerances of the resistors. The outer voltage
the input current is significantly reduced, and the power factor control loop has a lower bandwidth of 25 Hz. Hence, error in
is improved to 0.9645. Hence, using an EMI differential mode (d + Δ1 ) estimation will not affect output voltage regulation.
filter that has a lower filter capacitance will reduce the phase The proposed CCM–DCM digital controller is designed
shift in the input current and will improve the power factor at based on a constant boost inductance L of 1.24 mH. To verify
light load. the robustness of the controller under parameter variation,
The average inductor current sample correction and DCM simulations are carried out with a large variation in the boost
control depend on the accuracy in the estimation of (d + Δ1 ) inductance. A nonlinear inductor simulation model is created
that is given in (5). The accuracy is affected by quantization in PExprt [21] using the natural soft saturation characteristic of
and any error in the sampling of the variables. In addition, Sendust powdered metal core. With the soft saturation charac-
the correction factor is dependent on the resistor divider ratios teristic of a powdered metal core, a design based on the desired
that are used in sensing the input and output voltages. The full load inductance at the peak value of the maximum input
common resistor tolerance values are 1% and 5%. If there is ac current will give a higher inductance at light load due to the
a change in the value of the resistor divider ratios due to the inherent core properties [22]. In Fig. 16, the designed nonlinear
tolerances of the resistors, the accuracy in the estimation of inductor has inductance varying from 0.66 to 1.66 mH as the
(d + Δ1 ) will be affected. An error in (d + Δ1 ) estimation in inductor current changes from 5.4 to 0 A.
LIM AND KHAMBADKONE: SIMPLE DIGITAL DCM CONTROL SCHEME FOR BOOST PFC 1809

Fig. 17. Simulation results at an input voltage of 85 VAC and full load, with Fig. 19. Experimental results at 230 VAC and full load, with sample correc-
a large variation in boost inductance. tion and with CCM–DCM control.

Fig. 18. Simulation results at an input voltage of 230 VAC and 0.4-p.u. load, Fig. 20. Experimental results at 230 VAC and 0.4-p.u. load, without sample
with a large variation in boost inductance. correction and with CCM control.

The nonlinear inductor simulation model replaces the con-

stant boost inductor in the circuit models created in Simplorer.
For the largest variation in the boost inductance, the boost
converter with the proposed CCM–DCM digital controller and
the nonlinear inductor is simulated under the minimum input
voltage of 85 VAC and full load where the maximum input
ac current flows. Fig. 17 shows the simulation results. Fig. 18
shows the simulation results at an input voltage of 230 VAC
and 0.4-p.u. load, with CCM and DCM in the inductor current
observed in each ac half cycle. Both input current and output
voltage remain well regulated. The proposed CCM–DCM con-
troller is able to work under such nonlinearity where there is a
large inductance variation.
The proposed CCM–DCM controller is implemented on
FPGA in the experimental setup. The only difference between Fig. 21. Experimental results at 230 VAC and 0.4-p.u. load, with sample
the experimental and simulation setups is that the EMI differ- correction and with CCM–DCM control.
ential mode filter inductance Lf is 70 μH in the experimental
setup instead of 100 μH in the simulation setup. The inductor show the experimental results at an input voltage of 230 VAC
current in all experimental results is measured at a point be- and 0.4-p.u. load using the CCM control and the proposed
tween the input EMI filter and the diode bridge rectifier. CCM–DCM control, respectively. CCM and DCM in the induc-
Fig. 19 shows the experimental results at an input voltage of tor current are observed in each ac half cycle. Figs. 22 and 23
230 VAC and full load using the proposed CCM–DCM control show the experimental results at an input voltage of 230 VAC
scheme. The converter operates fully in CCM. Figs. 20 and 21 and 0.1-p.u. load using the CCM control and the proposed
1810 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 4, JULY/AUGUST 2011

Fig. 24. Harmonic currents at an input voltage of 230 VAC and 0.4-p.u. load.
Fig. 22. Experimental results at 230 VAC and 0.1-p.u. load, without sample
correction and with CCM control.
rection in DCM and DCM feedforward compensation using
the correction factor because the correction factor is equal to
unity in CCM. Comparing Fig. 20 with Fig. 21 for 0.4-p.u.
load and comparing Fig. 22 with Fig. 23 for 0.1-p.u load, there
is an improvement in the input current waveform with sample
correction and with the proposed control scheme for CCM and
DCM. There is a smooth transition between CCM and DCM
operations of the boost converter in each ac half cycle, with
minimal distortion in the input current during the transition.
Thus, with inductor current sample correction in DCM and with
the proposed CCM–DCM control scheme, good input current
shaping can be achieved in both CCM and DCM. In Table I, it
can be observed that the THD of the input current for harmonic
frequencies of up to 2 kHz is significantly reduced with sample
correction and with the proposed CCM–DCM control scheme.
The power factor and efficiency at light load are also improved
with the proposed control scheme.
Fig. 23. Experimental results at 230 VAC and 0.1-p.u. load, with sample
correction and with CCM–DCM control. The experimental measurements of the power factor at 0.1-
and 0.4-p.u. loads differ from the simulation results because
TABLE I the EMI differential mode filter inductance Lf is 70 μH in
E XPERIMENTAL M EASUREMENTS AT AN I NPUT VOLTAGE OF 230 VAC the experimental setup instead of 100 μH in the simulation
setup. The slight current distortion near the zero crossings of
the input current is due to the maximum duty cycle limitation
for MOSFET protection. Phase shift in the input current at a
light load of 0.1-p.u. is observed, as discussed earlier from the
simulation results. The leading phase shift is caused by the EMI
filter capacitance.
Fig. 24 shows the IEC61000-3-2 harmonic current limits for
Class D equipment and the individual harmonic currents for
odd order harmonics from 2 up to 40 at 0.4-p.u. load using the
CCM control and the proposed CCM–DCM control. With the
proposed CCM–DCM control scheme, there is a significant re-
duction in the harmonic currents of lower harmonic orders. This
CCM–DCM control, respectively. The converter operates fully significantly reduces the THD of the input current by 21.27%.
in DCM. The experimental measurements of the THD of the A lower rms current will be drawn from the ac mains, and the
input current for harmonic frequencies of up to 2 kHz, the device losses in the boost PFC will be reduced. Efficiency is
power factor, and the efficiency in each of these cases are increased by 0.78% from 97.91% to 98.69%. In addition, the
summarized in Table I. power factor is improved from 0.897 to 0.951.
In Fig. 19, it can be seen that good input current shaping Fig. 25 shows that there is a fast transient response to a
is achieved at full load, where the converter operates fully in step change in load from 0.1-p.u. load, where the converter
CCM with the proposed CCM–DCM control scheme. Current operates fully in DCM, to 0.4-p.u. load, where the converter
control in CCM is unaffected by inductor current sample cor- operates in both CCM and DCM within the ac half cycle. The
LIM AND KHAMBADKONE: SIMPLE DIGITAL DCM CONTROL SCHEME FOR BOOST PFC 1811

can be used in sensing the input and output voltages. These

affect the control coefficients in both the proposed CCM–DCM
digital controller and the conventional CCM–DCM digital ap-
proaches. In the proposed CCM–DCM digital controller, a new
lookup table will be required for the new power supply design
if a different set of resistor dividers is used in sensing the input
and output voltages.
For ASIC implementation of the digital control schemes, the
control coefficients and the lookup table can be stored in a non-
volatile memory. A change in the power supply design involves
reprogramming the new control coefficients and lookup table
into the memory. The control structure is still the same. The
manufacturing cost and time involved in this partial redesign are
comparatively lower than that required by a complete controller
redesign. The manufacturing cost incurred with the partial
redesign is approximately 25% of the cost incurred with a
Fig. 25. Dynamic response to a step change in load from 0.1- to 0.4-p.u. load
at an input voltage of 230 VAC. complete controller redesign. The manufacturing time incurred
with the partial redesign involves the change and fabrication
proposed CCM–DCM control scheme with inductor current of several metal layers, whereas a complete controller redesign
sample correction works well even during transient. Good input requires more than six months to reach production stage [25],
current shaping is achieved in both power levels. [26]. Thus, this gives design flexibility and design reuse of
However, a problem with the proposed control method is that the proposed CCM–DCM digital controller to meet the design
a sufficiently high-resolution ADC is required in sampling vg , requirement for power supplies of different applications.
vo , and iL when high-quality input current shaping and a high
power factor at light load are demanded. More digital resources
V. C ONCLUSION
will also be required with the higher resolution ADCs used.
This leads to high cost of implementation. Thus, depending on A simple digital DCM control scheme for boost PFC has
the target power factor at a defined light load, a suitable ADC been proposed. For input current shaping in DCM, no change
resolution should be selected to meet cost and performance is made to the CCM feedback average current controller. DCM
requirements. current control is achieved by changing the CCM feedforward
The use of lookup table to implement the division in the cor- controllers using a correction factor. The change in converter
rection factor significantly reduces computational time as com- characteristics between CCM and DCM, the nonlinearity in
pared to conventional CCM–DCM digital approaches which DCM, and the inductor current sample correction in DCM are
require a division and a square root calculation. However, a taken into account by the correction factor. This simplifies the
large nonvolatile memory is required to store the lookup table. DCM control design, and it is easy to implement digitally. DCM
Hence, there is a tradeoff between computational time and control is achieved with minimal changes to the CCM average
memory cost. The cost of memory has decreased significantly current control structure. Compared to other DCM control
over the years. The memory cost per megabyte is US$106 in schemes, no separate algorithms are required for conduction
1990, US$1.56 in 2000, and US$0.001 in 2010 [23], [24]. mode selection, the CCM and DCM duty ratios. In addition, no
Thus, the memory required to hold the lookup table may not complex and time-consuming duty ratio calculation in DCM is
significantly increase material cost. required in this proposed control scheme. It is mathematically
Since a PFC is operating within the output voltage regulation and computationally simple. The result of all arithmetic opera-
range of ±5% of the rated output voltage most of the time, the tions in the proposed current control loop to obtain the desired
size of the lookup table can be limited by enabling the proposed control output can be achieved in a single clock cycle, whereas
DCM control only within the output voltage regulation range. other DCM control schemes require multiple clock cycles.
In this way, the size of the lookup table will be determined by The CCM average current controller and the proposed DCM
the output voltage regulation range and the number of bits that control scheme provide a smooth transition between CCM and
represents the denominator of the correction factor. With this DCM at light loads within each ac half cycle. Good input
added constraint, the memory required and the corresponding current shaping and a higher power factor are achievable in
material cost will be reduced. CCM and DCM over the complete load range with the proposed
Another problem that is common between the pro- CCM–DCM digital controller. With a higher power factor at
posed CCM–DCM digital controller and the conventional light load, meeting higher power factor requirement at light load
CCM–DCM digital approaches that require a division and will be possible for power supplies of desktop computers and
a square root calculation arises when there is a new power servers. Moreover, bringing the power factor at light load to be
supply design. The value of the boost inductance and current close to unity helps in reducing the rms current drawn from the
sensing resistance may be changed. Depending on the range and ac mains. This helps in reducing the power consumption under
maximum value of the input and output voltages defined for the light load conditions and in meeting the ENERGY STAR light
inputs of the controller, different values of resistor divider ratios load efficiency requirement.
1812 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 4, JULY/AUGUST 2011

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[10] ENERGY STAR, Energy Star Program Requirements for Computers: where she is currently working toward the Ph.D.
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Servers. nologies Asia Pacific Pte. Ltd., Singapore, as a Test
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pp. 198–204. Wuppertal, Germany, in 1995.
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system applied to a PFC boost converter operating in mixed conduction (NUS), Singapore, in 1998, where he is currently
mode,” in Proc. Brazilian Power Electron. Conf. COBEP, Sep. 2009, an Associate Professor with the Department of Elec-
pp. 698–704. trical and Computer Engineering. Since April 2010,
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NJ: Prentice-Hall, 1993. perimental Power Grid Center (EPGC), A∗ STAR,
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J. A. Melkebeek, “Sample correction for digitally controlled boost PFC Dr. Khambadkone was the recipient of the Outstanding Paper Award in
converters operating in both CCM and DCM,” in Proc. 18th IEEE APEC, 1991 and the Best Paper Award in 2002 from the IEEE T RANSACTIONS ON
Feb. 2003, vol. 1, pp. 389–395. I NDUSTRIAL E LECTRONICS, the Prize Paper Award from the IEEE Industry
[20] J. P. Noon, Designing High-Power Factor Off-Line Power Supplies. [On- Applications Society Industrial Power Converter Committee in 2005, and the
line]. Available: http://focus.ti.com/lit/ml/slup203.pdf Outstanding Educator Award in 2008 from the NUS.