Sequential Logic Circuits

Module 4 Part A

Faculty in Charge: Jagadeesh Kumar P

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 Sequential Logic Circuits
Sequential Circuit -

Consists of a combinational circuit to which storage elements are connected to

form a feedback path.

The binary information stored in the storage elements define the state of the
system.

The external binary inputs

received with the present
state of the storage
elements together
determine the binary value
of the outputs.
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 Sequential Logic Circuits
The block diagram demonstrates that the outputs in a sequential circuit are a
function not only of the inputs, but also of the present state of the storage
elements.

The next state of the storage elements is aIso a function of external inputs and
the present state.

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 Sequential Logic Circuits
There are two main types of sequential circuits, and their classification is a
function of the timing of their signals.

A synchronous sequential circuit is a system whose behavior can be defined

from the knowledge of its signals at discrete instants of time.

The behavior of an asynchronous sequential circuit depends upon the input

signals at any instant of time and the order in which the inputs change.

The storage elements commonly used in asynchronous sequential circuits are

time-delay devices.

Because of the feedback among logic gates, an asynchronous sequential circuit

may become unstable at times.

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 Sequential Logic Circuits
A synchronous sequential circuit employs signals that affect the storage
elements at only discrete instants of time.

Synchronization is achieved by a timing device called a clock generator which

provides a clock signal having the form of a periodic train of clock pulses.

The clock signal is commonly denoted by the identifiers clock and clk.

The clock pulses are distributed throughout the system in such a way that
storage elements are affected only with the arrival of each pulse.

Synchronous sequential circuits that use clock pulses to control storage elements
are called clocked sequential circuits and are the type most frequently
encountered in practice.

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 Sequential Logic Circuits

The storage elements

(memory) used in clocked
sequential circuits are called
flip-flops.

A flip-flop is a binary
storage device capable of
storing one bit of
information.

In a stable state, the output

of a flip-flop is either 0 or 1.
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 Synchronous Clocked Sequential Circuit

The outputs of synchronous clocked

sequential circuits are formed by a
combinational logic function of the
inputs to the circuit or the values
stored in the flip-flops (or both).

The value that is stored in a flip-flop

when the clock pulse occurs is also
determined by the inputs to the
circuit or the values presently
stored in the flip-flop ( or both).

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 Synchronous Clocked Sequential Circuit

The new value is stored ( ie. the

flip-flop is updated) when a pulse of
the clock signal occurs.

Prior to the occurrence of the clock

pulse, the combinational logic
forming the next value of the
flip-flop must have reached a
stable value.

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 Storage Elements - Latches

The storage element in a digital circuit can maintain a binary state indefinitely ( as
long as power is delivered to the circuit), until directed by an input signal to switch
the states.

The major difference among the types storage elements - are the no of i/ps they
possess as well as the manner in which the i/ps affect the binary state.

Storage elements that operate with signal levels ( rather than signal transitions)
are referred to as latches;

- those controlled by a clock transition are flip-flops.

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 Storage Elements - Latches

The two types of storage elements are related -

- Latches are the basic circuits from which all flip-flops are constructed.

Latches are said to be level sensitive devices

Flip-flops are edge-sensitive devices.

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 SR Latch
The SR latch is a circuit with two cross-coupled NOR gates or two
cross-coupled NAND gates,

- and two inputs labeled S for set and R for reset.

The SR latch constructed with two cross coupled NOR gates is

shown in Fig. 5.3.

The latch has two useful states.

When output Q = 1 and Q' = 0, the latch is said to be in the set

state.

When Q = 0 and Q' = 1, it is in the reset state.

Outputs Q and Q ' are normally the complement of each other.

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 SR Latch
Two input conditions cause the circuit to be in the set
state.

The first condition (S = 1, R = 0) is the action that must

be taken by input S to bring the circuit to the set state.

Removing the active input from S leaves the circuit in

the same state.

After both inputs return to 0, it is then possible to shift to

the reset state by momentary applying a 1 to the R input.

The 1 can then be removed from R, whereupon the

circuit remains in the reset state.
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 SR Latch
When both inputs S and R are equal to 0, the latch can
be in either the set or the reset state, depending on
which input was most recently a 1.

If a 1 is applied to both the S and R inputs of the latch,

both outputs go to 0, This action produces an undefined
next state, because the state that resuIts from the input
transitions depends on the order in which they return to 0.

It also violates the requirement that outputs be the

complement of each other.

In normal operation, this condition is avoided by making

sure that 1's are not applied to both inputs simultaneously.
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 SR Latch

The SR latch with two cross-coupled NAND

gates is shown in Fig. 5.4

It operates with both inputs normally at 1, unless

the state of the latch has to be changed.

Also referred to as S′R′ latch

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 SR Latch

Operation of SR latch can be modified by

providing an addition i/p signal - a control
signal - to define when the state of the
latch can be changed.

When the enable i/p goes to 1, information

from the S or R i/p is allowed to affect the
latch.

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 D Latch ( Transparent Latch )

One way to eliminate the

undesirable condition of the
indeterminate state in the SR
latch is to ensure that inputs S
and R are never equal to 1 at
the same time.

This is done in the D latch,

shown in Fig. 5.6.

D latch has only two inputs: D

(data) and En (enable).

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 D Latch ( Transparent Latch )
The D latch receives that designation from
its ability to hold data in its storage.

The binary information present at the data

input of the D latch is transferred to the Q
output when the enable input is asserted.

The output follows changes in the data input

as long as the enable input is asserted.

This situation provides a path from input D

to the output, and for this reason, the circuit
is often called a transparent latch.

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 Storage Elements ( Flip-Flops )
The state of a latch or flip-flop - is switched by a change in the control input.

This momentary change is called trigger.

D-Latch - when the control i/p remains at the logic-1 level, any change in the data input will
change the o/p and the state of the latch.

The key to the proper operation of a flip-flop - is to trigger it only during a signal transition.

Two ways in which the latches can be modified to form flip-flops.

1) Employ two latches in a special configuration that isolates the o/p of the flip-flop and
prevents it from being affected while the i/p to the flip-flop is changing.
2) Produce a flip-flop that triggers only during the signal transition ( from 0 to 1 or from 1 to 0)
of the synchronising signal (clock) and is disabled during the rest of the clock pulse.

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Storage Elements ( Flip-Flops )

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 Edge-Triggered D Flip-Flop
The construction of a D flip-flop with two D latches and an inverter is shown in Fig
5.9

The first latch is called the master and the second the slave.

The circuit samples the D

input and changes its output
Q only at the negative edge
of the synchronizing or
controlling clock (designated
as Clk)

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 Edge-Triggered D Flip-Flop
When the clock is 0, the slave latch is enabled and its output Q is equal to the
master output Y.

The master latch is disabled because CIk = 0.

When the input pulse changes to logic-1 level, the data from the external D input
are transferred to the master.

The slave however is disabled as long as

the clock remains at the 1 level.

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 Edge-Triggered D Flip-Flop
The behavior of the master-slave flip-flop

(1) The output may change only once.

(2) a change in the o/p is triggered by the negative edge of the clock, and

(3) the change may occur only during clock's negative level.

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 Edge-Triggered D Flip-Flop
It is also possible to design the circuit so that the flip-flop o/p changes on the +ve
edge of the clock.

Using an additional inverter at the clock

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 Edge-Triggered D Flip-Flop Using Three S-R latches
Two latches respond to the
external data ( D-i/p) and Clk
i/ps.

The third latch provides the o/p

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 Setup and Hold Time
The timing of the response of a flip-flop to input data and to the cbck must be
taken into consideration when one is using edge-triggered flip-flops.

There is a minimum time called the setup time during which the D input must be
maintained at a constant value prior to the occurrence of the clock transition.

Similarly, there is a minimum time called the hold time during which the D input
must not change after the application of the positive transition of the clock.

The propagation delay time of the flip-flop is defined as the interval between the
trigger edge and the stabilization of the output to a new state.

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 JK Flip-Flop
There are three operations that can be
performed with a flip-flop

- Set it to 1

- Reset it to 0

- Complement its o/p

Since D flip-flop has only one input, it can set or

reset the o/p depending on the value of the D i/p
immediately before the clock transition.

Synchronised by a clock signal the J-K Flip-flop

has two i/ps and performs all the three
operations.
The JK flip-flop is named after his inventor known as Jack Kilby from Texas
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Instruments.
 JK Flip-Flop
J i/p sets the Flip-flop to 1

K i/p reset the Flip-flop to 0

When both the i/ps are enabled, the o/p is complemented.

D = JQ′ + K′Q

When J = 1 and K = 0, D = Q′ + Q = 1, so the next clock edge sets the o/p

to 1

When J = 0 and K = 1, D = 0, so the next clock edge resets the o/p to 0

When both J = K = 1 and D = Q′, the next clock edge complements the o/p.

When both J = K = 0 and D = Q, the clock edge leaves the o/p unchanged.

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 T ( toggle ) Flip-Flop
The T (toggle) Flip-flop is a complementing
flip-flop.

It can be obtained from a JK flip-flop when

i/ps J and K are tied together.

When T = 0 ( J=K=0), a clock edge does not

change the o/p.

When T = 1 ( J=K=1), a clock edge

complements the o/p.

The complementing flip-flop is useful for

designing binary counters.
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 T ( toggle ) Flip-Flop
T flip flop can be constructed with a D flip-flop
and an exclusive OR gate as shown in the Fig.

The expression for D input is D = T ⊕ Q

= TQ′ + T′Q

When T = 0, D = Q and there is no change in

the o/p

When T = 1, D = Q′ and the o/p complements.

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 Characteristic Tables
A characteristic table defines the logical properties of a
flip-flop by describing its operation in tabular form.

The characteristic tables of three types of flip-flops are

presented in Table 5.1

They define the next state (i.e., the state that results from
a clock transition) as a function of the inputs and the
present state.

Q(t) refers to the present state (it., the state present prior
to the application of a clock edge).

Q( t + 1 ) is the next state one clock period later.

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 Characteristic Equations
The logical properties of a flip-flop, as
described in the characteristic table, can
be expressed algebraically with a
characteristic equation.

For the D flip-flop, the characteristic

equation is Q(t+1) = D

- states that the next state of the o/p will

be equal to the value of the D i/p in the
present state

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 Characteristic Equations
For the JK flip-flop, the characteristic
equation can be derived from the
characteristic table or from the circuit of Fig
5.12

Q(t+1) = JQ′ + K′Q

- where Q is the value of the flip-flop o/p

prior to the application of a clock edge.

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 Characteristic Equations
For the T flip-flop, the characteristic
equation can be derived from the
characteristic table or from the circuit of Fig
5.13

Q(t+1) = T ⊕ Q = TQ′ + T′Q

- where Q is the value of the flip-flop o/p

prior to the application of a clock edge.

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 Direct inputs
Some flip-flops have asynchronous inputs

- which force the flip-flop to a particular state independently of the clock.

The i/p that sets the the flip-flop to one is called a preset or direct set.

The i/p that clears the flip-flop to zero is called clear or direct reset.

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 Direct inputs
A positive-edge-triggered D flip-flop with active-low asynchronous reset is
shown in Fig. 5.14.

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