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Uday Banala 1706544614

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53 views2 pages

Uday Banala 1706544614

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7mrjfxp9tf
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Uday Banala

+91 8886363684 [email protected] https://www.linkedin.com/in/uday-banala-vlsi/

CAREER OBJECTIVE

Desires to start an active career in ASIC/FPGA Front-End Design and Verification. Eager to apply
foundational knowledge in Verilog, VHDL, and System Verilog with a keen interest in EDA tools to support
new projects. Committed to continuous learning, I aim to bring passion and fresh perspective to a dynamic
team.

EDUCATION

Btech in Electronics and Communication Engineering Sep 2021 - April 2024


Parul University
CGPA : 8.54/Till 6th sem

Diploma in Electronics and Communication Engineering Jun 2018 - April 2021


TRR College of Technology
CGPA : 8.27

Secondary Education (SSC) Jun 2017 - April 2018


Nalanda Vidhyanekethan High School
CGPA : 8.8

PROFESSIONAL TRAINING

Advanced VLSI Design & Verification Course


Maven Silicon VLSI Design and Training Centre, Bangalore.

TECHNICAL SKILLS

HDL: Verilog, VHDL


HDVL: Knowledge in System Verilog
DOMAIN: ASIC/FPGA Front-End Design and Verification
EDA Tools: Mentor Graphics -Questasim, Modelsim, Intel Quartus Prime, Xilinx- ISE, Xilinx-Vivado
TB Methodology: Knowledge in Universal Verification Methodology (UVM)
Verification Methodologies: Knowledge in Constraint Random Coverage Driven Verification (CRCDV),
Assertion Based Verification -SVA
Operating Systems: Linux, Windows
Core Skills: RTL Coding using Synthesizable constructs of Verilog, FSM based design, Simulation,
CMOS Fundamentals, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis.
Programming Skills: Knowledge in C [Datatype | Array | Pointers | Memory Allocation | List | Queues
and stacks || C++ [Good knowledge of OOPs concept, Class, Inheritance,
Polymorphism]
PROJECTS

Power Optimization in RTL Design


Tools: Xilinx Vivado
-Taking an ALU as a Design Block and Implementing clock gating Technique Pre and Post analysis using
Vivado Xilinx and Complete Verilog Programming for Power, Area Minimization.

Router 1*3 Packet Design


Tools: ModelSim, QuartusPrime, QuestaSim
-Architected the block level structure for the Router that accepts data packets on a single 8-bit port and routes
-them to one of the three output channels.
-The Top module design consists of four sub modules: FIFO, Synchronizer, Register and FSM.
-Written and verified the functioning of individual modules and the whole model with linear testbenches.

Missile Detection and Auto Destroy System


Tools: Aurdino IDE
Purpose of the project is to automatic object detection and destroying system using Arduino and
ultrasonic sensor.

Design And Implementation of Asynchronous FIFO


Tools: ModelSim, QuartusPrime, Questasim
Designed an Asynchronous FIFO of depth N using Verilog and simulated it using Modelsim.
Implemented Two lip-Flop Synchronizer along with full and empty signals to avoid meta-stability issues in
CDC and Overflow/Underflow conditions respectively.

RELAVENT COURSES & CERTIFICATIONS


Advanced VLSI Design and Verification in Maven Silicon

Vlsi SOC Design from Maven Silicon

Learning Verilog for FPGA Development

Complete Verilog HDL programming with Examples and Projects from Udemy

PCB Design with Kicad from Udemy

ACHIEVMENTS
Maven Silicon Star of the Month.
Secured Second Position in National level circuit Design 2.0
Group Compition Winner in Robotronix Embedded Workshop.

DECLARATION
I declare that all the information provided in this document is true to the best of my knowledge and belief. It
is my responsibility to make sure that the above-mentioned details are accurate.

Date:__/___/______
Place: Hyderabad Uday Banala

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