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CSD Notes

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20 views

CSD Notes

Uploaded by

tejghorpade9
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Type Transfer function Improves Comments

•Pole at origin
•Zero near origin
•Increases system type
•May introduce aslow
Lag Error
transient
•Active circuitry required
•Susceptible to integrator
windup
 Lower-frequency zero
 Higher-frequency pole
 Net angle contribution
satisfies angle criterion at
Transient design point
Lead
Response  Added pole helps reduce
amplification of higher-
frequency sensor noise
 Passive circuitry
implementation possible
 Leadcompensation
improves transient
response
Error &  Lag compensation improves
Lead – Lag transient steady-state error
response  Passive circuitry
implementation possible
 Amplification of high-
frequency noise reduced

For K, z, p are all real and (+ve) values to be found two combinations: -
a) Lead compensator (p > z) and
b) Lag Compensator (p < z)
Design of Compensator using Root Locus

Design Steps for Lead Compensator using Root Locus

Design

To find K, z, p, use following steps

1. Find desired pole sd location using


√

2. Find angle of deficiency

3. Connect sd to origin.
4. Draw a horizontal line to the left from sd

5. Find the bisector of the above two lines


6. Draw two lines that make angles ⁄ ⁄ with the bisector

7. Their intersections with the real lines are −p and −z

8. Put values of p and z in

9. All points on the RL satisfy

10.sd belong to Root Locus find K from


_________________________________________________________________________________

Design Steps for Lag Compensator using Root Locus

Design

To find K, z, p, use following steps

1. Find desired pole sd location using


√

2. Find angle of deficiency

3. Connect sd to origin.
4. Draw a horizontal line to the left from sd
5. Find the bisector of the above two lines
6. Draw two lines that make angles ⁄ ⁄ with the bisector
7. Their intersections with the real lines are −p and −z

8. Put values of p and z in


9. All points on the RL satisfy
10. sd belong to Root Locus find K from

Design steps for Lag – Lead Compensator using Root Locus

1. Evaluate the performance of the uncompensated system to determine how much


improvement in transient response is required.
2. Design the lead compensator to meet the transient response specifications. The design
includes the zero location, pole location, and the loop gain.
3. Simulate the system to be sure all requirements have been met.
4. Redesign if the simulation shows that requirements have not been met.
5. Evaluate the steady-state error performance for the lead-compensated system to
determine how much more improvement in steady-state error is required.
6. Design the lag compensator to yield the required steady-state error.
7. Simulate the system to be sure all requirements have been met.
8. Redesign if the simulation shows that requirements have not been met.
-------------------------------------------------------------------------------------------------------------------------

Design of Compensator using Bode Plot

Lag Compensator Design Using Frequency Response


1‐Find the Loop Gain L(s) = G(s)H(s).
2‐Determine K that would give the desired Kv.
3‐Draw Bode Plot of L1(s) = KG(s)H(s).
‐Must compensate for K changes the PM requirement.
‐Evaluate the PM.
4‐Add 50 to 120 because of the increase in the gain due to the zero
5-Determine α from the required PM.
‐The new zero crossing occurs at frequency is where ωm is located.
- It is where the gain of L1(s) is given as

6‐Determine the location of the zero and the pole as:


7‐Choose the value of Kc from .
8‐Check the GM and PM requirements. If not met, reiterate the process.
(Usually, you need to go to step 4 and add more phase).
--------------------------------------------------------------------------------------------------------------------------

Lead Compensator Design Using Frequency Response


1‐Find the Loop Gain L(s) = G(s)H(s).
2‐Determine K= αKc that would give the desired Kv.
3‐Draw Bode Plot of L1(s) = KG(s)H(s).
‐Must compensate for K changes the PM requirement.
‐Evaluate the PM.
4‐Add 50 to 120 because of the increase in the gain due to the zero
5-Determine α from the required PM.
‐The new zero crossing occurs at frequency is where ωm is located.
- It is where the gain of L1(s) is given as

√
6‐Determine the location of the zero and the pole as:
√
√
7‐Choose the value of Kc from K = αKc.
8‐Check the GM and PM requirements. If not met, reiterate the process.
(Usually, you need to go to step 4 and add more phase).
-------------------------------------------------------------------------------------------------------------------------

Design step of Lag – Lead Compensator


1. Using a second-order approximation, find the closed-loop bandwidth required to meet
the settling time, peak time, or rise time requirement.
2. Set the gain, K, to the value required by the steady-state error specification.
3. Plot the Bode magnitude and phase diagrams for this value of gain.
4. Using a second-order approximation, calculate the phase margin to meet the damping
ratio or percent overshoot requirement.
5. Select a new phase-margin frequency near ω BW.
6. At the new phase-margin frequency, determine the additional amount of phase lead
required to meet the phase-margin requirement. Add a small contribution that will be
required after the addition of the lag compensator.
7. Design the lag compensator by selecting the higher break frequency one decade below
the new phase-margin frequency. The design of the lag compensator is not critical, and any
design for the proper phase margin will be relegated to the lead compensator. The lag
compensator simply provides stabilization of the system with the gain required for the
steady-state error specification. Find the value of γ from the lead compensator’s
requirements. Using the phase required from the lead compensator, the phase response
curve can be used to find the value of γ . 1=β. This value, along with the previously found
lag’s upper break frequency, allows us to find the lag’s lower break frequency.
8. Design the lead compensator. Using the value of γ from the lag compensator design and
the value assumed for the new phase-margin frequency, find the lower and upper break
frequencies for the lead compensator, and solving for T.
9. Check the bandwidth to be sure the speed requirement in Step 1 has been met.
10. Redesign if phase-margin or transient specifications are not met, as shown by analysis or
simulation.

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