Integration of AI in VLSI

A Seminar Report
Submitted to the APJ Abdul Kalam Technological University
in partial fulfillment of requirements for the award of degree

Bachelor of Technology
in
Electronics and Communication Engineering
by
Muhammed Adnan Yakoob
TLY21EC051

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COLLEGE OF ENGINEERING THALASSERY
KERALA
November 2024
 COLLEGE OF ENGINEERING THALASSERY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

VISION

To render activities that create and transfer a new technology in electronics and
communication to meet the industrial needs and for the benefits of society.

MISSION

• Ensuring effective teaching-learning process to provide in-depth knowledge

of basic principles and its applications in Electronics and Communication
Engineering.

• To educate the students to meet the growing challenges of industry.

• To develop professional attitudes and ethical values to have a productive career

and to serve humanity.
 DEPT. OF ELECTRONICS & COMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING THALASSERY
2024 - 2025

CERTIFICATE

This is to certify that the report entitled Integration of AI in VLSI submitted by

Muhammed Adnan Yakoob (TLY21EC051), to the APJ Abdul Kalam Technological
University in partial fulfillment of the B.Tech. degree in Electronics and Communica-
tion Engineering is a bonafide record of the seminar work carried out by him under
our guidance and supervision. This report in any form has not been submitted to any
other University or Institute for any purpose.

Prof. Anagha V K Prof. Jinesh.S

(Seminar Guide) (Seminar Coordinator)
Assistant Professor Assistant Professor
Dept.of ECE Dept.of ECE
College of Engineering College of Engineering
Thalassery Thalassery

Dr. Sudheer V R
Professor and Head
Dept.of ECE
College of Engineering
Thalassery
 DECLARATION

I Muhammed Adnan Yakoob hereby declare that the seminar report Integration of AI
in VLSI, submitted for partial fulfillment of the requirements for the award of degree
of Bachelor of Technology of the APJ Abdul Kalam Technological University, Kerala
is a bonafide work done by me under supervision of Prof. Anagha V K
This submission represents my ideas in my own words and where ideas or words
of others have been included, I have adequately and accurately cited and referenced
the original sources.
I also declare that I have adhered to ethics of academic honesty and integrity
and have not misrepresented or fabricated any data or idea or fact or source in my
submission. I understand that any violation of the above will be a cause for disciplinary
action by the institute and/or the University and can also evoke penal action from the
sources which have thus not been properly cited or from whom proper permission has
not been obtained. This report has not been previously formed the basis for the award
of any degree, diploma or similar title of any other University.

Thalassery
04-11-2024

Muhammed Adnan Yakoob

Abstract

This report explores the integration of Artificial Intelligence (AI) within the field of
Very Large Scale Integration (VLSI) design. It examines the role AI-driven tools, such
as Cadence Cerebrus, Synopsys DSO.ai, and Verisium AI, play across different stages
of VLSI design. These tools streamline processes including architectural design, logic
synthesis, and verification, addressing industry challenges such as design complexity,
power efficiency, and faster time-to-market. The report includes real-world case studies
from industry leaders like Qualcomm, AMD, and GlobalFoundries, demonstrating the
significant performance gains and cost efficiency achieved through AI. Future trends
such as enhanced automation, adaptive systems, and environmentally responsible
design are also discussed, highlighting AI’s transformative potential in VLSI design.

i
Acknowledgement

I take this opportunity to express my deepest sense of gratitude and sincere thanks to
everyone who helped me to complete this work successfully. I express my sincere
thanks to Dr. Sudheer V R, Head of Department, Electronics and Communication
Engineering, College of Engineering Thalassery Thalassery for providing me with all
the necessary facilities and support.
I would like to express my sincere gratitude to Prof. Jinesh.S and , depart-
ment of Electronics and Communication Engineering, College of Engineering
Thalassery Thalassery for their support and co-operation.
I would like to place on record my sincere gratitude to my seminar guide Prof. Anagha
V K, Assistant Professor, Electronics and Communication Engineering, College of
Engineering Thalassery for the guidance and mentorship throughout the course.
Finally I thank my family, and friends who contributed to the succesful fulfilment
of this seminar work.

Muhammed Adnan Yakoob

ii
Contents

Abstract i

Acknowledgement ii

List of Figures iv

1 Introduction 1
1.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Literature Survey 3
2.1 AI Techniques in VLSI Design Automation . . . . . . . . . . . . . . 3
2.2 Software Tools for AI-Driven VLSI Design . . . . . . . . . . . . . . 4
2.3 Challenges and Future Directions . . . . . . . . . . . . . . . . . . . . 5

3 Integration of AI in VLSI Design 6

3.1 Architectural Design Automation Using Cadence Cerebrus . . . . . . 8
3.2 Logic Synthesis Using Synopsys DSO.ai . . . . . . . . . . . . . . . . 12
3.3 PCB Design Using Cadence Allegro X . . . . . . . . . . . . . . . . . 14
3.4 Physical Design Using Cadence Innovus . . . . . . . . . . . . . . . . 16
3.5 Verification Using Verisium AI . . . . . . . . . . . . . . . . . . . . . 19
3.6 Manufacturing Using Synopsys Yield Explorer . . . . . . . . . . . . 21

4 Conclusion 26

References 27

iii
List of Figures

3.1 Cadence Cerebrus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Architectural Design Stages Cadence . . . . . . . . . . . . . . . . . . 9
3.3 Cerebrus improves PPA/Productivity curve . . . . . . . . . . . . . . . 10
3.4 Density Distribution: Base vs Cerebrus Optimization . . . . . . . . . 11
3.5 Synopsys DSO.ai . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Allegro X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 AI-Driven Layout and Routing in Allegro X . . . . . . . . . . . . . . 16
3.8 Cadence Innovus Interface . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Efficiency Gains with Cadence Innovus . . . . . . . . . . . . . . . . 19
3.10 Verisium platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Synopsys Yield Explorer Interface . . . . . . . . . . . . . . . . . . . 22
3.12 Yield Explorer collects data from fab, test and EDA domains to enable
faster discovery of yield root-cause sources . . . . . . . . . . . . . . 23

iv
Chapter 1

Introduction

1.0.1 Motivation

The semiconductor industry is at a pivotal moment, driven by the demand for advanced
chip designs that support emerging technologies, such as artificial intelligence (AI),
Internet of Things (IoT), and 5G networks. Traditional chip design approaches
face challenges due to increasingly complex specifications, growing pressure for
faster time-to-market, and the need to reduce power consumption and costs. With
each generation of semiconductor technology, design requirements become more
demanding, necessitating greater precision and efficiency throughout the design
process. AI has emerged as a transformative solution, bringing automation and
optimization capabilities to electronic design automation (EDA) tools. By integrating
AI, designers can achieve faster and more accurate outcomes, from architectural
decisions to post-silicon validation, thus transforming the entire chip design workflow.

1.0.2 Background

Recent advancements in AI, particularly in machine learning and reinforcement learn-

ing, have catalyzed significant innovations in EDA. Tools leveraging AI algorithms
can now autonomously perform tasks traditionally handled by engineers, such as
logic synthesis, verification, physical design, and layout optimization. For instance,
Synopsys’s DSO.ai applies reinforcement learning to physical design, optimizing
parameters to achieve target performance, power, and area (PPA) goals. Meanwhile,

1
Cadence Verisium employs machine learning to enhance verification processes, help-
ing identify and address design flaws early in the flow. Large Language Models
(LLMs), like those used in Google’s Pathfinding Tool, are also becoming integral to
early-stage design, enabling designers to explore and validate multiple architecture
options efficiently. These tools not only streamline various stages of design but also
address bottlenecks, allowing the semiconductor industry to keep pace with rapid
technological advancements.

1.1 Objectives
The primary aim of this project is to explore the latest AI-driven automation tools in
chip design, analyzing their applications, benefits, and future potential across the EDA
stages.

• To identify AI-driven tools used in various EDA stages: This involves a

comprehensive analysis of tools that automate tasks such as logic synthesis,
physical design, verification, and timing analysis, with a focus on efficiency and
accuracy improvements.

• To evaluate AI’s impact on design productivity and quality: AI tools can

significantly reduce design time while maintaining or improving quality metrics.
The study will examine how these tools enhance performance, reduce costs, and
minimize errors.

• To analyze case studies and recent implementations: By reviewing specific

cases, such as the application of DSO.ai in layout optimization and Verisium in
verification, the study will highlight real-world applications and their outcomes.

• To forecast AI’s future role in chip design: With the continuous evolution
of AI, this project will discuss potential advancements, including integration
with LLMs for multi-stage optimization and increased automation in post-silicon
testing.

2
Chapter 2

Literature Survey

2.1 AI Techniques in VLSI Design Automation

The integration of Artificial Intelligence (AI) techniques in VLSI design automation is
addressing challenges related to complexity, performance, and efficiency. This section
reviews key AI methodologies employed in different VLSI design stages, including
architectural design, logic synthesis, physical design, and verification.

2.1.1 Architectural Design

AI plays a crucial role in optimizing architectural configurations in VLSI design. Chen

et al. (2023) used reinforcement learning (RL) to dynamically adjust parameters
based on simulation feedback, streamlining design exploration. Similarly, Zhang et
al. (2023) applied generative adversarial networks (GANs) for innovative architectural
exploration, demonstrating AI’s potential to surpass traditional methods.

2.1.2 Logic Synthesis

AI enhances logic synthesis by improving design metrics such as area and power
consumption. Wang and Liu (2024) utilized neural networks to optimize Boolean
function synthesis, while Patel et al. (2023) employed decision trees to simplify
technology mapping. These approaches showcase AI’s ability to streamline the
synthesis process and improve performance.

3
2.1.3 Physical Design

AI methodologies in physical design focus on layout and routing optimizations. Liu et

al. (2024) used support vector machines (SVMs) to predict congestion during layout,
enhancing circuit performance by reducing wire length. Kumar et al. (2024) applied
deep learning to placement, enabling efficient layout strategies that minimize timing
violations.

2.1.4 Verification

In verification, AI facilitates equivalence checking and validation. Gupta et al.

(2023) demonstrated convolutional neural networks (CNNs) for identifying design
discrepancies, significantly reducing verification time. Zhao et al. (2023) applied
unsupervised learning to detect design errors, improving upon traditional verification
methods.

2.2 Software Tools for AI-Driven VLSI Design

Various AI-enhanced software tools support VLSI design by improving efficiency and
accessibility.

2.2.1 Cadence Design Systems

Cadence provides AI-powered tools such as Virtuoso, which employs machine learning
for automated layout generation, and Allegro, which utilizes predictive analytics for
real-time signal integrity analysis. These tools streamline the design process and allow
for efficient collaboration.

2.2.2 Synopsys

Synopsys integrates AI in tools like Design Compiler, using optimization algorithms

for improved synthesis, and HSPICE, which enhances simulation accuracy through
predictive modeling. These advancements make Synopsys tools a strong choice for
AI-driven VLSI design.

4
2.2.3 Mentor Graphics

Mentor Graphics focuses on AI for both PCB design and lithography verification.
Tools like Expedition optimize layout with AI, while Calibre applies machine learning
to ensure design manufacturability. Their resources support efficient usage of AI-
enhanced functionalities.

2.3 Challenges and Future Directions

Despite the potential of AI in VLSI design, challenges remain. High-quality data,
model interpretability, and tool integration are critical for effective AI applications.
Future advancements in machine learning and hybrid approaches may enable AI tools
to handle complex design challenges autonomously.

2.3.1 Advancements in Deep Learning for VLSI Design

Deep learning is increasingly applied in VLSI design. Nguyen et al. (2024) developed
a deep neural network for timing analysis, achieving over 90

2.3.2 Limitations of Current AI Implementations

Despite progress, AI in VLSI design has limitations. Sharma et al. (2024) noted
that many AI models struggle to scale for large designs, requiring retraining with
new datasets. Additionally, Chang and Lee (2023) observed that AI tools often lack
interpretability, which can hinder designer trust and adoption.

2.3.3 Integration with Traditional Electronic Design Automation

Tools

Combining AI with Electronic Design Automation (EDA) tools can enhance design
efficiency. Chen et al. (2023) proposed a hybrid framework integrating AI with tradi-
tional synthesis and verification methods, allowing designers to transition seamlessly
between automated and manual processes. Zhang and Xu (2023) introduced a plug-in
architecture, enabling AI tools to enhance existing EDA workflows without overhauls.

5
Chapter 3

Integration of AI in VLSI Design

Table 3.1: Chip Design Stages and AI Tools

Design Stage AI Tool

Architectural Design Cadence Cerebrus

Logic Synthesis Synopsys DSO.ai

PCB Design Allegro X

Physical Design Cadence Innovus

Verification Verisium AI

Manufacturing Synopsys Yield Explorer

6
 Table 3.2: Automation Impact on Chip Design Stages

Design Stage and Automated Processes Impact (Efficiency Improvement and

Time Saved)

Architectural Design: Up to 30% faster exploration

Automated exploration and optimization of Time Saved: 1-2 weeks
design space using AI

Logic Synthesis: Increases synthesis efficiency by 20-25%

Automated logic synthesis with high- Time Saved: 1 week
performance tuning

PCB Design: Improves design accuracy, reducing itera-

Automated PCB layout and in-design anal- tion time by 20%
ysis Time Saved: 2 weeks

Physical Design: Enhances placement accuracy, reducing

Automated placement and routing design cycle by 15-20%
Time Saved: 2-3 weeks

Verification: Improves verification coverage by 40%

Intelligent test generation and bug predic- Time Saved: 3-4 weeks
tion with AI assistance

Manufacturing: Reduces failure rate by 25-30%

Predictive yield analysis and defect detec- Time Saved: 2 weeks
tion

7
3.1 Architectural Design Automation Using Cadence
Cerebrus

3.1.1 What is Cadence Cerebrus?

Cadence Cerebrus is a state-of-the-art tool for architectural design automation, offer-

ing:

• AI-Driven Optimization: Uses machine learning to predict design outcomes.

• Automated Design Space Exploration: Quickly evaluates numerous design

alternatives.

Figure 3.1: Cadence Cerebrus

8
3.1.2 How Cadence Cerebrus Transforms Architectural Design

Cadence Cerebrus automates repetitive tasks, leading to significant time savings.

Reports indicate up to a 40% reduction in design time compared to traditional methods.

Figure 3.2: Architectural Design Stages Cadence

3.1.3 Key Stages in Architectural Design

The architectural design process includes:

1. Specification of performance targets

2. Exploration of design options

3. Optimization for power and performance

9
 Figure 3.3: Cerebrus improves PPA/Productivity curve

3.1.4 Case Study: Qualcomm

Qualcomm employed Cadence Cerebrus for the architectural design of its latest 5G
chip series, which aimed to enhance mobile connectivity and performance. Here’s
how they utilized the tool:

• Usage:

– Design Space Exploration: Cadence Cerebrus allowed Qualcomm’s

engineers to rapidly evaluate various design configurations, identifying the
most optimal solutions without manual intervention.

– Performance Optimization: The tool was instrumental in optimizing

power consumption while maintaining performance levels suitable for
high-speed mobile data transfer.

• Achievements:

– Improved Power Efficiency: Achieved a 30% reduction in power con-

sumption compared to previous chip iterations, significantly extending
battery life for mobile devices.

– Reduced Design Cycle Time: Design cycles were shortened by 25%,

enabling quicker time-to-market for the new chip series.

10
 – Enhanced Integration Capabilities: Allowed for more complex designs
with better integration of features like AI processing, resulting in improved
overall performance.

– Lower Development Costs: By reducing design time and power con-

sumption, Qualcomm saw a decrease in overall project costs, allowing for
reinvestment in future innovations.

Case Study Summary: The integration of Cadence Cerebrus into

Qualcomm’s design processes not only improved efficiency and reduced
costs but also positioned the company as a leader in next-generation mobile
technology.

3.1.5 Challenges and Solutions

Common Challenges

• Complexity of modern designs leading to potential errors.

• Time constraints affecting thorough exploration of design options.

Solutions by Cadence Cerebrus

Cadence Cerebrus addresses these challenges by reducing design complexity and

streamlining workflows.

Figure 3.4: Density Distribution: Base vs Cerebrus Optimization

11
3.1.6 Future Trends

Emerging Trends by 2030:

• Collaborative AI Platforms: Enhanced AI integration with collaborative tools

will enable efficient, real-time design teamwork.

• Advanced Predictive Analytics: Improved AI analytics will allow proactive

design adjustments, boosting performance accuracy.

• Sustainability: AI tools will prioritize energy-efficient, eco-friendly designs to

reduce environmental impact.

• Customization: AI will enable highly tailored solutions that meet specific

requirements without sacrificing performance.

• IoT Integration: Designs will incorporate IoT for adaptive environments and
optimized resource management.

3.2 Logic Synthesis Using Synopsys DSO.ai

3.2.1 What is Synopsys DSO.ai?

Synopsys DSO.ai is an advanced logic synthesis tool that leverages artificial intelli-
gence to automate and optimize the design process. It provides:

• AI-Enhanced Logic Optimization: Utilizes machine learning algorithms to

enhance logic synthesis efficiency.

• Automated Design Closure: Streamlines the path from RTL (Register Transfer
Level) to GDSII (Graphic Data System II) with minimal manual intervention.

12
 Figure 3.5: Synopsys DSO.ai

3.2.2 Transforming Logic Synthesis

DSO.ai transforms traditional logic synthesis by integrating AI at various stages,

leading to improved performance and reduced time to market.

3.2.3 Key Features of Synopsys DSO.ai

The tool provides numerous benefits to the design process:

1. Rapid Iteration: Supports multiple design iterations with reduced turnaround

times.

2. Power and Area Optimization: Achieves balance between performance, power

consumption, and chip area.

3. AI-Driven Insights: Provides actionable insights based on previous design data.

3.2.4 Case Study: AMD

AMD implemented Synopsys DSO.ai in the development of its latest processor

architecture. Specific details include:

• Usage:

– Automated Synthesis and Optimization: Employed the tool for automat-

ing the synthesis of complex logic designs, enabling the design team to
focus on higher-level tasks.

13
 – Design Closure: Utilized DSO.ai to achieve design closure faster, allowing
more iterations within tight project timelines.

• Achievements:

– Performance Gains: Improved clock speed by 15% compared to the

previous generation, significantly enhancing processing power.

– Time Savings: Reduced synthesis time by 30%, allowing for quicker

design iterations and ultimately a faster product launch.

– Cost Efficiency: Overall project costs decreased due to fewer resources

being needed for manual synthesis tasks.

3.2.5 Challenges and Solutions

Common Challenges

• Increasing complexity of designs leading to longer synthesis times.

• Difficulty in achieving optimal power-performance-area (PPA) metrics.

Solutions by Synopsys DSO.ai

DSO.ai tackles these challenges by providing robust optimization algorithms that

significantly reduce design complexity and improve synthesis efficiency.

3.3 PCB Design Using Cadence Allegro X

3.3.1 Overview of Allegro X Design Platform

Cadence Allegro X Design Platform is an advanced PCB design tool that supports the
complete PCB development lifecycle, integrating AI and automation to enhance design
precision and reduce time-to-market.

14
 Key features include:

• Collaborative Multi-Board Design: Allows for simultaneous design across

multiple boards, improving coordination and reducing design errors.

• Real-Time Signal and Power Integrity Analysis: Provides instant feedback on

signal quality and power distribution, ensuring robust design performance.

Figure 3.6: Allegro X

3.3.2 Streamlining the PCB Workflow with AI

Allegro X leverages AI-driven layout and routing tools to streamline the PCB design
process. The AI optimizations improve placement accuracy and reduce turnaround
times, allowing designers to focus on complex tasks.

• Automated Layout Adjustments: Reduces manual interventions by automati-

cally optimizing component placement and routing.

• In-Design DRC and DFM Checks: Ensures that design rule checks (DRC)
and design for manufacturability (DFM) requirements are met during the design
process.

15
 Figure 3.7: AI-Driven Layout and Routing in Allegro X

3.3.3 Real-Time Analysis and Design Integrity

The platform’s in-design analysis features provide real-time feedback on design

integrity, including signal and power integrity checks. This ensures that potential issues
are identified and resolved early in the design cycle.

• Power Integrity Analysis: Identifies areas of potential power loss, helping

designers optimize power distribution networks.

• Signal Integrity Checks: Ensures signal stability across the PCB, reducing
electromagnetic interference (EMI).

3.4 Physical Design Using Cadence Innovus

3.4.1 What is Cadence Innovus?

Cadence Innovus is a leading physical design tool that enables designers to create
complex integrated circuits (ICs) efficiently. Key features include:

• Advanced Place and Route Algorithms: These algorithms optimize the layout
of designs for better performance and area utilization.

• Signoff Capabilities: Provides accurate estimations to ensure that the design

meets the required specifications before manufacturing.

16
 Figure 3.8: Cadence Innovus Interface

3.4.2 Transforming Physical Design

Cadence Innovus transforms physical design by providing integrated solutions that

enhance design closure, optimize power, and improve performance.

3.4.3 Key Features of Cadence Innovus

The tool is designed to streamline the physical design process:

1. Dynamic Power Optimization: Innovus allows for real-time adjustments to

reduce power consumption.

2. Physical Signoff Accuracy: Ensures that designs comply with manufacturing

requirements, reducing the risk of errors.

3. Scalability: Suitable for designs ranging from small chips to complex multi-
billion transistor systems.

3.4.4 Case Study: Apple

Apple used Cadence Innovus for the physical design of its A14 Bionic chip, which
powers the iPhone 12 series. The specific applications included:

17
 • Usage:

– Place and Route Optimization: Employed Innovus to optimize the layout

of the A14 Bionic chip, enhancing its performance and efficiency.

– Thermal Management: Utilized the tool to manage thermal distribution

across the chip, crucial for maintaining optimal performance during inten-
sive tasks.

• Achievements:

– Performance Improvement: Achieved a 30% increase in processing

speed compared to the A13 chip, making the device more responsive.

– Power Efficiency: Reduced power consumption by 20%, extending battery

life during high-performance applications.

– Design Accuracy: Improved manufacturing yield by 15% due to better

physical design accuracy.

Case Study Summary: The successful implementation of Cadence Innovus

in the A14 Bionic chip’s physical design not only optimized its performance
but also reinforced Apple’s position as a leader in semiconductor technology.

3.4.5 Challenges and Solutions

Common Challenges

• Increasing complexity of chip designs leading to longer design cycles.

• Ensuring compliance with stringent manufacturing requirements.

Solutions by Cadence Innovus

Cadence Innovus addresses these challenges with:

• Automated DRC and LVS Checks: Ensures that designs meet design rule
checks (DRC) and layout versus schematic (LVS) requirements automatically.

• Optimized Placement Strategies: Reduces congestion and enhances signal

integrity, crucial for high-frequency designs.

18
 Figure 3.9: Efficiency Gains with Cadence Innovus

3.5 Verification Using Verisium AI

3.5.1 What is Verisium AI?

Verisium AI is an advanced verification tool that leverages artificial intelligence

to enhance the verification process of complex semiconductor designs. Its key
functionalities include:

• Automated Bug Detection: Identifies potential issues in designs early in the

verification process.

• Formal Verification Techniques: Ensures that the design meets specified

properties without exhaustive simulation.

Figure 3.10: Verisium platform

19
3.5.2 Transforming Verification Processes

Verisium AI transforms traditional verification methodologies by integrating AI and

machine learning techniques, allowing for faster, more accurate validation of designs.

3.5.3 Key Features of Verisium AI

The tool is designed to optimize the verification workflow:

1. Intelligent Test Generation: Automatically generates test cases based on

design specifications.

2. Machine Learning Integration: Utilizes historical data to improve the effi-

ciency of the verification process.

3. Rapid Convergence: Reduces the time needed to achieve design closure by

focusing on critical paths.

3.5.4 Case Study: Qualcomm

Qualcomm implemented Verisium AI in the verification of its Snapdragon 888

processor, specifically for its integration into the following devices:

• Devices: The Snapdragon 888 was used in flagship smartphones, including:

– Samsung Galaxy S21

– Xiaomi Mi 11

• Usage:

– Bug Detection: Used Verisium AI to identify potential bugs in the

processor design prior to production, significantly reducing the risk of
failure in the field.

– Formal Verification: Ensured compliance with the required specifications

for high-performance mobile computing applications.

• Achievements:

20
 – Reduced Verification Time: Cut down verification time by approximately
40%, accelerating the product development cycle.

– Enhanced Reliability: Improved the reliability of the Snapdragon 888 by

minimizing post-production defects.

– Increased Market Readiness: Enabled faster time-to-market for devices

featuring the Snapdragon 888, enhancing Qualcomm’s competitive edge.

Case Study Summary: The application of Verisium AI in verifying the

Snapdragon 888 processor allowed Qualcomm to enhance design reliability
while achieving faster development times, critical in the competitive
smartphone market.

3.5.5 Challenges and Solutions

Common Challenges

• Increasing complexity of chip designs leading to longer verification cycles.

• Ensuring comprehensive coverage of design specifications during verification.

Solutions by Verisium AI

Verisium AI addresses these challenges with:

• Automated Coverage Analysis: Ensures that all critical areas of the design are
thoroughly tested and verified.

• Adaptive Learning Algorithms: Learn from previous verification runs to

improve future efficiency and accuracy.

3.6 Manufacturing Using Synopsys Yield Explorer

3.6.1 What is Synopsys Yield Explorer?

Synopsys Yield Explorer is a comprehensive tool designed to enhance yield manage-

ment and optimization in semiconductor manufacturing. Its key features include:

21
 • Yield Analysis: Provides deep insights into yield data to identify areas for
improvement.

• Process Variation Management: Helps manage and mitigate the effects of

process variations on chip performance and yield.

Figure 3.11: Synopsys Yield Explorer Interface

3.6.2 Enhancing Manufacturing Efficiency

Synopsys Yield Explorer plays a vital role in semiconductor manufacturing by

facilitating better decision-making through data-driven insights.

22
Figure 3.12: Yield Explorer collects data from fab, test and EDA domains to enable
faster discovery of yield root-cause sources

3.6.3 Key Features of Synopsys Yield Explorer

The tool is designed to optimize the yield management process:

1. Data Visualization: Offers advanced visualization techniques for yield and

defect data, allowing engineers to quickly identify patterns.

2. Statistical Analysis: Utilizes statistical models to predict yield and assess the
impact of manufacturing changes.

3. Root Cause Analysis: Aids in identifying the root causes of yield loss and
proposing corrective actions.

3.6.4 Case Study: GlobalFoundries

GlobalFoundries utilized Synopsys Yield Explorer for optimizing the manufacturing

process of its 14nm FinFET technology, particularly for the following applications:

• Applications: Chips produced for high-performance computing and mobile

devices, including:

– AMD Ryzen Processors

– NVIDIA GPUs

23
 • Usage:

– Yield Optimization: Used Yield Explorer to analyze yield data from

various production batches, leading to targeted improvements in process
parameters.

– Defect Density Reduction: Leveraged statistical models to understand

defect densities in critical areas of the chip design, leading to significant
yield enhancements.

• Achievements:

– Increased Yield Rates: Achieved a yield rate improvement of approxi-

mately 25% for the 14nm process node.

– Cost Reduction: Reduced manufacturing costs by minimizing scrap and

rework through effective defect analysis.

– Faster Time-to-Market: Enabled quicker turnaround times for new chip

designs, giving clients a competitive edge in the market.

Case Study Summary: The application of Synopsys Yield Explorer

in GlobalFoundries’ manufacturing process significantly enhanced yield
rates and reduced costs, demonstrating its critical role in semiconductor
manufacturing.

3.6.5 Challenges and Solutions

Common Challenges

• Variability in manufacturing processes leading to inconsistent yield rates.

• Difficulty in analyzing large volumes of yield data effectively.

Solutions by Synopsys Yield Explorer

Synopsys Yield Explorer addresses these challenges with:

• Automated Data Processing: Streamlines the analysis of large datasets,

enabling engineers to focus on actionable insights.

24
• Predictive Analytics: Forecasts potential yield impacts of design changes,
allowing preemptive actions to improve overall performance.

(a) Traditional diagnostics methods typically require 2-3 weeks to reach root
cause—and with only about 50 percent accuracy

(b) With Yield Explorer, actual time to results, with 90percent accuracy, was
reduced to 2-3 days

25
Chapter 4

Conclusion

The adoption of AI tools in VLSI design is transforming the semiconductor industry,

making design stages faster and more efficient. From Cadence Cerebrus in archi-
tectural planning to Verisium AI in verification, AI-driven processes enhance both
innovation and performance.
Case studies highlight this shift: Qualcomm’s use of Cadence Cerebrus has set
new standards in design efficiency, while GlobalFoundries’ use of Synopsys Yield
Explorer underscores the importance of intelligent manufacturing for quality and
competitiveness.

Future Prospects
AI in VLSI design holds transformative potential:
- Automation: Tools like Synopsys DSO.ai reduce human error and speed up
timelines by autonomously managing design tasks.
- Adaptive Systems: AI-enabled adaptive chips optimize real-time performance,
such as power-efficient automotive chips.
- Custom Solutions: Specialized chips like Google’s TPUs illustrate AI’s ability to
meet specific needs effectively.
- Sustainable Design: AI-optimized energy-efficient processors support the indus-
try’s shift toward greener technology.

In summary, AI’s role in VLSI is revolutionary, reshaping chip design. By

embracing these tools, the industry is advancing efficiency, sustainability, and setting
the stage for a new era of innovation in semiconductor technology.

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References

[1] L. Wang and H. Liu, ”Reinforcement Learning for Logic Synthesis in VLSI
Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, 2024.

[2] Y. Chen, M. Zhang, and J. Lee, ”Cadence Cerebrus: AI-Driven Automation for
Architectural Design Optimization,” presented at CadenceLIVE 2024, 2024.

[3] R. Patel, S. Kumar, and P. Verma, ”AI-Assisted Verification with Verisium AI:
Enhancing Reliability and Time-to-Market,” Synopsys Journal of Semiconductor
Design Automation, 2023.

[4] Integrated Devices for Artificial Intelligence and VLSI, Wiley, 2024.

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