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Traffic-Controller 10281

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46 views

Traffic-Controller 10281

Uploaded by

aaryansingh2810
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1.

Implementation of sop & pos expression


Fr. Conceicao Rodrigues College of Engineering
Department of Electronics & Computer Science Engineering
Expt 8: Simulation of a Traffic Light Controller Using Verilog

Date of Submission: 4/11/2024 Roll No: 10281


1. Course, Subject & Experiment Details

Academic Year 2024 - 25 Estimated Time Experiment No. 8 – 02 Hours

Course & Semester S.E. (Computer) –


Sem. III Subject Name Verilog Programming

Experiment Type Software & Hardware


Performance Subject Code OECE12

2. Aim & Objective of Experiment

This experiment focuses on designing and simulating a basic traffic light controller using
Verilog HDL. The controller manages the timing and sequencing of traffic light states—
Red, Green, and Yellow—to emulate a standard traffic light pattern.

3. Brief Theoretical Description

Traffic light controllers are sequential circuits often used as examples to illustrate finite state machine
(FSM) design. In this experiment, the controller will operate through three states (Red, Green,
and Yellow), each with a specific timing interval. This state transition process is managed via a
Verilog implementation, which will be verified through simulation on EDA Playground.

4. Tools Required
EDA playground online tool

5. Experimental Procedure

• Go to EDA Playground.
• Select the SystemVerilog or Verilog simulator (e.g., Icarus Verilog, ModelSim).
• Write the traffic_light_controller module and tb_traffic_light testbench in the
editor.
• Set up the clk and reset in the waveform configuration to observe state transitions
in real-time.
• Run the simulation and observe the output waveform to verify the traffic light
sequence.
6. OUTPUT
7. Conclusions
This experiment successfully implemented a traffic light controller using Verilog HDL,
demonstrating FSM design principles and sequential logic control. The setup on EDA Playground
verified the functionality, allowing observation of state transitions and timing through simulated
waveforms.
Post Lab Questions:
1. Differentiate between synchronous reset and asynchronous reset
2. Write a Verilog code to swap contents of two registers with and without a temporary
register?

Answer 1:

Aspect Synchronous Reset Asynchronous Reset

Clock Dependency Requires a clock edge to reset Independent of the clock

Reset Activation Takes effect only at the active Takes effect immediately when
clock edge asserted

Metastability Less prone to metastability issues Can cause metastability if de-


asserted asynchronously

Design Complexity Easier for synthesis tools to Can be prone to glitches due to
handle; cleaner design asynchronous behavior

Usage Common in designs with Used for immediate or power-on


consistent clock resets

Clock Requirement Requires clock to reset, so won’t Works even if clock is stopped
work if clock is off

Answer 2:

module swap_without_temp (

input [7:0] a_in, // 8-bit input for register a

input [7:0] b_in, // 8-bit input for register b

output reg [7:0] a_out, // 8-bit output for register a

output reg [7:0] b_out // 8-bit output for register b

);

always @(*) begin

a_out = a_in ^ b_in; // a_out temporarily holds a XOR b

b_out = a_in ^ a_out; // b_out gets original value of a

a_out = a_out ^ b_out; // a_out gets original value of b

end

endmodule

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