Microprocessors & Interfacing - CS 402

1 . 3 . 6 . 9 . 1 1 . 1 3 . 1 5 . 1 8 . 2 0 . 2 2 . 2 5 . 2 8 . 3 1 . 3 4 . The total number of interrupts that can be supported by 8086 are a) 128 b) 256 c) 1024 d) 64 A computer mega is equal to ---kilobytes a) 1000 b) 10 c) 100 d) 10000 MIPS stand for a) mega instructions per second b) million instructions per second c) mega information per second d) million information per second To address one out of N memory locations, the minimum number of address bits required is a)log2 N b) N c) 2N d) 2N If the starting address of 8K*8 EPROM is F0000H, what is the last address a) F1FFFH b) FFFFFH c) F0FFFH d) F1111H The individual bits of port c can be used for data & control signal in --- of 82C55 a) mode 0 b) mode 1 c) mode 1 & d) mode 0, mode 1 & mode 2 mode 2 DAA and DAS instructions are also called as, a) packed BCD arithmetic instructions b) unpacked BCD arithmetic instructions c) unpacked BCD logical instructions d) both a and b Which OCW of 8259 is used to set / reset mask a) OCW1 b) OCW2 c) OCW3 d) OCW4

In which ICWs of 8259 the type n of Interrupt Vector is stored a) ICW1 & ICW2 b) ICW2 & c) ICW3 & d) ICW1 & ICW4 ICW3 ICW4 The angle by which stepper motor rotates depends on a) number of rotor teeth b) width of rotor teeth c) number of coils d) none 82C55 is a) parallel input-output port chip c) Programmable Timer b) Programmable interrupt Controller d) none

Time required to run a ALP depends on a) clock frequency b) sum of clock cycles for each instruction in the program c) both a) & b) d) none Can the register CS be loaded with a value using an instruction a) Yes b) No c) Depends on the situation d) none CS contents can be changed by a) long jump instruction c) both a) & b) b) short jump instruction d) MOV instruction

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Which of the following string instruction does not need ES segment a) LODSB b) STOSB c) MOVSB d) None The main input to the linker is a) .OBJ file b) .COM file

c) .EXE file

d) .ASM file

The far jump instruction modifies program address by changing the register or registers a) CS b) IP c) CS & IP d) CS or IP

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The instruction that tests the TEST pin of 88086 is a) WAIT b) INT3 c) MOV The return instruction in Interrupt Service Procedure is a) RET b) IRET c) MRET

d) none

d) a) or b)

Single stepping is accomplished by setting which flag in flag register a) TF b) DF c) IF d) None In 8086, the first ______ interrupt vector locations are reserved for Intel use a) 32 b) 24 c) 12 d) 64 Where is a slave INTR pin, connected to the master 8259A in a cascaded system a) IR0:IR7 b) INT c) A0 d) CAS0 Where is the Interrupt Vector of INT 0AH stored in the Interrupt Vector Table a) 28H b) 24H c) 32H d) 0AH 8086 is able to address a) 2Mbyte b) 1Kbyte

c) 1M*8 bits

d) 1Gbyte

Reason to multiplex address & data lines is a) to reduce number of pins on chip b) to reduce the cost of chip c) both a) & b) d) none Carriage return code a) returns print head or cursor to the left margin of current line b) moves the cursor or print head

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c) moves print head or cursor to end d) returns print head or cursor to the left margin of next line of line Which of the following is an Assembler Directive a) SHORT b) SEG c) PTR d) all The Interrupt Vector address of NMI is a) 0000:0008H b) 0000:0000H c) 0000:0010H PUSH instruction a) increments SP by 2 c) increments SP by 1 Which is the Type-0 interrupt a) NMI b) divide by zero

d) 0000:000CH

b) decrements SP by 2 d) decrements SP by 1 c) TRAP d) INT3

Few methods to pass parameters to procedure a) using Registers b) using PUBLIC & EXTERN c) using stack d) all What is the numeric range of eight bit unsigned binary number? a) 0..7 b) 1..8 c) 0..255 d) 1..256 What is the result of adding the following two positive binary bit strings? 101101.101 and 10100.0010 a) 1000001.1110 b) 1000001.1010 c) 1000001.1000 d) 1000001.1100 During what CPU cycle is an instruction moved from primary storage to the control unit? a) fetch b) execution c) access d) refresh Which of the following is a microchip that contains all of the circuits and connections that implement a CPU? a) b) Transistor c) Semiconductor d) Heat sink Microprocessor

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The contents of different registers are given below. Form Effective addresses for the instruction MOV AX, 5000H [BX] [SI] . [AX] =1000H, [BX] = 2000H, [SI] = 3000H, [DI] = 4000H, [BP] =5000H, [SP] = 6000H, [CS] = 0000H, [DS] = 1000H, [SS] = 2000H, [IP] = 7000H. a) 20000H b) 1A000H c) 1A00H d) 2A000H

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IDIV and DIV instructions perform the same operations for? a) Unsigned number b) Signed number c) Signed number & Unsigned d) none of above number respectively

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What is the output of the following code? AL=88 , CL=49 ADD AL, CL DAA a) D7, CF=1 b) 37, CF=1 c) 37, CF=0 What is the output of the following code? AL= 49 BCD, BH= 72 BCD SUB AL, BH DAS a) AL=D7, CF=1 b) AL=7D, c) AL=77, CF=1 CF=1 What is the output of the following code? MOV AL, 36H MOV BL, 34H ADD AL, BL AAA

d) 7D, CF=1

d) none

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1 0 1 . 1 0 3 . 1 0 5 . 1 0 7 .

a) AX= 0100H b) AX=0000H c) AX=006AH d) AX=016A H What is the output of the following code? MOV AL,19H AAM a) AX = 0205 H b) AX = 0019 H c) AX = 0025 H d) AX = 0109 H What is the output of the following code? CLC MOV BH,179 RCL BH, 1 a) CF=0, OF= 1, BH= 01100101 b) CF=1, OF=1, BH=01100110 c) CF=1, OF =0, BH= 01001101 d) CF=0, OF=0, BH=00101100 In 8086 microprocessor one of the following ASCII arithmetic instruction is executed before an arithmetic operation. a) AAM b) AAD c) DAS d) DAA 8086 Segmentation unit allows segments of _____ size at maximum a) 4Gbytes b) 6Mbytes b) 6Mbytes d) 64Kbytes

Access time is faster for a) ROM b) SRAM

c) DRAM

___ bit in ICW1 indicates whether the 8259A is in cascaded mode or not? a) LTIM=0 b)ADI c) SNGL d)IC4

1 0

8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the maximum number of interrupts available to the 8086 microprocessor is

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a) 8 b)16 c)15 Which interrupt has the highest priority? a) INTR b) TRAP c) INT n

d) 64 d) NMI

Which of the following is hardware interrupts? a) NMI b) INTR c) both a) & b)

d)none

Which processor structure is pipelined? a) all x80 b) all x85 c) all x86 processors processors processors

d)none of the above

The advantage of memory mapped I/O over I/O mapped I/O is, a) Faster b) Many instructions support memory mapped I/O c) Require a bigger address decoder d) All the above BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA s 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode An example for 32b processor is a)8086 b)80486

c) Motorola 68000

d)28000

Which of the following pair of statements is true? a)Address bus Unidirectional & b)address bus unidirectional & data bus unidirectional data bus bidirectional c)address bus bidirectional & d)address bus bidirectional & data bus unidirectional data bus bidirectional Can ROM be used as stack? a)yes b)no c) May be d)none

The total number of pins on 8086 is a)40 b)42

c)60

d)44

What is the power supply requirement of 8086?

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a)5V b)7V What is the reset address of 8086? a)FFFF0 H b)FFFFF H

c)10V c)00000 H

d)12V d)0FFFF H

Which is faster- Reading word size data whose starting address is at even or at odd address of memory in 8086? a)even b)odd c) both d) none ASCII code for digit zero is a)30 H b) 48

c) 00

d) both a) & b)

What is maximum size of the instruction in 8086? a)2 bytes b)4 bytes c)6 bytes

d)10 bytes

In string operations, which is the default segment in which source string is stored ? a)CS b)ES c) DS d)DS or ES

In string operations which is the default segment in which destination string is stored? a)CS b)ES c)DS d)DS or ES

The instruction which rotates the contents of the destination operand left by the specified count through the carry flag is a)RCL b) RCR c) ROL d) ROR The command which is executed, when the overflow flag OF is set is a)JMP b)INT0 c)CALL d)LOOP

Which unit of 8086 contains the circuit for physical address calculations ? a) BIU b) EU c) both a &b d) none

The size of prefetch queue in 8086 is a) 4 bytes long b) 5 bytes long c) 6 bytes long d) 8 bytes long The size of prefetch queue in 8088 is a)4 bytes long b) 5 bytes long c) 5 bytes long d) 8 bytes long

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The 8088 processor has how many bit data bus? a) 16-bit b) 32-bit c) 8-bit d) none

This signal indicates the availability of valid data over the address/data lines a) DT/R b) DEN c) M/IO d) none

In 8086 the byte data of even address is transferred on a) D7-D0 b) D15-D8 c) D0-D6

d) all of the above

Which pin is strapped to ground in the maximum mode of 8086? a) MN/MX b) RESET c) DEN d) none

The size of the 8088 address bus is a) 10 address bits b) 20 address bits

c) 32 address bits

d) 16 address bits

Which new pin was introduced in 8088 instead of BHE pin in 8086? a) M/IO b) SS0 c) ALE d) DT/R Which pin provides the status information in the minimum mode of 8088? a) ALE b) SS0 c) DEN d) none

This is an edge triggered input which causes type 2 interrupt a) INTA b) ALE c) NMI d) none The instruction to which REPE prefix is provided is executed repeatedly till a) CX is not zero b) equal condition is not satisfied c) equal condition is satisfied d) both a) & b) The CPU 8088 is able to address _____ bytes of physical memory a) 1Kbytes b) 1Gbytes c) 1Mbytes d) none

This flag is set to 1 if the lower byte of the result contains even number of ones a) trap b) interrupt c) parity d) zero

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In case of INC instruction , which of the following condition code flag is not affected a) ZF b) CF c) OF d) PF

ISR means a) international service routine c) interrupt service routine

b) instruction service routine d) interest service request

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The _______ is incremented to point to the next instruction in code segment a) BP b) DP c) SP d) IP _______ is an internal interrupt a) TRAP b) NMI

c) INTR

d) none

The __________ pin should remain high for at least two clock cycles for it to be recognised. a) ISR b) NMI c) none d) INTR

ALE stands for a) Address latch enable c) arithmetic latch enable

b) arithmetic latch enable d) address logic enable

The register which is only allowed to carry port address is, a) DX b) AX c) SI d) both a and b

The instruction used for table look up is a) XLAT b) LAHF c) XCHG

d) LEA

BHE stands for a) Bus high enable

b) byte high enable

c)Bus high extend

d) none

The indicator V-bit of opcode is used in case of a) loop instruction b) shift and rotate instruction c) both a and b d) jump instruction The instruction to convert from binary to BCD

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a) DAA b) AAM c) AAD d) DAS In the control transfer instructions, if the destination location lies in the same segment is called as, a) Intra segment b) Inter segment b) Immediate mode d) none mode mode In the register addressing mode, all registers are used except a) BX b) AX c) IP d)SP

then the mode

In case of jump instruction, if the signed displacement (d) is of 8 bits (i.e., -128<d<+127) then it is a, a) long jump b) medium jump c)short jump d) both a and c In MOV instruction, in case of immediate addressing mode, destination register should not be a, a) segment register b) general purpose register c) pointer d) index

The size of interrupt vector in 8086 is a) 4 words b) 4 bytes

c)6 bytes

d) 6 words c

The number of memory banks in 8086 is a) 1 b) 3 c)2

d) 4

The number of interrupt inputs to 8259 is a) 4 b) 16 c)8

d) 1

In the 8086 real mode, find the starting & ending address of the segment located by the segment register value1000H

a) 10000H & 1FFFF H

b) 1000H & FFFF H

c)00000H & FFFFF H

d) 10000 H & 11111H