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Lecture Notes on
Microprocessor and Microcontroller
(UNIT-IV)
Branch: CSDA Sem-3RD

1. Introduction to 8051 Microcontroller

Microcontroller is a single chip microcomputer which consists of CPU, Memory, I/O ports,
timers and other peripherals. The difference between microprocessor and microcontroller is
microprocessor is a single integrated CPU whereas microcontroller is single chip microcomputer.
The world leaders of manufacturing of microprocessor and microcontroller are Intel, Motorola,
IBM, Cyrix etc. Here we have to focus on microcontroller 8051.

In 1981 Intel Corporation introduced an 8 bit microcontroller called 8051.this

microcontroller had 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial port and
four ports (each 8bit wide) all on a single chip. It is an 8 bit processor means it can process8 bit
of data at a time. It has total of four I/O ports, each 8 bit wide.

Features of 8051

Feature Quantity

ROM 4K bytes
RAM 128bytes
Timer 2
I/O pins 32
Serial Port 1
Interrupt sources 6

Pin diagram of 8051

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Pin out Description:

Pins 1-8: Port 1 Each of these pins can be
configured as an input or an output.
Pin 9: RST A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller. By applying
logic zero to this pin, the program starts execution from the beginning.
Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions:
Pin10: RXD Serial asynchronous communication input or Serial synchronous communication
output.
Pin11: TXD Serial asynchronous communication output or Serial synchronous
communication clock output.
Pin 12: INT0 Interrupt 0 inputs.
Pin 13: INT1 Interrupt 1 input.
Pin 14: T0 Counter 0 clock input.
Pin 15: T1 Counter 1 clock input.
Pin 16: WR Write to external (additional) RAM.
Pin 17: RD Read from external RAM.
Pin 18, 19: XTAL2/XTALI is for oscillator input
Pin 20: GND-Ground.
Pin 21-28: Port 2- If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address byte,
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i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is
not used, which means that not all eight port bits are used for its addressing, the rest of them
are not available as inputs/outputs.
Pin 29: PSEN’- Program Store Enable. If external ROM is used for storing program, then a
logic zero(0) appears on it every time the microcontroller reads a byte from memory.
Pin 30: ALE – Address latch enable
1 – Address on AD 0 to AD 7
0 – Data on AD 0 to AD 7
Pin 31: EA’ – it indicates the presence of external memory
Pin 32-39: Port 0 Similar to P2.
Pin 40: VCC → +5V power supply.

2. Architecture of 8051
Fig 4.1 shows a simplified architecture for the internal Hardware. Fig 4.2 shows an overview of
the internal hardware architecture of the 8051/8031 microcontrollers.

The CPU has the controlled and sequencing logic circuits with signals as in a microprocessor.The
MCU has, besides the CPU, ROM, Interrupt control circuit, internal timing devices (timersT0, T1),
serial interface (SI), RAM and special function registers (SFRs). It has four ports P0, P1, P2 and P3
as shown in Fig. 4.1. The overview block diagram of 8051 is depicted in Fig.4.2.

Fig. 4.1 Simplified architecture of 8051

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Description of Sub units in the hardware architecture and meaning of the symbols

PC- Program Counter

A 16 bit register to hold the program memory address of the instruction being currently fetched.
Increments continuously to point to the next instruction, unless there is change in the program flow
path.

DPTR- Data Pointer register

A 16-bit register to hold the external data memory address of the data being currently fetched or
to be fetched.
A-Accumulator
An 8-bit register to save an operand for an ALU or data transfer operation and is also used to
accumulate result after an ALU operation.
B- B register
An 8-bit register to save a second operand for the ALU and also accumulate the result after ALU
operation for multiplication or division.
ALU- Arithmetic logic unit
A unit to perform an arithmetic and logical operation at an instance as per the instruction to be
executed and give result.
PSW- Processor Status Word
A register to save the bits of different flags.
P0- Port P0
An 8-bit port for the I/Os in a single chip mode and for the data bus-cum- lower order address in
the expanded mode.
P2- Port2
An 8-bit port for the I/Os in a single chip mode and for the higher order address in the expanded
mode
P1- Port1
An 8-bit port for the I/Os in a single chip mode and a few device operations related bits in certain
8051 family variants in the expanded mode.
P3- Port3
An 8-bit port for the I/Os in a single chip mode and the serial interface (SI) bits , timer T0 and T1
inputs, Interrupts INT0 and INT1 inputs , RD and WR for the memory read-write in the expanded
mode.
SI- Serial Interface Device
Serial device for full duplex UART serial I/O operations through the set of two pins of P3, RxD
and TxD and for the half duplex synchronous communication of the bits through the same set of
pins, DATA and CLOCK.
T0 and T1- Timers T0 and T1
Timing devices in 8051 family using four registers TH1, TH0, TL1, and TL0.
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SFRs- Special Function Registers

All registers the SP, PSW, A, B, IE, IP, SCON, TCON, SMOD, SBUF, PCON, , TL0, TH0,
TL1, TH1 are called SFRs
ROM- Read only Program memory
Masked ROM EPROM or flash EEPROM of 4kB in 8051 classic family.
Internal RAM- Internal Random Access Memory
For read and write the 128 B memory is indirectly and directly addressable in address space.
Register banks- Four set of registers
Four register banks each of 8 registers and these are also part of the internal RAM.
XTAL1 and XTAL2 – Pins to the Crystal
Pins to the crystal in the oscillator circuit, usually 12 MHz
EA - External Enable
To enable use of external memory addresses to external ROM.
RST- Reset Pin
Reset circuit input and also reset few output cycles to the external peripheral devices to let
processor reset and synchronize with devices.
INT 0 and INT 1- Interrupt pins
Active low two external interrupts.
VCC and GND- Voltage supply pi and ground pin
For 5 V supply and ground connections respectively.
PSEN - Program Store Enable
Active low when reading the external program memory bytes
RD -Read
Active low when reading the byte from external data memory.
WR - Write
Active low when writing the byte to external data memory

3. Memory Organization
The 8051 micro controller has a total of 128 bytes of RAM. The 128 bytes of RAM inside the
8051 are assigned addresses 00H to 7FH and divided into three different groups as follows.

1. A total of 32 bytes from location s 00H to 1FH are set aside for register banks and the stacks.
2. A total of 16 bytes from locations 20H to 2FH are set aside for bit addressable read/write
memory.
3. A total of 80 bytes from locations 30H to 7FH are used for read and write storage, or what is
normally called a scratch pad. These 80 locations of RAM are widely used for the purpose of
storing data and parameters by 8051 programmers.

Register banks in the 8051

As mentioned, a total of 32 bytes of RAM are set aside for the register banks. These 32 bytes
are divided into 4 banks of registers in which each bank has 8 registers, R0-R7. RAM locations
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from 0 to 7 are set aside for bank 0 of R0-R7 where R0 is RAM location 0 , R2 is location 2 and
so on. The second bank of registers R0-R7 start RAM location 08 and goes to location 1FH. The
third bank of R0-R7 starts at memory location 10 H and goes to location 17H. finally RAM
location 18H to 1FH are set aside for the fourth bank of R0-R7. The following shows how 32
bytes are allocated into 4 banks.

Fig. 4.7 RAM Allocation in the 8051

Fig. 4.6 RAM allocation in the 8051

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External Program Memory

Fig.4.8 shows a layout of the external code memory addresses in the classic 8051 architecture.

1. When the the EA =0 at RESET, the PC (MCU program counter ) starts from 0x0000 and
accesses the external addresses from the memory. Memory addresses are between 0x0000
and 0xFFFF.
2. When the EA =1 at RESET, the PC starts from 0x0000 for banks0 and 1 and accesses the
internal addresses and the 0x1000 onwards from the external addresses from the memory.

Fig. 4.8 Code Memory (Program memory)

External Data Memory

Fig. 4.9 shows a layout of the external data (X-DATA) memory addresses in the classic 8051
architecture. It can be accessed through the indirect addressing mode used.

Fig. 4.9 Memory for X-Data in classic 8051

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5. Special Function Registers (SFR)

For a programmer, the SFRs are at the directly addressable space special registers. These can
be accessed by their names or by their addresses. The SFRs have addresses between 80H and FFH.
These addresses are above 80H, since the addresses 00 to 7FH are addresses of RAM memory
inside the 8051.Not all the address space of 80 to FF is used by the SFR. The unused locations
80H to FFH are reserved and must not be used by the 8051 programmer. The meaning of each
symbol is enlisted in Table 4.1.

Table 4.1 Special Function Register (SFR) Address.

Symbol Name Address
ACC* Accumulator 0E0H
B* B-register 0F0H
PSW* Program Status Word 0D0H
SP Stack Pointer 81H
DPTR Data Pointer 2 bytes
DPL lower byte 82H
DPH higher byte 83H
P0* Port0 80H
P1* Port1 90H
P2* Port2 0A0H
P3* Port3 0B0H
IP* Interrupt Priority Control 0B8H
IE* Interrupt Enable Control 0A8H
TMOD Timer /counter mode control 89H
TCON* Timer/counter control 88H
T2CON* Timer/counter 2 control 0C8H
T2MOD Timer /counter mode control 0C9H
TH0 Timer/counter0 high byte 8CH
TL0 Timer/counter0 low byte 8AH
TH1 Timer/counter 1 high byte 8DH
TL1 Timer/counter 1 low byte 8BH
TH2 Timer/counter 2 high byte 0CDH
TL2 Timer/counter 2 low byte 0CCH
RCAP2H T/C2 capture register high 0CBH
byte
RCAP2L T/C2 capture register high 0CAH
byte
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON8 Power control 87H
* indicate Bit addressable
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6. Port Operation
The four ports P0, P1, P2 and P3 each use 8 pins, making them 8-bit ports. All the ports upon
RESET are configured as output, ready to be used as output ports. To use any of these ports as
an input port , it must be programmed.

Port 0

It can be used for input or output. It occupies total of 8 pins (pins 32-39). To use the pins of port
0 as both input and out ports, each pin must be connected externally to a 10 K ohm pull-up resistor.
P0 is an open drain unlike P1, P2 and P3. With external pull-up resistors connected uponreset,
port0 is configured as an output port.

Fig. 4.11 Port 0 with pull up Resistors

With resistors connected to port 0 , in order to make it as input the port must be programmed by
writing 1 to all the bits. In the following code.

MOV A, #0FFH

MOV P0, A

BACK: MOVA, P0

MOV P1, A

SJMP BACK.

Port 1

Port 1 occupies a total of 8 pins (pins 1 through 8) . It can be used as input or output. In contrastto
Port 0 , this port does not need any pull-up resistors since it already has pull-up resistors internally.
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Upon reset port 1 is configured as an output port. To make Port 1 an input port it must be
programmed as such by writing 1 to all its bits.

Port 2

Port 2 occupies a total of 8 pins ( pins 21 through 28). It can be used as input or output. Just like
P1, port 2 does not need any pull-up resistors since it already has pull-up resistors internally. Upon
reset, port 2 is configured as an output port. To make port 2 as input, it must programmed
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as such by writing 1 to all its bits. The dual role of port 2 is also accomplished by providing higher
byte address through A8-A15 to access the external memory.

Port 3

Port 3 occupies a total of 8 pins, pin 10 through 17. It can be used as input or output. P3 does not
need any pull-up resistors , the same as P1 and P2. Although Port 3 is configured as an output port
upon reset, Port 3 has additional function of providing some extremely important signals such as
interrupts. Table depicts the alternate functions of port 2

Table 4.2 Port 3 alternate functions

P3 bit Functions Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17

P3.0 and P3.1 are used for the RxD and TxD serial communication signals. P3.2 and P3.3 are used
for external interrupts. Bits P3.4 and P3.5 are used for timers 0 and 1. Bits P3.6 and P3.7
are used to provide WR and RD signals for external memories in 8051 based system.

6.3 Interfacing with External ROM/RAM as Program and Data Memory

For interfacing to external ROM some pins have important role that to be discussed here.

EA -When this pin is connected to Vcc, that indicates the program code is stored in the
microcontroller on-chip ROM. For external ROM access this pin is grounded.

P0 and P2 role in providing addresses- In 8051 P0 and P2 provides the 16-bit address to access
external memory. Of these ports P0 provides the lower 8 bit addresses A0-A7, and P2 provides the
upper 8 bit addresses A8-A15. More importantly, P0 is also used to provide 8 bit- data bus D0-D7.
In other words P0.0- P0.7 are used for both address and Data is called as address/data multiplexing.
The sharing of this bus is accomplished by ALE (address latch enable.) Pin.
When ALE=0, the 8051 uses P0 for the data path and when ALE=1, it is used for address path.

PSEN (program store enable)- It is an output signal must be connected to OE pin of a ROM
containing the program code. When EA pin is connected to ground the 8051 fetches opcode
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from external ROM by using PSEN .

7. Programmer’s Model
The CPU registers are used to store the data temporarily. The information may be data to
be processed or address pointing the data to be fetched. The majority of registers are 8 bits. The 8-
bit registers are shown in the diagram from MSB (most significant bit) D7 to the LSB (least
significant bit) D0. The most widely used registers of 8051 are A (accumulator), B, R0, R1, R2,
R3, R4, R5, R6, R7, DPTR (data pointer), and PC (program counter). All these registers are 8 bits
except DPTR and the program counter. The accumulator is used to hold one operand before
execution and hold the result after execution. The program counter points to the address of next
instruction to be fetched. It is a auto increment register. As the size of program counter is 16 bit.
8051 can access the program addresses from 0000H-FFFFH. When 8051 is powered-up the
program counter contents will be 0000H. This means that it expects the first opcode to be stored
at ROM address 0000H. For this reason in the 8051 system, the first opcode must be burned
memory location 0000H of program ROM since this is where it looks for the first instruction when
it is booted.

Fig. 4.22 Programmer’s model Fig. 4.23 PSW register

PSW (program status word register)

The program status word register (PSW) is an 8-bit register. It is also referred as Flag register.
Although this register is size of 8-bits, only 6bits are used by 8051. Two unused bits are user
definable flags. Other 4 bits are called as conditional flags such as CY (carry), AC (auxiliary
carry), P(parity) and OV(overflow).In this register the bits PSW.3 and PSW.4 are designated as
RS0 and RS1 and used to select the banks. PSW.5 and PSW.1 bits are general purpose status flags
and can be used by the programmer for any purpose.
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8. Operand addressing

An addressing mode is a method of specifying the data source or destination in an

instruction. There are 5 types of addressing modes is supported by 8051.

1. Register
2. Immediate
3. Direct (memory related)
4. Register Indirect (memory related)
5. Index register addressing

Register addressing mode

This addressing mode involves the use of registers to hold the data to be manipulated.

Examples:

MOV A, R0 ; Copy the contents of R0 int A

ADD A, R7 ; Add the contents of R7 to contents of A and the result is stored in A

Immediate addressing mode

In this addressing mode immediate data is specified in instruction as a source operand.

Examples:

MOV B, #40H ; load 40H into B register

MOV DPTR, #2000H ; load 2000H into DPTR

Direct addressing mode

As we know the on-chip RAM of 8051 is 128 byte, it can be accessed through memory address
from 00H to FF H. The allocations of 128 bytes are as follows.

1. RAM location 00H-1FH are assigned to register banks and stack

2. RAM location 20H-2FH is set aside as bit-addressable space to save single bit data.
3. RAM location 30H-7F is available as place to save bite-sized data.

Although the entire 128 bytes of RAM can be accessed through direct addressing mode, it is most
often used to access RAM location 30H-7FH. This is due to fact that register banks are accessed
through their names.
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Examples:

MOV R4, 70H ; move the contents of RAM location 70H to R4.

MOV 56H, A ; save the content of A in RAM location 56H

PUSH 05 ; push R5 onto the stack

Register indirect addressing mode

In this mode the address (of 8bits) is indirectly specified in the instruction by the contents of
pointer. This addressing mode so called because the source operand is from the address specified
indirectly by another register in the instruction. The limitation is that only R0 and R1 register can
be used in 8051 for indirect addressing. SFRs are directly accessible.

Examples

MOV R1, #55H ; load pointer R1=55H

MOV A, @R1 ; the content of pointer is transferred to A

Index registers addressing

Suppose we need to access external data RAM and external code space of on-chip ROM
16 bit address must be required. In this case we have to use DPTR. This mode is widely used in
accessing data elements of look-up table entries in the program ROM space of 8051.

Examples;

MOV DPTR, #0200H ; load DPTR with 0200

CLR A ; clear accumulator

MOVC A,@A+DPTR ; Move the content 0200 location into A