19-3174; Rev 0; 1/04

KIT
ATION
EVALU BL E
AVAILA
Low-Cost Linear-Regulator
LCD Panel Power Supplies
General Description Features

MAX8710/MAX8711/MAX8712
The MAX8710/MAX8711/MAX8712 offer complete lin- ♦ High-Performance Linear Regulator
ear-regulator power-supply solutions for thin-film tran- 1.6% Output Accuracy
sistor (TFT) liquid-crystal-display (LCD) panels used in Works with Small Ceramic Output Capacitors
LCD monitors and LCD TVs. All three devices include a Fast Transient Response
high-performance AVDD linear regulator, a positive Foldback Current Limit
charge-pump regulator, a negative charge-pump regu- ♦ 50mA Negative Regulated Charge Pump
lator, and built-in power-up sequence control. The
MAX8710 and MAX8711 also include a high-current ♦ 20mA Positive Regulated Charge Pump with
operational amplifier. Additionally, the MAX8710 pro- Adjustable Delay
vides logic-controlled high-voltage switches to control ♦ Built-In Power-Up Sequence
the positive charge-pump output. ♦ High-Current Operational Amplifier
The linear regulator directly steps down the input volt- (MAX8710/MAX8711)
age to generate the supply voltage for the source-driver ±150mA Output Short-Circuit Current
ICs (AVDD). The two built-in charge-pump regulators 12V/µs Slew Rate
are used to generate the TFT gate-on and gate-off sup- 12MHz, -3dB Bandwidth
plies. The high-current operational amplifier is typically Rail-to-Rail Inputs/Output
used to drive the LCD backplane (VCOM) and features ♦ Dual-Mode™ High-Voltage Switches (MAX8710)
high output current (150mA), fast slew rate (12V/µs),
and wide bandwidth (12MHz). Its Rail-to-Rail® inputs ♦ Thermal Protection
and output maximize flexibility. ♦ Latched Fault Protection with Timer
The MAX8710 is available in a 24-pin thin QFN package,
the MAX8711 is available in a 16-pin thin QFN package, Ordering Information
and the MAX8712 is available in a 12-pin thin QFN pack-
PART TEMP RANGE PIN-PACKAGE
age. All three packages are 4mm x 4mm with a maximum
thickness of 0.8mm for ultra-thin LCD panel design. They MAX8710ETG -40°C to +100°C 24 Thin QFN 4mm x 4mm
operate over the -40°C to +100°C temperature range. MAX8711ETE -40°C to +100°C 16 Thin QFN 4mm x 4mm
MAX8712ETC -40°C to +100°C 12 Thin QFN 4mm x 4mm
Applications
LCD Monitor Panel Modules
Minimum Operating Circuit
LCD TV Panel Modules
IN
Pin Configurations IN
GND INL
MODE
SRC

FBN

DLP

CTL
FBL

REF OUTL
REF AVDD
FBL
TOP VIEW
24

23

22
21

20
19

FBN
MAX8710
SUPCP SHDN
VIN
GON 1 18 SHDN
VGOFF DRVN DRVP
DRN 2 17 FBP DLP

REF 3 16 THR POSB VP

AVDD

POSB 4 MAX8710 15 SUPB SUPB

AVDD FBP

INL 5 14 OUTB
OUTB
VCOM
NEGB 6 13 GND NEGB
SRC

MODE
GON
VGON
10

11
12
7

DRN
CTL REF
CTL
IN

OUTL

SUPCP
DRVN

DRVP
N.C.

THR

THIN QFN 4mm x 4mm

Pin Configurations continued at end of data sheet.
Rail-to-Rail is a registered trademark of Motorola, Ltd. Dual Mode is a trademark of Maxim Integrated Products, Inc.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
ABSOLUTE MAXIMUM RATINGS
MAX8710/MAX8711/MAX8712

CTL, FBL, FBP, FBN, SHDN, REF, THR to GND ......-0.3V to +6V OUTB Maximum Continuous Output Current....................±75mA
MODE, DLP to GND ....................................-0.3V to VREF + 0.3V DRVP RMS Output Current .................................................90mA
IN, INL, OUTL (MAX8710) to GND .........................-0.3V to +28V DRVN RMS Output Current..............................................-150mA
SUPCP, SUPB , OUTL (MAX8711, MAX8712) Continuous Power Dissipation (TA = +70°C)
to GND................................................................-0.3V to +14V 24-, 16-, and 12-Pin Thin QFN 4mm x 4mm
POSB, OUTB, NEGB to GND ....................-0.3V to VSUPB + 0.3V (derate 16.9mW/°C above +70°C) .............................1349mW
DRVN, DRVP to GND ..............................-0.3V to VSUPCP + 0.3V Operating Temperature Range .........................-40°C to +100°C
SRC to GND ...........................................................-0.3V to +30V Junction Temperature ......................................................+150°C
GON, DRN to GND......................................-0.3V to VSRC + 0.3V Storage Temperature Range .............................-65°C to +160°C
DRN to GON............................................................-30V to +30V Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0°C to +85°C. Typical values are at TA =
+25°C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

IN Operating Supply Range 8 28 V
SHDN = GND 0.2 0.4
IN Quiescent Current mA
SHDN = 3.3V 2.5
Duration to Trigger Fault Condition 216 oscillator clock cycles 44 ms
REF Output Voltage -10µA < IREF < 1mA (excluding internal load) 4.9 5.0 5.1 V
SUPCP Input Supply Range 2.7 13.2 V
Charge-Pump Regulators Operating
1275 1500 1725 kHz
Frequency
Thermal Shutdown Rising temperature, 15°C hysteresis +160 °C
LINEAR REGULATOR
INL Operation Supply Range VOUTL < VINL 7 28 V
Dropout Voltage IOUTL = 50mA 150 300 mV
FBL Regulation Voltage IOUTL = 50mA 2.46 2.50 2.54 V
FBL Input Bias Current VFBL = 2.5V 50 nA
FBL Fault Trip Level Falling edge 1.92 2.00 2.08 V
VINL = VIN = 10.8V~13.2V, VOUTL = 10V,
15
FBL Line-Regulation Error IOUTL = 50mA mV
VINL = VIN = 10V~28V, VOUTL = 9V, IOUTL = 50mA 10
Bandwidth Guaranteed by design 1000 kHz
Maximum OUTL Current VFBL = 2.4V 300 mA
OUTL Soft-Start Period 212 oscillator clock cycles in a 7-bit DAC 3 ms
OUTL Load Regulation VIN = 12V, 5mA < IOUTL < 300mA 2 %
OPERATIONAL AMPLIFIER
SUPB Supply Operating Range 4.5 13.2 V
SUPB Supply Current Buffer configuration, VPOSB = 4V, no load 0.7 1.0 mA
Input Offset Voltage (VNEGB, VPOSB) = VSUPB / 2, TA = +25°C 0 12 mV
Input Bias Current (VNEGB, VPOSB) = VSUPB / 2 -50 +1 +50 nA

2 _______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
ELECTRICAL CHARACTERISTICS (continued)

MAX8710/MAX8711/MAX8712
(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0°C to +85°C. Typical values are at TA =
+25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Common-Mode Input Range VNEGB, VPOSB 0 VSUPB V
Common-Mode Rejection Ratio 0 ≤ (VNEGB, VPOSB) < VSUPB 50 90 dB
Open-Loop Gain 125 dB
VSUPB - VSUPB
IOUTB = 100µA
15 -2
Output Voltage Swing High mV
VSUPB - VSUPB
IOUTB = 5mA
150 - 80
IOUTB = -100µA 2 15
Output Voltage Swing Low mV
IOUTB = -5mA 80 150
Short to VSUPB / 2, sourcing 50 150
Short-Circuit Current mA
Short to VSUPB / 2, sinking 50 140
Buffer configuration, VPOSB = 4V,
Output Current ±40 mA
VOUTB error < ±10mV
Power-Supply Rejection Ratio 6V ≤ VSUPB ≤ 13.2V, DC (VNEGB, VPOSB) = VSUPB / 2 60 100 dB
Slew Rate 12 V/µs
-3dB Bandwidth Buffer configuration, RL = 10kΩ, CL = 10pF 12 MHz
Gain-Bandwidth Product Buffer configuration, RL = 10kΩ, CL = 10pF 8 MHz
POSITIVE CHARGE-PUMP REGULATOR
FBP Regulation Voltage IGON = 10mA 2.425 2.500 2.575 V
VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V,
FBP Line-Regulation Error 25 mV
VGON = 27V, IGON = 20mA
FBP Input Bias Current VFBP = 2.5V -50 +50 nA
DRVP P-Channel On-Resistance 15 30 Ω
VFBP = 2.4V 6 12 Ω
DRVP N-Channel On-Resistance
VFBP = 2.6V 20 kΩ
FBP Fault Trip Level Falling edge 1.92 2.00 2.08 V
Positive Charge-Pump Soft-Start
212 oscillator clock cycles in a 7-bit DAC 2.73 ms
Period
NEGATIVE CHARGE-PUMP REGULATOR
FBN Regulation Voltage IGOFF = 10mA 200 250 300 mV
FBN Input Bias Current VFBN = 250mV -50 +50 nA
VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V,
FBN Line Regulation 25 mV
VVGOFF = -6V, IGOFF = -50mA
DRVN P-Channel On-Resistance 7.5 15 Ω
VFBN = 350mV 3 6 Ω
DRVN N-Channel On-Resistance
VFBN = 150mV 20 kΩ
FBN Fault Trip Level Rising edge 700 mV
Negative Charge-Pump Soft-Start
212 oscillator clock cycles in a 7-bit DAC 2.73 ms
Period

_______________________________________________________________________________________ 3
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
MAX8710/MAX8711/MAX8712

(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = 0°C to +85°C. Typical values are at TA =
+25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SEQUENCE CONTROL
SHDN Input Low Voltage 0.6 V
SHDN Input High Voltage 2.0 V
SHDN Input Current 1 µA
DLP Capacitor Charge Current During startup, VDLP = 1.0V 4 5 6 µA
DLP Turn-On Threshold 2.375 2.5 2.625 V
SHDN = low or fault tripped; DLP, FBP, FBN to GND 10 Ω
Pin Discharge Switch On-Resistance SHDN = low or fault tripped;
1 kΩ
MODE, OUTL, GON, OUTB to GND
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 2.0 V
CTL Input Leakage Current -1 +1 µA
VMODE = VREF, 1.5nF from GON to GND, VCTL = 0V to
CTL to GON Rising Propagation
3V step, no load on GON, measured from VCTL = 1.5V 100 ns
Delay
to GON = 20%

VMODE = VREF, 1.5nF from GON to GND, VCTL = 3V to

CTL to GON Falling Propagation
0V step, DRN falling, no load on DRN and GON, 100 ns
Delay
measured from VCTL = 1.5V to GON = 80%
SRC Input Voltage Range 28 V
SRC Input Current VMODE = VREF, VDLP = 3V, CTL = high 150 250 µA
DRN Input Current VMODE = VREF, VDRN = 8V, VDLP = 3V, VCTL = 0V 26 40 µA
SRC Switch On-Resistance VMODE = VREF, VDLP = 3V, CTL = high 15 30 Ω
DRN Switch On-Resistance VMODE = VREF, VDLP = 3V, VCTL = 0V 30 Ω
MODE Switch On-Resistance 1 kΩ
Mode 2 MODE Capacitor Charge
VMODE < MODE current-source stop voltage threshold 42 50 64 µA
Current

MODE Voltage Threshold for

Enabling DRN Switch Control in 2.3 2.5 2.7 V
Mode 2

MODE Current-Source Stop Voltage

VMODE rising edge 3.3 3.5 3.7 V
Threshold
THR to GON Voltage Gain 9.4 10 10.6 V/V
GON Falling Slew Rate 13.5 V/µs

4 _______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
ELECTRICAL CHARACTERISTICS

MAX8710/MAX8711/MAX8712
(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = -40°C to +100°C, unless otherwise noted.)
(Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
REF Output Voltage -10µA < IREF < 1mA (excluding internal load) 4.9 5.1 V
SUPCP Input Supply Range 2.7 13.2 V
Charge-Pump Regulators Operating
1200 1850 kHz
Frequency
LINEAR REGULATOR
Dropout Voltage IOUTL = 50mA 300 mV
FBL Regulation Voltage IOUTL = 50mA 2.455 2.545 V
FBL Fault Trip Level Falling edge 1.96 2.04 V
VINL = VIN = 10.8V~13.2V, VOUTL = 10V,
FBL Line-Regulation Error 15 mV
IOUTL = 50mA
Maximum OUTL Current VFBL = 2.4V 300 mA
OUTL Load Regulation VIN = 12V, 5mA < IOUTL < 300mA 2 %
OPERATIONAL AMPLIFIER
SUPB Supply Current Buffer configuration, VPOSB = 4V, no load 1.0 mA
Input Offset Voltage (VNEGB, VPOSB) = VSUPB / 2 14 mV
VSUPB -
IOUTB = 100µA
15
Output Voltage Swing High mV
VSUPB -
IOUTB = 5mA
150
IOUTB = -100µA 15
Output Voltage Swing Low mV
IOUTB = -5mA 150
Short to VSUPB / 2, sourcing 50
Short-Circuit Current mA
Short to VSUPB / 2, sinking 50
POSITIVE CHARGE-PUMP REGULATOR
FBP Regulation Voltage IGON = 10mA 2.425 2.575 V
VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V,
FBP Line-Regulation Error 25 mV
VGON = 27V, IGON = 20mA
FBP Input Bias Current VFBP = 3V -50 +50 nA
DRVP P-Channel On-Resistance 30 Ω
VFBP = 2.4V 12 Ω
DRVP N-Channel On-Resistance
VFBP = 2.6V 20 kΩ
NEGATIVE CHARGE-PUMP REGULATOR
FBN Regulation Voltage IGOFF = 10mA 200 300 mV
VOUTL (VSUPCP, MAX8710) = 10.8V~13.2V,
FBN Line Regulation 25 mV
VGOFF = -6V, IGOFF = -50mA
DRVN P-Channel On-Resistance 15 Ω
VFBN = 350mV 6 Ω
DRVN N-Channel On-Resistance
VFBN = 150mV 20 kΩ

_______________________________________________________________________________________ 5
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
MAX8710/MAX8711/MAX8712

(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 27V, TA = -40°C to +100°C, unless otherwise noted.)
(Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SEQUENCE CONTROL
SHDN Input Low Voltage 0.6 V
SHDN Input High Voltage 2.0 V
DLP Capacitor Charge Current During startup, VDLP = 1.0V 4 6 µA
DLP Turn-On Threshold 2.375 2.625 V
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
SRC Input Current VMODE = VREF, VDLP = 3V, CTL = high 250 µA
DRN Input Current VMODE = VREF, VDRN = 8V, VDLP = 3V, VCTL = 0V 40 µA
SRC Switch On-Resistance VMODE=VREF, VDLP = 3V, CTL = high 30 Ω
Mode 2 MODE Capacitor Charge
VMODE < MODE current-source stop voltage threshold 42 64 µA
Current

MODE Voltage Threshold for

Enabling DRN Switch Control in 2.3 2.7 V
Mode 2
Note 1: Specifications to -40°C and +100°C are guaranteed by design, not production tested.

Typical Operating Characteristics

(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 10V, TA = 0°C to +85°C. Typical values are at TA =
+25°C, unless otherwise noted.)
LINEAR-REGULATOR LOAD-TRANSIENT
LINEAR-REGULATOR LINE REGULATION LINEAR-REGULATOR LOAD REGULATION RESPONSE
MAX8710/11/12 toc03
1 0.5
MAX8710/11/12 toc01

MAX8710/11/12 toc02

0
OUTPUT VOLTAGE ERROR (%)

OUTPUT VOLTAGE ERROR (%)

0 10V
IOUTL = 50mA
-1
A

-2 IOUTL = 300mA -0.5

-3 VOUTL = 10V
-1.0 VINL = 12V B
-4
VOUTL = 10V 0mA

-5 -1.5
10 12 14 16 18 20 22 24 26 28 1 10 100 1000 20µs/div
INPUT VOLTAGE (V) LOAD CURRENT (mA) A: VOUTL, 50mV/div, AC-COUPLED
B: IOUTL, 200mA/div

6 _______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Typical Operating Characteristics (continued)

MAX8710/MAX8711/MAX8712
(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 10V, TA = 0°C to +85°C. Typical values are at TA =
+25°C, unless otherwise noted.)

LINEAR-REGULATOR PULSED LINEAR-REGULATOR OVERCURRENT CHARGE-PUMP NO-LOAD SUPPLY CURRENT

LOAD-TRANSIENT RESPONSE PROTECTION vs. SUPPLY VOLTAGE
MAX8710/11/12 toc04 MAX8710/11/12 toc05
2.0

MAX8710/11/12 toc06
10V 1.9

SUPPLY CURRENT (mA)

A
A
1.8
0V
1.7

B
1.6
0mA B

0mA 1.5
4µs/div 10ms/div 8 9 10 11 12 13 14
A: VOUTL, 100mV/div, AC-COUPLED A: VOUTL, 5V/div SUPPLY VOLTAGE (V)
B: IOUTL, 500mA/div B: IOUTL, 500mA/div

POSITIVE CHARGE-PUMP LOAD POSITIVE CHARGE-PUMP NEGATIVE CHARGE-PUMP LOAD

REGULATION LINE REGULATION REGULATION
0.5 0.2 0.25
MAX8710/11/12 toc07

MAX8710/11/12 toc09
MAX8710/11/12 toc08

VGOFF = -5V
0 0 INPUT = 12V
0
OUTPUT VOLTAGE ERROR (%)

OUTPUT VOLTAGE ERROR (%)

OUTPUT VOLTAGE ERROR (%)

-0.2 -0.25
-0.5
-0.4 -0.50
-1.0
-0.6 -0.75

-1.5
-0.8 -1.00
INPUT = 12V 20mA LOAD CURRENT
-2.0 -1.0 -1.25
0 10 20 30 40 50 10 11 12 13 14 0 20 40 60 80 100
LOAD CURRENT (mA) INPUT VOLTAGE (V) LOAD CURRENT (mA)
NEGATIVE CHARGE-PUMP LINE
REGULATION POWER-UP SEQUENCE SWITCH CONTROL FUNCTION (MODE 1)
MAX8710/11/12 toc11 MAX8710/11/12 toc12
0.2
MAX8710/11/12 toc10

0 A
OUTPUT VOLTAGE ERROR (%)

0V A
-0.2
0V
B
-0.4 0V

-0.6 B
0V
CGON = 1.5nF
-0.8
VGOFF = -5V C
IGOFF = 50mA C
-1.0 0V 0V
7 8 9 10 11 12 13 14 10ms/div 20µs/div
INPUT VOLTAGE (V) A: VOUTL, 10V/div A: VGON, 10V/div
B: VGOFF, 5V/div B: VMODE, 5V/div
C: VGON, 10V/div C: VCTL, 5V/div

_______________________________________________________________________________________ 7
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Typical Operating Characteristics (continued)
MAX8710/MAX8711/MAX8712

(Circuit of Figure 1. VIN = VINL = VSUPCP = 12V, VOUTL = VSUPB = 10V, VSRC = 10V, TA = 0°C to +85°C. Typical values are at TA =
+25°C, unless otherwise noted.)

SWITCH CONTROL FUNCTION (MODE 2) REFERENCE LOAD REGULATION REFERENCE vs. TEMPERATURE
MAX8710/11/12 toc13
0 0.2

MAX8710/11/12 toc14

MAX8710/11/12 toc15
-0.02
REF VOLTAGE ERROR (%)

REF VOLTAGE ERROR (%)

A 0

-0.04
0V -0.2
CGON = 1.5nF -0.06
B
0V -0.4
-0.08

C
0V -0.10 -0.6
20µs/div 0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100
A: VGON, 10V/div REF LOAD CURRENT (mA) TEMPERATURE (°C)
B: VMODE, 5V/div
C: VCTL, 5V/div
SUPB SUPPLY CURRENT OPERATIONAL-AMPLIFIER SMALL-SIGNAL OPERATIONAL-AMPLIFIER LARGE-SIGNAL
vs. SUPB VOLTAGE STEP RESPONSE (BUFFER CONFIGURATION) STEP RESPONSE (BUFFER CONFIGURATION)
MAX8710/11/12 toc17 MAX8710/11/12 toc18
1.0
MAX8710/11/12 toc16

A
0.8
SUPB SUPPLY CURRENT (mA)

0V A

0V
0.6

0.4 B
B
0V
0.2
BUFFER CONFIGURATION 0V
VOUTB = 0.5 x VPOSB
0
4 6 8 10 12 14 400ns/div 400ns/div
SUPB VOLTAGE (V) A: VPOSB, 50mV/div, AC-COUPLED A: VPOSB, 5V/div
B: VOUTB, 50mV/div, AC-COUPLED B: VOUTB, 5V/div
OPERATIONAL-AMPLIFIER LOAD-TRANSIENT OPERATIONAL-AMPLIFIER
RESPONSE (BUFFER CONFIGURATION) RAIL-TO-RAIL I/O
MAX8710/11/12 toc19 MAX8710/11/12 toc20

A
A
5V

0V

B 0V

0mA

1µs/div 40µs/div
A: VOUTB, 2V/div A: VPOSB, 5V/div
B: IOUTB, 50mA/div B: VOUTB, 5V/div

8 _______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Pin Description

MAX8710/MAX8711/MAX8712
PIN
NAME FUNCTION
MAX8710 MAX8711 MAX8712
Internal High-Voltage MOSFET Switch Common Terminal. GON is the output of the
GON 1 — — high-voltage switch-control block. GON is internally pulled to GND by a 1kΩ
resistor in shutdown.

Switch Input. Drain of the internal high-voltage back-to-back P-channel MOSFETs

DRN 2 — —
connected to GON.
Reference Output. Connect a 0.22µF capacitor from REF to GND. REF remains on
REF 3 1 1
in shutdown.
POSB 4 2 — Operational-Amplifier Noninverting Input
INL 5 3 2 Linear-Regulator Supply Input
NEGB 6 4 — Operational-Amplifier Inverting Input
IN 7 5 3 IC Supply Input. Bypass IN to GND with a 0.1µF capacitor.
Linear-Regulator Output. OUTL is internally pulled to GND by a 1kΩ resistor in
OUTL 8 6 4 shutdown. For the MAX8711/MAX8712, OUTL is also the supply input for the
charge-pump regulators.
Supply Input for the Charge-Pump Regulators. Connect a 0.1µF capacitor from
SUPCP 9 — —
SUPCP to GND.
Negative Charge-Pump Driver Output. Output high level is VSUPCP, and output
DRVN 10 7 5 low level is GND. DRVN is internally pulled high to SUPCP when the negative
charge pump is disabled.
Positive Charge-Pump Driver Output. Output high level is VSUPCP, and output low
DRVP 11 8 6
level is GND. DRVP is internally pulled low in shutdown.
N. C. 12 — — No Connect. Not internally connected.
GND 13 9 7 Ground
Operational-Amplifier Output. OUTB is internally pulled to GND by a 1kΩ resistor
OUTB 14 10 —
in shutdown.
SUPB 15 11 — Operational-Amplifier Supply Input. Bypass SUPB to GND with a 0.1µF capacitor.
GON Low-Level Regulation Set-Point Input. Connect THR to the center of a
THR 16 — — resistive voltage-divider between REF and GND to set the VGON regulation level.
The actual level is 10 × VTHR. See the Switch Control section for details.

_______________________________________________________________________________________ 9
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Pin Description (continued)
MAX8710/MAX8711/MAX8712

PIN
NAME FUNCTION
MAX8710 MAX8711 MAX8712

Positive Charge-Pump Feedback Input. Connect FBP to the center of a resistive

voltage-divider between the positive charge-pump regulator output and GND to
FBP 17 12 8
set the regulator output voltage. Place the divider within 5mm of FBP. FBP is
internally pulled to GND by a 10Ω resistor in shutdown.

Active-Low Shutdown Control Input. Pull SHDN low to turn off all sections of the
SHDN 18 13 9 device except REF. Pull SHDN high to enable the device. Cycle SHDN to reset the
device after a fault.

High-Voltage Switch-Control Block Timing Control Input. See the Switch Control
CTL 19 — —
section for details.

Linear-Regulator Feedback Input. Connect FBL to the center of a resistive

FBL 20 14 10 voltage-divider between the linear-regulator output and GND to set the linear-
regulator output voltage. Place the divider within 5mm of FBL.

High-Voltage Switch-Control Block-Mode Selection Input and Timing-Adjustment

Input. See the Switch Control section for details. MODE is high impedance when it
MODE 21 — —
is connected to REF. MODE is internally pulled to GND by a 1kΩ resistor during
REF UVLO, when VDLP < 2.5V, or in shutdown.
Positive Charge-Pump Startup Delay and High-Voltage Switch Delay Input.
DLP 22 15 11 Connect a capacitor from DLP to GND to set the delay time. A 5µA current source
charges CDLP. DLP is internally pulled to GND by a 10Ω resistor in shutdown.
Negative Charge-Pump Feedback Input. Connect FBN to the center of a resistive
voltage-divider between the negative output and REF to set the output voltage.
FBN 23 16 12
Place the divider within 5mm of FBN. FBN is internally pulled to GND through a
10Ω resistor in shutdown.
Switch Input. Source of the internal high-voltage P-channel MOSFET connected to
SRC 24 — —
GON.

Typical Operating Circuit input voltage to generate the source-driver ICs’ supply
voltage. The two built-in charge-pump regulators are
Figures 1, 2, and 3 are the Typical Operating Circuits of
used to generate the TFT gate-on and gate-off supplies.
the MAX8710, MAX8711, and MAX8712 for generating
The high-current operational amplifier is typically used to
power rails in TFT LCD panels. The input voltage range
drive the LCD backplane (VCOM) and features high out-
is from 10.8V to 13.2V. The AVDD output is 10V at
put current (150mA), fast slew rate (12V/µs), and wide
300mA, the V GON output is 27V at 20mA, and the
bandwidth (12MHz). Its rail-to-rail inputs and output maxi-
VGOFF output is -5V at 50mA.
mize flexibility.
Detailed Description Linear Regulator
The MAX8710/MAX8711/MAX8712 include a high-perfor- MAX8710/MAX8711/MAX8712 contain a linear regulator
mance linear regulator, a positive charge-pump regula- that uses an internal PNP pass transistor to supply load
tor, a negative charge-pump regulator, and built-in currents up to 300mA. Connect an external resistive volt-
power-up sequence control. The MAX8710 and age-divider between the regulator output and GND with
MAX8711 also include a high-current operational amplifi- the midpoint connected to FBL to adjust the linear-regu-
er. Additionally, the MAX8710 provides logic-controlled lator output. An error amplifier compares the FBL voltage
high-voltage switches to control the positive charge- with the 2.5V internal reference voltage and amplifies the
pump output. The linear regulator directly steps down the difference. If the feedback voltage is higher than the

10 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies

MAX8710/MAX8711/MAX8712
GND IN
10.8V TO 13.2V

0.1µF 10µF

GND IN N.C. INL

OUTL
C1
AVDD 47pF 4.7µF AVDD
10V/300mA
SUPB
0.1µF
120kΩ FBL
R2 R1
POSB 33.2kΩ 100kΩ
MAX8710 1% 1%
100kΩ IN
SUPCP
NEGB 0.1µF
MMBD4148SE
(FAIRCHILD)
OUTB 0.1µF
OUTB DRVP
0.1µF 0.1µF
MMBD4148SE
(FAIRCHILD) 0.1µF MMBD4148SE
0.22µF
(FAIRCHILD)
DRVN
GOFF 1µF
R5 VP
-5V/mA 27V/20mA
110kΩ FBP
1% FBN R4 R3
R6 33.2kΩ 325kΩ
100kΩ 1% 1%
1%
REF SRC
REF 0.47µF 1µF
5V/1mA 51.1kΩ
THR
GON
20kΩ GON
20kΩ
DRN
MODE

CTL
SHDN DLP
CTL
SHDN 100kΩ
0.1µF

Figure 1. Typical Operating Circuit of the MAX8710

______________________________________________________________________________________ 11
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
MAX8710/MAX8711/MAX8712

GND IN
10.8V TO 13.2V

0.1µF 10µF

GND IN INL
OUTL
C1
AVDD 47pF 4.7µF AVDD
10V/300mA
SUPB
0.1µF
120kΩ FBL
R1
R2 100kΩ
POSB MAX8711 33.2kΩ 1%
1%
100kΩ

NEGB

OUTB MMBD4148
OUTB MMBD4148SE 0.1µF
(FAIRCHILD) DRVP
0.22µF 0.1µF 1µF
DRVN
GOFF 1µF 0.1µF 2x MMBD4148SE
-5V/50mA (FAIRCHILD)
R5
110kΩ
1% GON
1µF
27V/20mA
FBN FBP
R4 R3
R6 33.2kΩ 325kΩ
100kΩ 1% 1%
1%

REF DLP
REF 0.47µF 0.1µF
5V/1mA

SHDN
SHDN

Figure 2. Typical Operating Circuit of the MAX8711

12 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies

MAX8710/MAX8711/MAX8712
GND IN
10.8V TO 13.2V

0.1µF 10µF

GND IN INL
MMBD4148SE OUTL
C1
(FAIRCHILD) AVDD
47pF 4.7µF
0.22µF 10V/300mA
DRVN
GOFF 1µF FBL
-5V/50mA R5 R1
110kΩ R2 100kΩ
1% 33.2kΩ 1%
FBN 1%
MAX8712
R6
100kΩ
1%
REF MMBD4148
0.1µF
REF
5V/1mA 0.47µF DRVP
0.1µF 1µF

DLP 0.1µF 2x MMBD4148SE

(FAIRCHILD)
0.1µF
GON
1µF
27V/20mA

SHDN FBP
SHDN R4 R3
33.2kΩ 325kΩ
1% 1%

Figure 3. Typical Operating Circuit of the MAX8712

reference voltage, the controller lowers the base current approximately 2µs. The period of the pulse load is
of the PNP transistor, which reduces the amount of cur- between 8.9µs and 31.7µs. The excellent transient perfor-
rent delivered to the output. If the feedback voltage is too mance of the linear regulator can easily meet this tran-
low, the device increases the PNP transistor’s base cur- sient-response requirement.
rent, which allows more current to pass to the output and The linear regulator can deliver at least 300mA output
raises the output voltage. The linear regulator also current continuously with a 4.7µF output capacitor. Do not
includes an output current limit that protects the internal allow the device power dissipation to exceed the pack-
pass transistor against short circuits. age-dissipation limit listed in the Absolute Maximum
The input voltage range of the linear regulator is from 8V Ratings section. The power dissipation can be estimated
to 28V. The Typical Operating Circuits shown use a 12V by multiplying the voltage difference between the input
input. The output voltage range of the linear regulator and the output with the required maximum continuous
(OUTL) is up to 28V (MAX8710) or up to 14V output current. For applications where the power dissipa-
(MAX8711/MAX8712). The linear-regulator output is used tion exceeds the package limit, see the External
to generate the AVDD voltage, which is the analog supply Transistor for Higher Current or Power Dissipation section
rail for source-driver ICs in TFT LCD panels. The typical for more information.
load of the AVDD supply is a periodic pulsed load, with a The linear regulator is enabled whenever REF is in regula-
peak current of approximately 1A and pulse width of tion and SHDN is logic high. Each time it is enabled, the

______________________________________________________________________________________ 13
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
MAX8710/MAX8711/MAX8712

IN

IN
INL
GND
MAX8710

REF
REF REF
LINEAR OUTL
AVDD
REG FBL
FBN

SUPCP OSC
VIN
SHDN

VGOFF DRVN DRVP

DLP
SEQ

POSB VP
AVDD
SUPB
AVDD
FBP

OUTB
VCOM

NEGB

MODE SRC

SWITCH
CONTROL GON
VGON
CTL
CTL REF
DRN

THR

Figure 4. MAX8710 Functional Diagram

14 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
linear regulator goes through a soft-start routine by ramp- and the setting of the feedback divider determine the out-

MAX8710/MAX8711/MAX8712
ing up its internal reference voltage from 0 to 2.5V in 128 put voltage of the positive charge-pump regulator. The
steps. The soft-start period is 2.73ms (typ), and FBL fault charge pump includes a high-side P-channel MOSFET
detection is disabled during this period. This soft-start (P1) and a low-side N-channel MOSFET (N1) to control
feature effectively limits the inrush current during startup. the power transfer as shown in Figure 5. The MOSFETs
The linear-regulator current-limit circuitry monitors the switch at a constant frequency of 1.5MHz.
current flowing through the internal pass transistor. The During the first half-cycle, N1 turns on and allows VINPUT
internal current limit is approximately 800mA. The linear- (VSUPCP, MAX8710 or VOUTL, MAX8711/MAX8712) to
regulator output declines when it is not able to supply the charge up the flying capacitor CX(POS) through diode
load current. If the FBL voltage drops below 0.75V, the D1. The amount of charge transferred from VINPUT to
current limit folds back to approximately 100mA. CX(POS) is determined by the on-resistance of N1, which
The MAX8710/MAX8711/MAX8712 monitor the FBL volt- varies according to the output of the feedback error
age for undervoltage conditions. If VFBL is continuously amplifier. The error amplifier compares the feedback sig-
below 2V (typ) for approximately 44ms, the device latch- nal (FBP) with a 2.5V internal reference and amplifies the
es off. The foldback current-limit circuit, in conjunction difference. If the feedback signal is below the reference,
with the output undervoltage fault latch and thermal-over- the error-amplifier output increases the supply voltage of
load protection, protects the output load and the internal N1’s gate driver, lowering the on-resistance. Similarly, if
pass transistor against short circuits or overloads. the feedback signal is above the reference, the error-
amplifier output reduces the driver supply voltage,
Positive Charge-Pump Regulator increasing the on-resistance. During the second half-
The positive charge-pump regulator is typically used to cycle, N1 turns off and P1 turns on, level shifting CX(POS)
generate the positive supply rail for the TFT LCD gate-dri- by VINPUT volts. This connects CX(POS) in parallel with
ver ICs. The output voltage is set with an external resistive the reservoir capacitor C OUT(POS) . If the voltage
voltage-divider from its output to GND with the midpoint across COUT(POS) plus a diode drop (VPOS + VDIODE) is
connected to FBP. The number of charge-pump stages smaller than the level-shifted flying-capacitor voltage

REF

FBN
MAX8710
SUPCP
VSUPCP

D4 D1
P2 P1
VNEG VSUPCP
DRVN 0.5 x VREF DRVP
COUT(NEG)
CX(NEG) CX(POS)
N2 250mV N1
D3 D2 VPOS

COUT(POS)
OSCILLATOR
FBP

SEQUENCE

Figure 5. Charge-Pump Regulator Functional Diagram

______________________________________________________________________________________ 15
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
(V CX(POS) + V INPUT ), charge flows from CX(POS) to time it is enabled, the negative charge-pump regulator
MAX8710/MAX8711/MAX8712

COUT(POS) until diode D2 turns off. goes through a soft-start routine by ramping down its
The positive charge-pump regulator’s startup can be internal reference voltage from 5V to 250mV in 128
delayed by connecting an external capacitor from DLP steps. The soft-start period is 2.73ms (typ), and FBN
to GND. An internal constant current source begins fault detection is disabled during this period. The soft-
charging the DLP capacitor when SHDN is logic high start feature effectively limits the inrush current during
and REF reaches regulation. When the DLP voltage startup. The MAX8710/MAX8711/MAX8712 also monitor
exceeds VREF / 2, the positive charge-pump regulator the FBN voltage for undervoltage conditions. If VFBN is
is enabled. Each time it is enabled, the positive charge- continuously above 700mV (typ) for approximately
pump regulator goes through a soft-start routine by 44ms, the device latches off.
ramping up its internal reference voltage from 0 to 2.5V Operational Amplifier
in 128 steps. The soft-start period is 2.73ms (typ), and (MAX8710/MAX8711)
FBP fault detection is disabled during this period. The The MAX8710/MAX8711s’ operational amplifier features
soft-start feature effectively limits the inrush current dur- high output current (150mA), fast slew rate (7.5V/µs),
ing startup. The MAX8710/MAX8711/MAX8712 also and wide bandwidth (12MHz). The operational amplifier
monitor the FBP voltage for undervoltage conditions. If is enabled when REF is in regulation and SHDN is logic
VFBP is continuously below 2V (typ) for approximately high. The output of the amplifier (OUTB) is internally
44ms, the device latches off. pulled to ground through a 1kΩ resistor in shutdown.
Negative Charge-Pump Regulator The amplifier is typically used to drive the backplane
The negative charge-pump regulator is typically used to (VCOM) of TFT LCD panels. The LCD backplane
generate the negative supply rail for the TFT LCD gate- consists of a distributed series capacitance and resis-
driver ICs. The output voltage is set with an external resis- tance, a load that can be easily driven by this opera-
tive voltage-divider from its output to REF with the mid- tional amplifier. However, if the operational amplifier is
point connected to FBN. The number of charge-pump used in an application with a pure capacitive load,
stages and the setting of the feedback divider determine steps must be taken to ensure stable operation. As the
the output of the negative charge-pump regulator. The operational amplifier’s capacitive load increases, the
charge-pump controller includes a high-side P-channel amplifier’s bandwidth decreases and its gain peaking
MOSFET (P2) and a low-side N-channel MOSFET (N2) to increases. To ensure stable operation, a 5Ω to 50Ω
control the power transfer as shown in Figure 5. The resistor can be placed between OUTB and the capaci-
MOSFETs switch a constant frequency of 1.5MHz. tive load to reduce gain peaking.
During the first half-cycle, P2 turns on and allows The operational amplifier limits short-circuit current to
V INPUT to charge up the flying capacitor C X(NEG) approximately ±150mA if the output is directly shorted
through diode D3. During the second half-cycle, P2 to SUPB or to GND. If the short-circuit condition
turns off and N2 turns on, level shifting CX(NEG) by VIN- persists, the junction temperature of the IC rises until it
PUT volts. This connects CX(NEG) in parallel with reser- trips the IC’s thermal-overload protection.
voir capacitor C OUT(NEG) . If the voltage across
COUT(NEG) minus a diode drop is greater than the volt- Reference Voltage (REF)
age across CX(NEG), charge flows from COUT(NEG) to The reference output is nominally 5V and can source
CX(NEG) until the diode D4 turns off. The amount of up to 1mA (see the Typical Operating Characteristics).
charge transferred to the output is controlled by the on- Bypass REF with a 0.22µF ceramic capacitor connect-
resistance of N2, which varies according to the output ed between REF and GND. The reference remains
of the feedback error amplifier. The error amplifier com- enabled in shutdown.
pares the feedback signal (FBN) with a 250mV internal
Power-Up Sequence and Shutdown Control
reference and amplifies the difference. If the feedback
When the MAX8710/MAX8711/MAX8712 are powered
signal is above the reference, the error-amplifier output
up, REF rises with the voltage on IN. After REF reaches
increases the supply voltage of N2’s gate driver, lower-
regulation and if SHDN is logic high, the linear regula-
ing the on-resistance. Similarly, if the feedback signal is
tor, operational amplifier, and negative charge-pump
below the reference, the error-amplifier output reduces
regulator are enabled and begin their respective soft-
the driver supply voltage, increasing the on-resistance.
start routines. After the soft-start routines are complet-
The negative charge-pump regulator is enabled when
SHDN is logic high and REF reaches regulation. Each

16 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
ed, the fault-protection circuits for the linear regulator Thermal-Overload Protection

MAX8710/MAX8711/MAX8712
and the negative charge-pump regulator are activated. The thermal-overload protection prevents excessive
When the linear regulator is enabled, the positive power dissipation from overheating the IC. When the
charge-pump-regulator delay block is enabled. An junction temperature exceeds +160°C, a thermal sensor
internal current source starts charging the DLP capaci- immediately activates the fault protection, which shuts
tor. The voltage on DLP linearly rises because of the down all the outputs except the reference, allowing the
constant charging current. When V DLP goes above device to cool down. Once the device cools down by
VREF / 2, the switch control block is enabled, and the approximately 15°C, the IC restarts automatically.
positive charge-pump regulator begins its soft-start. Switch Control (MAX8710)
After the positive charge-pump regulator’s soft-start is The MAX8710’s switch-control block (Figure 6) consists
completed, the fault protection of the positive charge- of a high-voltage P-channel MOSFET Q1 between SRC
pump regulator is also enabled. and GON, and a common-source-connected P-channel
The MAX8710/MAX8711/MAX8712 enter into shutdown MOSFET pair Q2 between GON and DRN. The switch-
when SHDN is pulled low or REF falls below 4.5V. In control block is enabled when VDLP goes above VREF /
shutdown, OUTL, GON and OUTB are all internally 2. Q1 and Q2 are controlled by CTL and MODE. There
pulled to ground with 1kΩ resistors. FBN, FBP, and DLP are two different modes of operation.
are all internally pulled to ground with 10Ω resistors in Activate the first mode by connecting MODE to REF.
shutdown. The DLP current source is disabled in shut- When CTL is logic high, Q1 turns on and Q2 turns off,
down and a switch discharges CDLP to ground. REF connecting GON to SRC. When CTL is logic low, Q1
remains on in shutdown. Pulling SHDN high when REF turns off and Q2 turns on, connecting GON to DRN.
is above 4.5V reactivates the IC. Output fault protection GON can then be discharged through a resistor con-
and thermal-overload protection can also turn off the nected between DRN and GND or OUTL. Q2 turns off
IC’s outputs. See the respective sections for details. and stops discharging GON when VGON reaches 10
Output Fault Protection times the voltage on THR.
During steady-state operation, if the output of the linear When VMODE is less than 0.9 x VREF, the switch-control
regulator or any of the charge-pump regulator outputs block works in the second mode. The rising edge of VCTL
does not exceed its respective fault-detection thresh- turns on Q1 and turns off Q2, connecting GON to SRC.
old, the MAX8710/MAX8711/MAX8712 activate an inter- An internal N-channel MOSFET Q5 between MODE and
nal fault timer. If any condition or the combination of GND is also turned on to discharge an external capacitor
conditions indicates a continuous fault for the fault- between MODE and GND. The falling edge of VCTL turns
timer duration (44ms typ), the MAX8710/MAX8711/ off Q5, and an internal 50µA current source starts charg-
MAX8712 set the fault latch, shutting down all the out- ing the MODE capacitor. Once VMODE exceeds 0.5 x
puts except the reference. Once the fault condition is VREF, the switch-control block turns off Q1 and turns on
removed, cycle the input voltage or toggle SHDN to Q2, connecting GON to DRN. GON can then be dis-
clear the fault latch and reactivate the device. Each charged through a resistor connected between DRN and
regulator’s fault-detection circuit is disabled during the GND or OUTL. Q2 turns off and stops discharging GON
regulator’s soft-start time. when VGON reaches 10 times the voltage on THR.

______________________________________________________________________________________ 17
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
MAX8710/MAX8711/MAX8712

REF

5µA MAX8710

DLP
FAULT
Q4 SHDN
REF OK

SRC
0.5 x VREF
Q1

GON

9R
1kΩ

Q2
Q3 R

REF DRN
50µA
THR
R

4R

MODE

1kΩ 5R

Q5

CTL

Figure 6. MAX8710 High-Voltage Switch Control

18 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Design Procedure where IPULSE is the height of the pulse load, and tPULSE

MAX8710/MAX8711/MAX8712
is the pulse width. Higher capacitance and lower ESR
Linear Regulator result in less voltage dip. The ESR dip can be ignored
Output-Voltage Selection when using ceramic output capacitors. Calculate the
Adjust the linear-regulator output voltage by connecting minimum required capacitance for the maximum allowed
a resistive voltage-divider from the linear-regulator out- dip using:
put AVDD to GND with the center tap connected to FBL
(Figure 1). Select the lower resistor of the divider R2 in I × tPULSE
COUT(MIN) ≈ PULSE
the range of 10kΩ to 50kΩ. Calculate the upper resistor VDIP(MAX)
R1 with the following equation:
The above equations are “worst-case” and assume that
V  the linear regulator does not react to correct the output
R1 = R2 ×  AVDD − 1 voltage during the load pulse. In fact, the regulator is
 VFBL 
fast enough to partially correct the output voltage, so
where VFBL = 2.5V (typ) is the regulation point of the the actual dip may be smaller, or a smaller capacitor
linear regulator. may be acceptable. For the typical load pulse
described above, assuming the voltage dip must be
Input-Capacitor Selection limited to 150mV, the minimum output capacitor is:
The linear regulator’s output stage consists of a PNP pass
transistor. Rapid movements of the input voltage must be 1A × 1µs
avoided since the movement can be coupled into the COUT(MIN) ≈ = 6.7µF
base of the transistor through the base-to-emitter junction 0.15V
capacitance. The input capacitor reduces the current Because the regulator is able to limit the dip somewhat,
peaks drawn from the input supply and slows down the the circuit of Figure 1 uses a 4.7µF output capacitor.
input voltage movement. One 10µF ceramic capacitor is The voltage rating and temperature characteristics of
used in the Typical Operating Circuits (Figure 1, 2, and 3) the output capacitor must also be considered.
because of the high source impedance seen in typical
lab setups. Actual applications usually have much lower Feed-Forward Compensation
source impedance, since the linear regulator typically The output capacitance and equivalent load resistance
runs directly from the output of another regulated supply determine the dominant pole. An internal parasitic
and can operate with less input capacitance. capacitance of the regulator creates a second pole.
This pole typically occurs at 100kHz, but can vary
Output-Capacitor Selection between 60kHz and 140kHz depending on the process
The output capacitor and its equivalent series resistance variation. Since the pole occurs after the loop gain
(ESR) affect the linear regulator’s stability and transient crossover, it does not affect the loop stability. However,
response. The regulator can deliver at least 300mA out- canceling this pole with an additional zero can improve
put current continuously with a 4.7µF output capacitor. the load-transient response.
The typical load on the linear regulator for source-driver A zero can be added by connecting a feed-forward
applications is a large pulsed load, with a peak current capacitor (C1) between OUTL and FBL as shown in
of approximately 1A and pulse width of approximately Figure 1. The frequency of the zero can be calculated
2µs. The shape of the pulse is close to a triangle, so it with the following equation:
is equivalent to a square pulse with 1A height and 1µs
pulse width. The total voltage dip during the pulsed
load transient also has two components: the ohmic dip 1
fZERO =
due to the output capacitor’s ESR, and the capacitive 2π × R1 × C1
dip caused by discharging the output capacitance:
where R1 is the upper resistor of the feedback divider.
VDIP = VDIP(ESR) + VDIP(C) To cancel the second pole, the zero should be placed
at or below the frequency of the second pole. Because
VDIP(ESR) = IPULSE × RESR the frequency of the second pole varies between
I × tPULSE 60kHz and 140kHz, the zero can be placed between
VDIP(C) ≈ PULSE 40kHz and 60kHz.
COUT

______________________________________________________________________________________ 19
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Charge-Pump Regulators Output Voltage Selection
MAX8710/MAX8711/MAX8712

Number of Charge-Pump Stages Adjust the positive charge-pump-regulator output volt-

For highest efficiency, always choose the lowest num- age by connecting a resistive voltage-divider from the
ber of charge-pump stages that meets the output regulator output VP to GND with the center tap connect-
requirement. ed to FBP (Figure 1). Select the lower resistor of divider
R4 in the range of 10kΩ to 50kΩ. Calculate upper resistor
The number of positive charge-pump stages is given by: R3 with the following equation:
VP + VSWITCH − VSUPCP  V 
nPOS = R3 = R4 ×  P − 1
VINPUT − 2 × VDIODE V
 FBP 

where nPOS is the number of positive charge-pump where VFBP = 2.5V (typ) is the regulation point of the
stages, VP is the positive charge-pump regulator out- positive charge-pump regulator.
put, VINPUT is the supply voltage for the charge-pump
regulators (V SUPCP, MAX8710 or V OUTL, MAX8711/ Adjust the negative charge-pump-regulator output volt-
MAX8712), VDIODE is the forward-voltage drop of the age by connecting a resistive voltage-divider from the
charge-pump diode, and VSWITCH is the voltage drop negative charge-pump output VGOFF to REF with the
of the internal switches. Use VSWITCH = 0.3V. center tap connected to FBN (Figure 1). Select R6 in
the 20kΩ to 100kΩ range. Calculate R5 with the follow-
The number of negative charge-pump stages is given by: ing equation:
− VGOFF + VSWITCH VFBN − VGOFF
nNEG = R5 = R6 ×
VINPUT − 2 × VDIODE VREF − VFBN

where nNEG is the number of negative charge-pump where VREF = 5V and VFBN = 250mV is the regulation
stages and VGOFF is the negative charge-pump regula- point of the negative charge-pump regulator.
tor output.
The above equations are derived based on the Flying Capacitor
assumption that the first stage of the positive charge Increasing the flying-capacitor (CX) value lowers the
pump is connected to VMAIN and the first stage of the effective source impedance and increases the output-
negative charge pump is connected to ground. current capability of the charge pump. Increasing the
Sometimes fractional stages are more desirable for bet- capacitance indefinitely has a negligible effect on out-
ter efficiency. This can be done by connecting the first put-current capability because the internal switch resis-
stage to another available supply, such as a 5V supply. tance and the diode impedance place a lower limit on
If the first charge-pump stage is powered from 5V, then the source impedance. A 0.1µF ceramic capacitor
the above equations become: works well in most low-current applications. The flying
capacitor’s voltage rating must exceed the following:
VP + VSWITCH − 5V VCX > n x VINPUT
nPOS =
VINPUT − 2 × VDIODE where n is the stage number in which the flying capaci-
− VGOFF + VSWITCH + 5V tor is used, and VINPUT is the supply voltage for the
nNEG = charge-pump regulators (VSUPCP, MAX8710 or VOUTL,
VINPUT − 2 × VDIODE
MAX8711/MAX8712).
Charge-Pump Input Capacitor
Use an input capacitor with a value equal to or greater
than the flying capacitor. Place the capacitor as close
to the IC as possible. Connect the capacitor directly
to PGND.

20 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Charge-Pump Output Capacitor

MAX8710/MAX8711/MAX8712
VIN = 19V
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
51Ω
peak transient voltage. With ceramic capacitors, the 4.7µF
output voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
INL KSB834W
required capacitor value:
(FAIRCHILD)

ILOAD _ CP OUTL AVDD = 10V

LINEAR
COUT _ CP ≥ REGULATOR
2 fOSC VRIPPLE _ CP 140kΩ 4.7µF
FBL
where COUT_CP is the output capacitor of the charge
pump, I LOAD_CP is the load current of the charge 20kΩ

pump, and V RIPPLE_CP is the desired peak-to-peak MAX8710

MAX8711
value of the output ripple.
MAX8712
Charge-Pump Rectifier Diode
Use low-cost silicon switching diodes with a current rat- Figure 7. High-Power Linear Regulator
ing equal to or greater than two times the average
charge-pump input current. If it helps avoid an extra
stage, some or all of the diodes can be replaced with
REF
Schottky diodes with an equivalent current rating.
0.47µF
Applications Information MAX8710
VDD
External Transistor for Higher Current OUTL MAX8711

or Power Dissipation 4.7µF

The load current and the voltage difference between MAX1512
the input and output determine the linear regulator’s SUPB
CE AVDD
power dissipation as shown in the following equation: 0.1µF
20kΩ
PDISSIPATION = (VINL - VOUTL) x IOUTL
POSB TO
OUT
For some applications, the input voltage to the linear OUTB VCOM
regulator is from a 19V adapter. To make a 10V output, NEGB
100kΩ
the voltage across the pass transistor is 9V. In this case, CTL SET
the regulator’s power dissipation may exceed the dissi-
pation limit that the package can handle. In some other GND
applications, the load current may be much higher than 25kΩ
the regulator’s guaranteed 300mA output current.
The solution for such applications is to connect an exter-
nal PNP transistor with the internal PNP transistor in a Figure 8. Using the MAX1512 to Adjust the VCOM Buffer Output
Darlington configuration as shown in Figure 7. The
external pass transistor must be able to handle most of Using the MAX1512 VCOM Calibrator
the power dissipation since most of the load current to Adjust the Buffer Output
flows through it. On the other hand, the power dissipat- The operational amplifier is typically used as the VCOM
ed in the internal pass transistor is very low. The current- buffer in TFT LCD panels. The output voltage of the
limit circuit will not work if an external pass transistor is VCOM buffer can be adjusted using the MAX1512,
used because the linear regulator only senses the cur- which is an EEPROM-programmable VCOM calibrator,
rent of the internal pass transistor. using the circuit shown in Figure 8. Refer to the
MAX1512 data sheet for details.

______________________________________________________________________________________ 21
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Pin Configurations (continued)
MAX8710/MAX8711/MAX8712

PC Board Layout Guidelines

Careful PC board layout is important for proper opera-

SHDN
tion. Use the following guidelines for good PC board

FBN

DLP

FBL
TOP VIEW
layout:
16 15 14 13
1) Create a power ground island consisting of the lin-
ear-regulator input and output-capacitor ground
connections, the GND pin, and the capacitor REF 1 12 FBP
ground connections for the charge-pump regula-
tors. Connect all these together with short, wide POSB 2 11 SUPB
traces or a small ground plane. Maximizing the MAX8711
width of the power ground traces improves efficien- INL 3 10 OUTB
cy. Create an analog ground island consisting of all
the feedback-divider ground connections, the oper- NEGB 4 9 GND
ational-amplifier divider ground connection, the REF
capacitor ground connection, the MODE capacitor 5 6 7 8
ground connection, the DLP capacitor ground con-

IN

OUTL

DRVN

DRVP
nection, and the device’s exposed backside pad.
Connect the analog ground island and the power THIN QFN 4mm x 4mm
ground island by connecting the GND pin directly to

DLP
FBN

FBL
the exposed backside pad. Make no other connec-
tions between these separate ground islands. 12 11 10
2) Place all feedback voltage-divider resistors as close
to their respective feedback pins as possible. The REF 1 9 SHDN
divider’s center trace should be kept short. Placing
the resistors far away causes their FB traces to INL 2 8
MAX8712 FBP
become antennas that can pick up noise from the
switching nodes of the charge pumps. Avoid running
IN 3 7 GND
any feedback trace near these switching nodes.
3) Place IN, INL, SUPB, SUPCP, and REF pin bypass
capacitors close to the IC. The ground connection 4 5 6
of the IN bypass capacitor should be connected
OUTL

DRVP
DRVN

directly to the GND pin with a wide trace.

4) Minimize the length and maximize the width of the THIN QFN 4mm x 4mm
traces between the output capacitors and the load
for best transient responses.
5) Minimize the size of the switching nodes (DRVP and Chip Information
DRVN). Keep the switching nodes away from feed-
back nodes (FBL, FBP, and FBN) and the analog TRANSISTOR COUNT: 3946
ground. Use DC traces as a shield if necessary. PROCESS: BiCMOS
Refer to the MAX8710 evaluation kit for an example of
proper board layout.

22 ______________________________________________________________________________________
 Low-Cost Linear-Regulator
LCD Panel Power Supplies
Package Information

MAX8710/MAX8711/MAX8712
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)

24L QFN THIN.EPS

PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
1
21-0139 B 2

PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
2
21-0139 B 2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.