Lab 3 DP
Lab 3 DP
Lab-3
Anuj Pasaya
202101509
Q1:
module fulladd(
input a,
input b,
input cin,
output sum,
output carry
);
endmodule
module FullAdder(
input [7:0]a,
input [7:0]b,
input cin,
output [7:0]sum,
);
wire[6:0] c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);
fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
fulladd a4(a[3],b[3],c[2],sum[3],c[3]);
fulladd a5(a[4],b[4],c[3],sum[4],c[4]);
fulladd a6(a[5],b[5],c[4],sum[5],c[5]);
fulladd a7(a[6],b[6],c[5],sum[6],c[6]);
fulladd a8(a[7],b[7],c[6],sum[7],cout);
assign flag[2]=c[3];
assign flag[3]=!sum[0];
assign flag[4]=cout;
endmodule
Q2:
module Decoder(
input [7:0]m,
output [8:0]p,
output e
);
assign p[7:0]=m[7:0];
endmodule
Q3:
module Exercise1 (
input [7:0] a,
input [7:0] b,
output reg equal,
output reg less,
output reg greater
);
always @(*)
begin
equal = 0;
less = 0;
greater = 0;
if (a == b) begin
equal = 1;
end else if (a < b) begin
less = 1;
end else begin
greater = 1;
end
end
endmodule
Q4:
module multiplier_concat(
input [3:0] A,
input [3:0] B,
);
integer i;
always @(*) begin
if (B[i])
end
end
endmodule