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Lab6 DP

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9 views8 pages

Lab6 DP

Uploaded by

anujpasaya7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab Report

18 September 2024
Digital Programming Lab
Anuj Pasaya
Roll No - 202101509
Task 1:
`timescale 1ns / 1ps
module AC_Controller (input [7:0] temperature, output reg fan_speed );
always @(*) begin
if (temperature >= 8'd20 && temperature <= 8'd30) begin
fan_speed = 0;
end
else if (temperature > 8'd30 && temperature <= 8'd40) begin
fan_speed = 0;
end
else if (temperature > 8'd40 && temperature <= 8'd50) begin
fan_speed = 1;
end
else if (temperature > 8'd50) begin
fan_speed = 1;
end
else begin
fan_speed = 0;
end
end
endmodule

Output Waveform:
Task 2:
`timescale 1ns / 1ps

module SecAccCntrl ( input wire [1:0] access_code, input wire EN, output reg [3:0] door_unlock);

always @(*) begin


if (EN) begin
case (access_code)
2'b00: door_unlock = 4'b0001;
2'b01: door_unlock = 4'b0010;
2'b10: door_unlock = 4'b0100;
2'b11: door_unlock = 4'b1000;
default: door_unlock = 4'b0000;
endcase
end
else begin
door_unlock = 4'b0000;
end
end

endmodule

Output Waveform:
Task 3:
`timescale 1ns / 1ps

module Decoder3to8( input wire A, B, C, output wire [7:0] Y);


assign Y[0] = ~A & ~B & ~C;
assign Y[1] = ~A & ~B & C;
assign Y[2] = ~A & B & ~C;
assign Y[3] = ~A & B & C;
assign Y[4] = A & ~B & ~C;
assign Y[5] = A & ~B & C;
assign Y[6] = A & B & ~C;
assign Y[7] = A & B & C;
endmodule

module BooleanFunction( input wire A, B, C, output wire F);

wire [7:0] Y;
Decoder3to8 decoder(.A(A), .B(B), .C(C), .Y(Y));

assign F = Y[2] | Y[3] | Y[5] | Y[6] | Y[7];

endmodule

Output Waveform:
Task 4:
`timescale 1ns / 1ps

module HexToBinaryEncoder(input [3:0] hex, output reg [3:0] bin);


always @(*) begin
case(hex)
4'h0: bin = 4'b0000;
4'h1: bin = 4'b0001;
4'h2: bin = 4'b0010;
4'h3: bin = 4'b0011;
4'h4: bin = 4'b0100;
4'h5: bin = 4'b0101;
4'h6: bin = 4'b0110;
4'h7: bin = 4'b0111;
4'h8: bin = 4'b1000;
4'h9: bin = 4'b1001;
4'hA: bin = 4'b1010;
4'hB: bin = 4'b1011;
4'hC: bin = 4'b1100;
4'hD: bin = 4'b1101;
4'hE: bin = 4'b1110;
4'hF: bin = 4'b1111;
endcase
end
endmodule
Output Waveform:
Task 5:
timescale 1ns / 1ps

module Decoder3to8 ( input A, B, Cin, output reg [7:0] D);


always @(*) begin
D = 8'b00000000;
case ({A, B, Cin})
3'b000: D[0] = 1;
3'b001: D[1] = 1;
3'b010: D[2] = 1;
3'b011: D[3] = 1;
3'b100: D[4] = 1;
3'b101: D[5] = 1;
3'b110: D[6] = 1;
3'b111: D[7] = 1;
endcase
end
endmodule

module FullAdderWithDecoder ( input A, B, Cin, output Sum, Cout);


wire [7:0] D;

Decoder3to8 decoder (.A(A),.B(B),.Cin(Cin),.D(D));

assign Sum = D[1] | D[2] | D[4] | D[7];


assign Cout = D[3] | D[5] | D[6] | D[7];

endmodule
Output Waveform:
Task 6(Behavioral):
`timescale 1ns / 1ps

module Demux1to16_behavioral ( input wire [3:0] sel, input wire in, output reg [15:0] out);
always @(*) begin
out = 16'b0;
case (sel)
4'b0000: out[0] = in;
4'b0001: out[1] = in;
4'b0010: out[2] = in;
4'b0011: out[3] = in;
4'b0100: out[4] = in;
4'b0101: out[5] = in;
4'b0110: out[6] = in;
4'b0111: out[7] = in;
4'b1000: out[8] = in;
4'b1001: out[9] = in;
4'b1010: out[10] = in;
4'b1011: out[11] = in;
4'b1100: out[12] = in;
4'b1101: out[13] = in;
4'b1110: out[14] = in;
4'b1111: out[15] = in;
default: out = 16'b0;
endcase
end
endmodule
Task 6(RTL/Dataflow):
`timescale 1ns / 1ps

module Demux1to16_RTL ( input wire [3:0] sel, input wire in, output wire [15:0] out);
assign out = (sel == 4'b0000) ? 16'b0000000000000001 & {16{in}} :
(sel == 4'b0001) ? 16'b0000000000000010 & {16{in}} :
(sel == 4'b0010) ? 16'b0000000000000100 & {16{in}} :
(sel == 4'b0011) ? 16'b0000000000001000 & {16{in}} :
(sel == 4'b0100) ? 16'b0000000000010000 & {16{in}} :
(sel == 4'b0101) ? 16'b0000000000100000 & {16{in}} :
(sel == 4'b0110) ? 16'b0000000001000000 & {16{in}} :
(sel == 4'b0111) ? 16'b0000000010000000 & {16{in}} :
(sel == 4'b1000) ? 16'b0000000100000000 & {16{in}} :
(sel == 4'b1001) ? 16'b0000001000000000 & {16{in}} :
(sel == 4'b1010) ? 16'b0000010000000000 & {16{in}} :
(sel == 4'b1011) ? 16'b0000100000000000 & {16{in}} :
(sel == 4'b1100) ? 16'b0001000000000000 & {16{in}} :
(sel == 4'b1101) ? 16'b0010000000000000 & {16{in}} :
(sel == 4'b1110) ? 16'b0100000000000000 & {16{in}} :
(sel == 4'b1111) ? 16'b1000000000000000 & {16{in}} : 16'b0;

endmodule
Task 6(STRUCTURAL):
`timescale 1ns / 1ps

module Demux1to16_structural(input wire [3:0] sel, input wire in, output wire [15:0] out);

wire [15:0] y;

and (y[0], in, ~sel[3], ~sel[2], ~sel[1], ~sel[0]);


and (y[1], in, ~sel[3], ~sel[2], ~sel[1], sel[0]);
and (y[2], in, ~sel[3], ~sel[2], sel[1], ~sel[0]);
and (y[3], in, ~sel[3], ~sel[2], sel[1], sel[0]);
and (y[4], in, ~sel[3], sel[2], ~sel[1], ~sel[0]);
and (y[5], in, ~sel[3], sel[2], ~sel[1], sel[0]);
and (y[6], in, ~sel[3], sel[2], sel[1], ~sel[0]);
and (y[7], in, ~sel[3], sel[2], sel[1], sel[0]);
and (y[8], in, sel[3], ~sel[2], ~sel[1], ~sel[0]);
and (y[9], in, sel[3], ~sel[2], ~sel[1], sel[0]);
and (y[10], in, sel[3], ~sel[2], sel[1], ~sel[0]);
and (y[11], in, sel[3], ~sel[2], sel[1], sel[0]);
and (y[12], in, sel[3], sel[2], ~sel[1], ~sel[0]);
and (y[13], in, sel[3], sel[2], ~sel[1], sel[0]);
and (y[14], in, sel[3], sel[2], sel[1], ~sel[0]);
and (y[15], in, sel[3], sel[2], sel[1], sel[0]);

assign out = y;

endmodule
Output Waveform:

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