AVR MICROCONTROLLERS- AN OVERVIEW MPMC

INTRODUCTION
• The basic architecture of AVR was designed by two students of
Norwegian Institute of Technology (NTH), Alf-Egil Bogen
and Vegard Wollan, and then was bought and developed by
Atmel in 1996.
• The AVR stands for Advanced Virtual RISC, or Alf and
Vegard RISC.
• The AVR is an 8-bit RISC single-chip microcontroller with
Harvard architecture.
• Contains on chip FLASH , EEPROM, SDRAM memory and
buit in peripherals like ADC
TYPES
• tinyAVR- smallest version 8 bit, 8kB of internal FLASH, 512 bytes of
SRAM and EEPROM.
• megaAVR-high performance with hw multiplier, 256kB of internal FLASH
program memory and 8K SRAM and 4K EEPROM.
• XMEGA High performace with inbuilt DMA
• Application based AVR:
• Automotive AVR, CAN AVR, LCD AVR, Lighting AVR etc.
AVR PART NUMBERS
ARCHITECTURE • It has 8 bit ALU, 32 8 bit GP
registers, Stack Pointer, Program
Counter, Instruction Register,
Instruction Decoder and Status
and control registers.
• AVR allows pipelined architecture
( pre-fetch+execution)
• All 32 registers are connected to
ALU but 2 independent
registers can be accessed in a
single instruction
• Register access time= 1 clock
cycle
• 6 registers are used as 16 bit
Indirect Address Registers (X,Y
and Z)
FEATURES
 ON CHIP PERIPHERALS
-- On-board EEPROM for parameter settings;
--ADC
-- U(S)ART(s)
-- BOD (Brown-out detector , the power source provided to the VCC pin fluctuates, BOD circuit
compares VCC with BOD-Level and resets the chip if VCC falls below the BOD-Level)
-- Watchdog
-- Choice of clock sources
-- Low-power modes
-- SPI/I2C (SERIAL PERIPHERAL INTERFACE -full-duplex/INTER INTEGRATRED CIRCUIT-
half-duplex
communication protocol )
-- Enough SRAM
-- Choice of flash sizes within a family
-- Fairly powerful timers/counters
-- Lots of external interrupt sources
PIN DESCRIPTION
4 nos of 8 bit ports – PA, PB, PC and PD
3 interrupt pins-INT 0, 1 and 2
Asynchronous serial communication-RXD, TXD
External clock input/output during serial communication-XCK
Multiple device-Serial Peripheral Interface (SPI)-SS’,MOSI, MISO, SCK
One way communication-I2C- SCL (clock), SDA (Data)
8 analogs to digital channels- ADC0-ADC7
Timers. T0 , T1 ,TOSC1, TOSC2
PWM generation- OC0, OC1B, OC1A, OC2.
PWM pins for output- ICP1 (to capture the external input to calculate the frequency
and duty cycle of the external device.)
Internal Comparator- AN0 (non-inverted), AN1 (inverted)
JTAG to debug or to test the microcontrollers- TDI, TDO, TMS, TCK
Analog Ref and VCC- Aref, AVCC
Oscillator (internal 8MHz→ 16 MHz)- XTAL2, XTAL1
Power- VCC, GND, RESET- Reset’
 REGISTER ADDRESS MAP
• The I/O Registers are locations in
Data Memory which control
certain microcontroller functions.
• All of the data direction registers
and ports (e.g. DDRx and PORTx)
are located in the I/O Register
portion of Data Memory.
• Because they are needed so
often, there are special
instructions which allow quick
access and modification of the I/O
Registers.
CONT..
The following registers can be applied for specific use
• R1:R0 store the result of multiplication instruction
• R0 stores the data loaded from the program memory
• I/O registers – 64 8-bit registers
• Used in input/output instructions
• Status register (SREG) – A special I/O register
 STATUS REGISTER (SREG)
I T H S V N Z C

C= carry
Z=zero
N=negative; N is the most significant bit of the result.
V=overflow; Two’s Complement Overflow Flag
S=Sign; Exclusive OR between the N and V flag bits ( S = N ⊕V).
H=Half Carry
T=Bit Copy Storage (acts as source and destination for bit copy storage
instructions (BLD and BST)
I=Global Interrupt Enable (activates or deactivates interrupts) Used to enable and
disable interrupts. – 1: enabled. 0: disabled. This bit is cleared by hardware after
an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts
 RESET IN AVR
• Sources : Power on Reset, External Reset, Watchdog Reset, and Brownout Reset
• On reset all registers and ports are initialized.
• In order to know the source of reset the MCUCSR (MCU control and
status register) is used.
RSD RSD RSD RSD WDRF BORF EXTRF PORF

• Flag corresponding to specific RESET is set to indicate type of Reset.

• RSD→ Reserved
 STACK
• SP is 16 bit register (SPH+SPL)
• At reset SP=0000H
• Stack grows down
• Implemented in SRAM
• Stack to be initialized at 0060 for proper functioning
• PUSH=SP-1, store
• POP=retrieve, SP+1
ADDITION OF TWO 16BIT NOS
.include "m328pdef.inc"
.def num1L = r16 ; define lower byte of number 1 as r16 .def
num1H = r17 ; define upper byte of number 1 as r17 .def num2L =
r18 ; define lower byte of number 2 as r18 .def num2H = r19 ;
define upper byte of number 2 as r19 .cseg
.org 0x00
ldi num1L,0x34 ; load 0x34 into r16
ldi num1H,0x12 ; load 0x12 into r17
ldi num2L,0xCD ; load 0xCD into r18
ldi num2H,0xAB ; load 0xAB into r19
add num1L,num2L ; add lower bytes of number
adc num2H,num2H ; add upper bytes of number
loop: rjmp loop ; infinite loop
DATA TRANSFER INSTRUCTIONS

Immediate instructions only work with registers 16 through 31.

 LOGICAL INSTRUCTION

As with ldi, andi and ori only work on registers 16 through 31.
Example:
ldi r16,0x55 ; load 0x55 into r16
ldi r17,0x0F ; load 0x0F into r17
and r16,r17 ; mask the upper 4 bits of r16 (result = 0x05)
COMPLEMENT
ldi r16,0x55 ; load 0x55 into r16
com r16 ; one's complement of r16 (result = 0xAA)
******
ldi r16,5 ; load 5 into r16
neg r16 ; negate r16 (result = -5 = 0xFB)
ARITHMETIC
ADDITION
ldi r16,0x34 ; place lower byte of 0x1234 in r16
ldi r17,0x12 ; place upper byte of 0x1234 in r17
ldi r18,0xCD ; place lower byte of 0xABCD in r18
ldi r19,0xAB ; place upper byte of 0xABCD in r19
add r16,r18 ; compute sum of lower bytes (result = 0x01)
adc r17,r19 ; compute sum of upper bytes with carry
(result = 0xBE)
SUBTRACTION
ldi r16,0x01 ; place lower byte of 0xBE01 in r16
ldi r17,0xBE ; place upper byte of 0xBE01 in r17
ldi r18,0x34 ; place lower byte of 0x1234 in r18
ldi r19,0x12 ; place upper byte of 0x1234 in r19
sub r16,r18 ; subtract lower bytes (result = 0xCD)
sbc r17,r19 ; subtract upper bytes with carry (result = 0xAB)
*********
ldi r16,0x05 ; load 0x05 into register 16
sbi r16,0x05 ; subtract 5 from r16 (result = 0x00)
*** No adi available
ADD WORD
ldi r24,0x00 ; load 0x1000 into
ldi r25,0x10 ; registers r24:r25
adiw r24,0x0A ; add 0x0A to r24:r25 (result = 0x100A)
ldi XL,0x80 ; load 0x8080 into
ldi XH,0x80 ; X pointer
adiw X,1 ; increment X pointer (result = 0x80801)
FRACTIONAL MULTIPLICATION

ldi r16,0xC0 ; load r16 with 0xC0 (1.5)

ldi r17,0xA0 ; load r17 with 0xA0 (1.25)
fmul r16,r17 ; multiply r16 and r17 (r1:r0 = 0xF000 = 1.875)

fmul will only work with r16 through r23.

Output the result in r1 and r0
SHIFT/ ROTATE

ldi r16,0b10101010 ; load 1010101010 into r16

ldi r17,0b10101010 ; load 1010101010 into r17
lsl r16 ; shift r16 left (result = 01010100)
rol r17 ; shift r17 left and bring carry (result = 01010101)
BIT MANIPULATION

ldi r16,0x00 ; load 0x00 into r16

sbr r16,0x0F ; set lower 4 bits of r16 (result = 0x0F)
cbr r16,0x0F ; clear lower 4 bits of r16 (result = 0x00)
******
ser and clr are not
ser r16 ; set all bits in r16 (result = 0xFF) actual instructions
clr r16 ; clear all bits in r16 (result = 0x00) implemented in the
architecture, but are
Eqwt to provided by the
ldi r16,0xFF assembler as aliases
for other instructions.
eor r16,r16
SWAP
ldi r16,0x0F ; load 0x0F into r16
swap r16 ; swap nibbles of r16 (result = 0xF0)

****BCD addition
LED BLINK
#ifndef F_CPU
# define F_CPU 16000000UL // clock speed is 16MHz
#endif
#include <avr/io.h>
#include <util/delay.h>
int main(void)
{
DDRD = 0xFF; // declared port B as output
while(1) // initialize infinite while loop
{
PORTD = 0xFF; // turn on all LEDs of PORTB
_delay_ms(1000); // delay of one second
PORTD = 0x00; // turn off all LEDs of PORTB
_delay_ms(1000); // delay of one second
} // while loop end
} // main end
END OF SLIDES
SOURCE
8-bit AVR® Microcontrollers - Developer Help (microchipdeveloper.com)
AVR Tutorials - Working With Registers R0 - R31 (rjhcoding.com)
ATmega32 Microcontroller Pinout, Programming Examples and Features (microcontrollerslab.com)