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ELE 2213 Digital Circuits - Lab 9 - Synchronous Counters - Version 202230

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32 views

ELE 2213 Digital Circuits - Lab 9 - Synchronous Counters - Version 202230

Uploaded by

afnanofyouth
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab Experiment ELE 2213

ELE 2213 Digital Circuits

CLO-3 Analyze sequential logic circuits using logic symbols,


truth tables, and associated timing diagrams.

Lab #9 Synchronous Counters

Student Name
Student ID Number

Lab Manual modified in 202220


Lab Experiment #9 ELE 2213
THEORY
In asynchronous counter is formed with a series cascaded flip-flops. In a asynchronous counters, the
flip-flop output transition serves as a source for triggering other flip-flops. The first flip-flop is
triggered by the input pulses. The output of the flip-flops are trigger the clock of the next flip-flop.

In a synchronous counter, the clock pulses are applied to clock inputs of all flip-flops. Therefore each
flip- flop of the counter changes state at the same time. This advantage of this configuration is that
only one gate delay is required for the counter stages to change state.

PRIOR TO THE LAB SESSION

- Should be aware about Synchronous Counter


- Study the procedure for conducting the experiment in the lab.

OBJECTIVES
To construct 3 bit asynchronous and synchronous counter, and verify it with the NI ELVIS II.

EQUIPMENT/COMPONENTS R E Q U I R E D
- NI ELVIS II.
- 2 IC7476 (Dual J-K flip flop –ve edge triggered)
- Connecting wires

CIRCUIT DIAGRAM:
2 bit Synchronous counter

Figure 1:: synchronous Counter

Lab Manual modified in 202220


Lab Experiment #9 ELE 2213

Design circuit diagram and the timing diagram for 3-bit synchronous counter.

Circuit Diagram for 3-bit synchronous counter

Timing Diagram for 3-bit synchronous counter

PROCEDURE:

1. Connect the circuit as per the circuit diagram (a and b). Taking care to connect
the Vcc and gnd of respective chips.
2. Apply the input clock and verify the truth table and counter binary states.

TRUTH TABLE:

Table 1 Synchronous Counter

S.No: Binary states Decimal Value Practical states


verified

1. 000
2. 001

Lab Manual modified in 202220


Lab Experiment #9 ELE 2213
3. 010
4. 011
5. 100
6. 101
7. 110
8. 111

APPENDIX OF LAB 9

Given below are the pin diagram of the IC’s using in Lab 9

74LS76 IC – FLIP FLOP

Lab Manual modified in 202220

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