05/12/2022, 14:37 Quiz -IIa

Dashboard / My courses / 1154_CS F215_ECE F215_EEE F215_INSTR F215 / General / Quiz -IIa

Started on Sunday, 4 December 2022, 11:25 AM

State Finished
Completed on Sunday, 4 December 2022, 11:55 AM
Time taken 29 mins 47 secs
Grade 4.00 out of 10.00 (40%)

Question 1 Two D flip-flops are connected as a synchronous counter such that the state AB (B is LSB) goes through the
Correct sequence 00-01-11-10-00….. For this counter, the two D inputs DA and DB respectively are: Answer in the format
Mark 1.00 out of xy with no space in between.
1.00

BA' 

Question 2
A multiplier system is to be designed using a ROM, which multiplies the 3 bit number by number 3. What
Correct
minimum size ROM will be used? Give your answer in the format mxn without any spacing in between
Mark 1.00 out of
1.00 4x4 

Question 3
Given that a= 0xx0, b=101. What will be the output if each of the following conditions are tested in verilog
Incorrect
individually?
Mark 0.00 out of
1.00 (i) (a===b)

(ii) ( a!==b)

(iii) (a==b)

(iv) (a!=b)

Give you answer in the format as described without any space in between, for example if the outputs are (i) 1 (ii) 1
(iii) 1 (iv) 0, then write in a single line 1110.

0101 

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05/12/2022, 14:37 Quiz -IIa

Question 4
If the frequency of the clock applied to the mod 6 section of the 7492 counter IC is 15 kHz, what will be the
Incorrect
frequency at the 2nd LSB output ? Give your answer in KHz. Do not append the unit.
Mark 0.00 out of
1.00 3.75 

Question 5
A clock does not appear explicitly as input variable in a state diagram of sequential circuits. This
Correct
means......................
Mark 1.00 out of
1.00

Select one:
a. state transition occurs only during a clock edge 

b. state transition may occur at the edge or at the level of the clock pulse

c. A clock is not required as input to the circuit

d. state transition occurs at the level of the clock pulse

Your answer is correct.

The correct answer is: state transition occurs only during a clock edge

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05/12/2022, 14:37 Quiz -IIa

Question 6
For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is
Incorrect
ΔT.Which of the following waveforms correctly represents the output at Q1​?
Mark 0.00 out of
1.00

Select one:

a. 

b.

c.

d.

Your answer is incorrect.

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05/12/2022, 14:37 Quiz -IIa

The correct answer is:

Question 7 Identify the modulus and direction of the counter .................... If the modulus is 10 and direction UP, write the
Incorrect answer in the form: 10UP .
Mark 0.00 out of
1.00 8DOWN 

Question 8
The initial state of the sequential circuit given below is
Incorrect Q2Q1Q0 = 000. The next three states will be.......? Your answer should be in the form:
Mark 0.00 out of xxx,yyy,zzz with no spacing in between.
1.00

111,000,111 

Question 9
A 100 KHz clock signal having a duty cycle of 30% is used to the clock the 4 bit binary synchronous counter. What
Incorrect
will be the frequency in KHz and duty cycle of the 2nd MSB output of the counter? Give your answer in the
Mark 0.00 out of
format: x y
1.00
where x is the frequency in kHz and y is the duty cycle in %. Do not append the unit or % symbol. There should be
single spacing between the two .

55 

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05/12/2022, 14:37 Quiz -IIa

Question 10
The following binary values were applied to the X and Y inputs of NAND latch shown in the figure in the sequence
Correct
indicated below:
Mark 1.00 out of
1.00 X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1

The corresponding stable P Q, output will be

Select one:
a.
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1

b.
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1 

c.
P = 1, Q = 0; P = 0, Q = 1 or P = 0, Q = 1; P = 0, Q = 1

d.
P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1

Your answer is correct.

The correct answer is:

P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1

◄ Batch -2 seating arrangement Jump to... Quiz II-b ►

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