Lec2 Assembly
Lec2 Assembly
Slide rule
Abacus
Curta (1948)
Pascaline
Vacuum Tube
Half Adder
Memory ?!!
Punched Card
C++ language
cout<<(A*B+C)
Games, Graphics
Program execution:
Interpretation
Compilation (Translation)
Every CPU has a built-in interpreter for its own "instruction set"
(ISA, Instruction Set Architecture; the binary language it is
programmed in)
High Level
Level 4
Language
Instruction Set
Level 2 Architecture (ISA)
• C Compiler (translator)
Microsoft C
Compiler
• Produces assembly language (object file)
•Programmer
JEdit •Produces a Java Program
37 = 100101
10/15/2014 Assemly Language-Lecture 1 29
Binary Addition
Same as normal addition, from right to left
0 + 0 = 0
0 + 1 = 1, 1 + 0 = 1
1 + 1 = 0 with a carry of 1
carry: 1
0 0 0 0 0 1 0 0 (4)
+ 0 0 0 0 0 1 1 1 (7)
0 0 0 0 1 0 1 1 (11)
bit position: 7 6 5 4 3 2 1 0
word 16
doubleword 32
quadword 64
Byte = 8 Bits
Word = 2 Bytes
Doubleword = 2 Words = 4 Bytes
Quadword = 4 Words = 8 Bytes = 64 Bits = Max value for a 64 bit CPU
1 1 1 1 0 1 1 0
Negative
0 0 0 0 1 0 1 0 Positive
ANSI (0 – 255)
Unicode (0 – 65,535)
Null-terminated String
Array of characters followed by a null byte
NOT
AND
OR
Two-input multiplexer
S
X
mux Z
Y
data bus
registers
I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2
ALU CU clock
control bus
address bus
5
5
Clock
Synchronizes all CPU and bus operations
one cycle
6
Instruction Execution Cycle
Fetch instruction
Decode
Fetch operands
Memory registers (internal)
Execute
Store output
7
Reading from Memory
Multiple cycles are required when reading from memory, because it
responds much more slowly than the CPU
CLK
address placed on address bus
Address
ADDR
Read Line (RD) set low (0)
RD
CPU waits one cycle for memory
Data
to respond DATA
Read Line (RD) goes to 1, indicating that the data is on the data bus
8
Cache Memory
High‐speed expensive static RAM both inside and outside
the CPU
9
Multitasking
OS can run multiple programs at the same time
10