SRM Institute of Science and Technology BATCH 1

College of Engineering and Technology SET - A

DEPARTMENT OF ECE
SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamil Nadu
Academic Year: 2024-2025 (ODD)

Test: CLAT- 1 Date: 23.08.2024

Course Code & Title: 21ECC303T VLSI DESIGN TECHNOLOGY Duration: – 9.40 am
Year & Sem & Dept: III/V/ECE Max. Marks: 50

Course Articulation Matrix:

21ECC303T VLSI DESIGN TECHNOLOGY Program Outcomes (POs)
Graduate Attributes PSO
COs Course Outcomes (COs) 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3

Design and implement digital circuits using

1 - 2 3 - - - - - - - - - 2 - -
Verilog HDL with different abstract levels.
Examine the characteristics of MOS transistors
2 - 3 - - - - - - - - - - - - -
and Analyze CMOS inverter
Explain how the VLSI subsystem components
adders and multipliers to address the design of
3 - 2 3 - - - - - - - - - - 2 -
data path subsystem and other complex logic
gates design using different logic styles.
Explain how the transistors are built, and learn
the various process of fabrication techniques
4 - 3 1 - - - - - - - - - 2 - -
such as lithography, etching, polysilicon,
diffusion, ion implantation and metallization
To learn the various VLSI process simulation
5 - 2 2 - - - - - - - - - 2 - -
and integration

Part – A (10 x1 = 10 Marks)

Q. No Questions Marks BL CO PO
If A=1’b1; B=2’b00; C=2’b10 and D=3’b110 the result of Y={3{A},2{B},C} is
(A) 101
1 (B) 1010001111 1 2 1 2
(C)1111111111
(D) 111000010
Let data1=56; data2=89; What will be the output after execution of the statement
$display ("Result for data(%0d)===Result for data(%0d) : %0d", data1, data2,
data1===data2); What will be the output after the execution of the function
2 (A) Result for data(56)===Result for data(89) : 0 1 3 1 3
(B) Result for data(56)===Result for data(89) : 1
(C) Infinjte loop
(D) Error
The symbol used in User Defined Primitive (01) or (0x) or (x1) or (z1) stands for
(A) Falling edge including x
3 (B) Two input values 1 2 1 3
(C) Rising edge including x and z
(D) Unknown inputs
module and_data(a,b,y);
4 input a,b; 1 4 1 3
output y;
 y=a&b;
endmodule;

Will the code work? If not, which line might have an error
(A) Line 1
(B) Line 3
(C) Line 4
(D) The code will work

5 1 3 1 2

Which of the following options are true with respect to the block given above
(A) A1, B1, C1, B1, A0 are inputs and S1 is a wire
(B) A1, B1, C0, B1, A0 are inputs and C1 is a wire
(C) A1, B1, C1, B1, A0 are inputs and S1 is a wire
(D) A1, B1, C1, B1, A0 are inputs and S0 is a wire

Let the VDS of an n-channel MOSFET be a positive voltage and VGS is also positive.
What type of carriers will be induced at the surface of the MOSFET
A) Negative charge carriers
6 1 2 2 2
B) Positive charge carriers
C) No carriers at the surface
D) Surface will be neutral
The MOSFET reaches the threshold voltage when the surface potential is
A) Very high
7 B) Same as the Fermi potential 1 2 2 2
C) Twice the Fermi potential
D) Zero
The non ideality of channel length modulation has the following effect
A) Reduces the threshold voltage
8 B) Increases the threshold voltage 1 2 2 2
C) Causes the drain current to decrease
D) Causes the drain current to increase
A MOS capacitor with P substrate is in accumulation mode. What will be the charges
in the surface of the substrate
A) Positive
9 1 2 2 2
B) Negative
C) Neutral
D)No mobile charge
When VGS> VT, the MOSFET will be operating in
A) Cutoff or Saturation region
10 B) Accumulation or Inversion region 1 2 2 2
C) Cutoff or Linear region
D) Linear or Saturation region
PART B
Section B1: (2 x 4 = 8 Marks) Answer any two questions
Write the primitive for any multiplexer using Verilog
11 4 3 1 2
primitive mux (out, sel, a, b);
output out;
 input sel, a, b;
table
//sel a b out
0 1 ? : 1;
0 0 ? : 0;
1 ? 0 : 0;
1 ? 1 : 1;
x 0 0 : 0;
x 1 1 : 1;
endtable

endprimitive
Differentiate between the logical, relational and equality operators with necessary
examples Any 4 differences

12 4 3 1 3

Give the differences between blocking and non-blocking statements in Verilog

Any 4 differences

13 4 3 1 3

Section B2: (2 x 4 = 8 Marks) Answer any two questions

What are the main electric fields under which the MOSFET operates. Give the
necessary conditions to check whether the MOSFET is operating in linear or active
regions?
14 Main electric fields under which the MOSFET operates-VGS, VDS (1 mark) 4 3 2 2
Necessary conditions (3 marks)

Linear region
 VGS > VT
VGS > VGD
VGD > VT

Saturation region
VGS > VT
VGS < VGD
VGD < VT

Which MOS parameter is affected by the sub threshold conduction. Explain in detail
with necessary characteristics

The drain current Id (1 mark)

Characteristics (2 marks)
Explanation (1 mark)

15 4 3 2 2

i) What are the main components of the threshold voltage? Explain each
component in detail.

16 2+2 2 2 2

ii) Explain the effect of Fermi potential on the threshold voltage

When the MOSFET reaches the inversion region, the Fermi potential will be
twice.
The threshold voltage is said to be reached when the inversion region is reached

PART C (2 X 12 = 24 Marks) Either or Choice

a) Explain in detail any 6 lexical conventions used in Verilog with necessary

examples

17 6+6 3 1 2

3. Number specifications: Sized and Unsized

 4.Identifiers and keywords
5.Value sets in Verilog

b) Write the Verilog code for a 3 by 8 decoder in the behavioral and dataflow
abstraction
Behavioral-ANY LOOP can be used
module decoder3_to_8( in,out, en);
input [2:0] in;
input en;
output [7:0] out;
reg [7:0] out;

always @( in or en)
begin
if (en)
begin
out=8'd0;
case (in)
3'b000: out[0]=1'b1;
3'b001: out[1]=1'b1;
3'b010: out[2]=1'b1;
3'b011: out[3]=1'b1;
3'b100: out[4]=1'b1;
3'b101: out[5]=1'b1;
3'b110: out[6]=1'b1;
3'b111: out[7]=1'b1;
default: out=8'd0;
endcase
end
else
out=8'd0;
end
endmodule

Dataflow : Any type of program can be accepted if it is dataflow

module decoder_3to8(
input [2:0] a,
output [7:0] d );
assign d[0]=(~a[2])&(~a[1])&(~a[0]);
assign d[1]=(~a[2])&(~a[1])&(a[0]);
assign d[2]=(~a[2])&(a[1])&(~a[0]);
assign d[3]=(~a[2])&(a[1])&(a[0]);
assign d[4]=(a[2])&(~a[1])&(~a[0]);
assign d[5]=(a[2])&(~a[1])&(a[0]);
assign d[6]=(a[2])&(a[1])&(~a[0]);
assign d[7]=(a[2])&(a[1])&(a[0]);
endmodule

a) Draw the switch level representation of the equation

Y=(AB + CD+ E)’ and write the Verilog code for it
12 4 1 3
Logic diagram 2 marks
 Program 4 marks
module cmos_equation(inout a,b,c,d,e, output y);
supply1 vdd;
supply0 gnd;
wire y1,y2,y3,y4;
pmos p1(y1,vdd,c);
pmos p2(y1,vdd,d);
pmos p3(y2,y1,a);
pmos p4(y2,y1,b);
pmos p5(y,y2,e);

nmos n1(y,y3,a);
nmos n2(y3,gnd,b);
nmos n3(y,y4,c);
nmos n4(y4,gnd,d);
nmos n5(y,gnd,e);
endmodule

b) Write the gate level representation of a full subtractor with necessary

diagrams
Method 1-ANY OTHER SUITABLE METHOD CAN ALSO BE USED
module full_subtractor(
input a,
input b,
input c,
output diff
output borr);
wire x,n2,z,n1;
xor s1(x,a,b);
not s3(n2,x);
not s4(n1,c);
 and s5(y,n1,b);
xor s2(diff,a,x);
and s6(z,n2,a);
or (borr,y,z);

endmodule

Method 2

module full_subtractor(A, B, Bin, D, Bout);

input A, B, Bin;
output D, Bout;
wire p, q, r;
half_subtractor u4(A, B, p, q);
half_subtractor u5(p, Bin, D, r);
or_gate u6(q, r, Bout);
endmodule

module half_subtractor(a4, b4, c4, d4); // module declaration

input a4, b4; // input variable
output c4, d4; // output variable
wire x; // temporary variable
xor_gate u1(a4, b4, c4); // XOR gate instance u1; a4, b4 will act as input and c4 will
be the output
and_gate u2(x, b4, d4); // AND gate instance u2; x, b4 will act as input and d4 will be
the output
not_gate u3(a4, x); // NOT gate instance u3; a4 will act as input and x will be the
output
endmodule

Explain the non idealities which occur due to the following causes and also explain
their effect on the characteristics with necessary equations
4 marks for each effect
a) Vertical field strength is high- Mobility degradation
18 Let Vertical field strength be high 12 2 2 2

lower than expected

b) A large positive VDS- Drain Induced barrier lowering

 A positive reduces
= -ɳ
c) Gate oxide has less thickness
Tunneling of carriers through the gate oxide
Tunneling drops off exponentially with gate oxide thickness

a) Draw and explain the characteristics of the N-channel enhancement MOSFET

and explain the accumulation, depletion and inversion regions of operation

Characteristics of N-channel MOSFET with explanation (2 marks)

Accumalation region ( 1 mark)

Occurs when VGS is negative
Positive charges acculamate at the surface
g 4 2 2

Depletion region (1 mark)

VGS is small and is > Vt
Surface is depleted
 Inversion region (2 marks)
VGS is big and is > Vt
Surface is inverted

b) Consider an ideal long channel nMOSFET (enhancement-mode) with gate

length 10 µm and width 100 µm. The product of electron mobility (µm n) and
oxide capacitance per unit area (Cox) is µnCox = 1 mA/V2. The threshold
voltage of the transistor is 1 V. For a gate-to-source voltage VGS = [2 − sin(2t)]
V and drain-to source voltage VDS = 1 V (substrate connected to the source)
find the maximum value of the drain-to-source current.
Finding out the region of operation 3 marks
Current equation 3 marks

Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions

 CO Coverage (%)

BL Coverage (%)
100
80
100
60 80
40 60
20 40
20
0
0
CO1 CO2 CO3 CO4 CO5 BL-1 BL-2 BL-3 BL-4 BL-5

Approved by the Course Coordinator Signature of the Question paper setter

Evaluation Sheet
Name of the Student: Register No.:
Part- A – Section A1 (3 x 4= 12 Marks)
Q. No CO PO Maximum Marks Total
Marks Obtained

1 CO1 PO2 1
2 CO1 PO2 1
3 CO1 PO2 1
4 CO1 PO2 1
5 CO1 PO2 1
6 CO2 PO3 1
7 CO2 PO3 1
8 CO2 PO3 1
9 CO2 PO3 1
10 CO2 PO3 1
Part- B – Section B1 (2 x 4= 8 Marks)
11 CO1 PO2 4
12 CO1 PO2 4
13 CO1 PO2 4
Part- B – Section B2 (2 x 4= 8 Marks)
14 CO2 PO3 4
15 CO2 PO3 4
16 CO2 PO3 4
Part- C (2 x 12= 24 Marks)
17 a CO1 PO2 12
17 b CO1 PO2 12
18 a CO2 PO3 12
18 b CO2 PO3 12

Consolidated Marks:
PO Maximum Marks
Marks Obtained
 CO Maximum Marks 2 25
Marks Obtained 3 25
1 25 Total 50
2 25
Total 50

Signature of Course Teacher

Signature of the Course Coordinator Signature of the Academic Advisor