VEMU INSTITUTE OF TECHNOLOGY

P.KOTHAKOTA, NEAR PAKALA, CHITTOOR-517112

(Approved by AICTE, New Delhi & Permanently Affiliated to JNTUA, Accredited by NAAC,
Recognised under 2(F) &12(B)of UGC Act 1956,An ISO 9001:2015 certified Institute)

 NAME: S VIDYA

 SUBJECT: DLD (20A04303T)

 REGULATION: R20
 BINARY NUMBER SYSTEM
◦ BINARY NUMBERS
◦ OCTAL NUMBERS
◦ HEXA DECIMAL NUMBERS
◦ NUMBER BASE CONVERSIONS
◦ COMPLIMENTS
◦ SIGNED BINARY NUMBERS
◦ BINARY CODES
 Binary logic and Gates
 Boolean Algebra
◦ Basic Properties
◦ Algebraic Manipulation
 Standard and Canonical Forms
◦ Minterms and Maxterms (Canonical forms)
◦ SOP and POS (Standard forms)
 The decimal system is the base-10 system that we use every day.
 A number, say 6357, represented in the base-10 system consists of multiple ordered
digits. (In other words, digits are normally combined together in groups to create
larger numbers.)
 A digit is a single place that can hold numerical values between 0 and 9 (10 different
values).
 For example, 6,357 has four digits.

 It is understood that in the number 6,357,

◦ the 7 is filling the "1s place,"
◦ while the 5 is filling the 10s place,
◦ the 3 is filling the 100s place
◦ and the 6 is filling the 1,000s place.

 So you could express 6,357 this way if you want to be explicit:

(6 * 1000) + (3 * 100) + (5 * 10) + (7 * 1)
= 6000 + 300 + 50 + 7
= 6357
 What you can see from this expression is that each digit is a placeholder for the
power of the index of that placeholder of base 10, starting from the least
significant digit with 10 raised to the power of zero (i.e. counting from the
rightmost digit).
 But why do we human beings use 10 based number system?
 The most commonly accepted explanation is that our base-10 number system was
adopted by our ancestors most likely because we have 10 fingers.
 Interestingly enough, maybe that is why digit in English also means a finger or toe.
 Computers happen to operate using the base-2 number system, also
known as the binary number system, just like the base-10 number
system is known as the decimal number system to human beings
 Modern computers use binary number system, in which there are only
zeros and ones. (Only two symbols)
 A “bit” to binary is similar a “digit” to a decimal information. (Again,
the easiest way to understand bits is to compare them to something
you know: digits.)
 A bit has a single binary value, either 0 or 1.
 Binary is a base two system which works just like our decimal system.
 Considering the decimal number system, it has a set of values which
range from 0 to 9.
 The binary number system is base 2 and therefore requires only two
digits, 0 and 1.
 The binary number system uses binary digits (bits) in place of decimal
digits.
 A binary number is composed of only 0s and 1s, like this: 1011.

 How do you figure out what the value of the binary number 1011 is in
decimal world?
 0=0
 1=1
 2 = 10
 3 = 11
 4 = 100
 5 = 101
 6 = 110
 7 = 111
 8 = 1000
 9 = 1001
 10 = 1010
 11 = 1011
 12 = 1100
 Keep dividing by 2
 Ex 2 : 23710
237 / 2 = 118 Remainder 1----------------------------------------
--------------|
118 / 2 = 59 Remainder 0----------------------------------------
-----------| |
59 / 2 = 29 Remainder 1----------------------------------------
--------| | |
29 / 2 = 14 Remainder 1----------------------------------------
--------| | |
14 / 2 = 7 Remainder 0----------------------------------------
-----| | | |
7 / 2 =3 Remainder 1----------------------------------------
--| | | | |
3/ 2=1 Remainder 1-----------------------------------| |
| | | | |
1/ 2=0 Remainder 1--------------------------------| | | |
| | | |

1 1 1 0 1 1 0 1
 Look at adder in binary and decimal
3
+3
=6
6
11
+ 11
= (carry) which is 6 in decimal.
110
 Although not a problem internally, long binary number seems a
problem to display in some situations. A common practice to
solve this problem is to use hexadecimal to represent Binary
numbers more compactly externally.
 The hexadecimal system is base 16. Therefore, it requires 16
different symbols. The values 0 through 9 are used, along with
the letters A through F, which represent the decimal values 10
through 15.
0..9, A, B, C, D, E, F
0..9, 10, 11, 12,13, 14, 15
 The Octal system is base 8. Therefore it requires 8 digits. The values 0 through 7 are
used.

 Octal to hexadecimal conversion, or visa versa, is most easily performed by first

converting to binary.
 A binary number is converted to octal by grouping of 3 bits

1 1 0 1 0 1 1 0 1-----------655
 The binary, hexadecimal (hex) and octal system
share one common feature – they are all based on
powers of 2.
 Each digit in the hex system is equivalent to a four-
digit binary number and each digit in the octal
system is equivalent to a 3-digit binary number.
 Consider a system of 3 input signals (variables) x, y, & z.
 A term which ANDs all input variables, either in the true or complement form, is
called a minterm.
 Thus, the considered 3-input system has 8 minterms, namely:

 Each minterm equals 1 at exactly one particular input combination and is equal to 0
at all other combinations
 Thus, for example, is always equal to 0 except for the input combination xyz
= 000, where it is equal to 1.
 Accordingly, the minterm is referred to as m0.
 In general, minterms are designated mi, where i corresponds the input combination
at which this minterm is equal to 1.
 For the 3-input system under consideration, the
number of possible input combinations is 23, or
8. This means that the system has a total of 8
minterms as follows:
 In general, for n-input variables, the number of minterms = the total
number of possible input combinations = 2n.
 A minterm = 0 at all input combinations except one where the
minterm = 1.
 Example: What is the number of minterms for a function with 5 input
variables?
◦ Number of minterms = 25 =32 minterms.
 Consider a circuit of 3 input signals (variables) x, y, & z.
 A term which ORs all input variables, either in the true or
complement form, is called a Maxterm.
 With 3-input variables, the system under consideration has a total
of 8 Maxterms, namely:

 Each Maxterm equals 0 at exactly one of the 8 possible input

combinations and is equal to 1 at all other combinations.
◦ For example, (x + y + z) equals 1 at all input combinations
except for the combination xyz = 000, where it is equal to 0.
◦ Accordingly, the Maxterm (x + y + z) is referred to as M0.
 In general, Maxterms are designated Mi, where i
corresponds to the input combination at which this
Maxterm is equal to 0.
 For the 3-input system, the number of possible
input combinations is 23, or 8. This means that the
system has a total of 8 Maxterms as follows:
 For n-input variables, the number of Maxterms =
the total number of possible input combinations =
2n.
 A Maxterm = 1 at all input combinations except one
where the Maxterm = 0.
 Using De-Morgan’s theorem, or truth tables, it can
be easily shown that:
 Consider the function F defined by the
shown truth table:
 Now let’s rewrite the table, with few
added columns.
◦ A column i indicating the input
combination
◦ Four columns of minterms m2, m4, m5
and m7
◦ One last column OR-ing the above
minterms (m2+m4+m5+m7)
 From this table, we can clearly see that F
= m2+m4+m5+m7
 In general, Any function can be expressed by OR-ing all minterms (mi)
corresponding to input combinations (i) at which the function has a value of 1.
 The resulting expression is commonly referred to as the SUM of minterms and is
typically expressed as F = Σ(2, 4, 5, 7), where Σ indicates OR-ing of the indicated
minterms. Thus, F = Σ(2, 4, 5, 7) = (m2 + m4 + m5 + m7)
 Consider the example with F and F`.
 The truth table of F` shows that F`
equals 1 at i = 0, 1, 3 and 6, then,
◦ F` = m0 + m1 + m3 + m6,
◦ F` = Σ(0, 1, 3, 6),
◦ F = Σ(2, 4, 5, 7)
 The sum of minterms expression of F`
contains all minterms that do not appear
in the sum of minterms expression of F.
 Using De-Morgan theorem on equation:

 This form is designated as the Product of Maxterms and is expressed

using the Π symbol, which is used to designate product in regular
algebra, but is used to designate AND-ing in Boolean algebra.
 F` = Π (2, 4, 5, 7) = M2. M4. M5. M7
 F` = Σ(0, 1, 3, 6) = Π (2, 4, 5, 7)
 Any function can be expressed both as a sum of minterms (Σ mi) and as a product of maxterms (Π
Mj).
 The product of maxterms expression (Π Mj) of F contains all maxterms Mj (∀ j ≠ i) that do not appear
in the sum of minterms expression of F.
 The sum of minterms expression of F` contains all minterms that do not appear in the sum of
minterms expression of F.
 This is true for all complementary functions. Thus, each of the 2 n minterms will appear either in the
sum of minterms expression of F or the sum of minterms expression of F` but not both.
 The product of maxterms expression of F` contains all maxterms that do not appear
in the product of maxterms expression of F.
 This is true for all complementary functions. Thus, each of the 2n maxterms will
appear either in the product of maxterms expression of F or the product of maxterms
expression of F` but not both.
 Example: Given that F (a, b, c, d) = Σ(0, 1, 2, 4, 5, 7), derive the product of maxterms expression of F
and the two standard form expressions of F`.
 Since the system has 4 input variables (a, b, c & d), the number of minterms and maxterms = 24= 16
 F (a, b, c, d) = Σ(0, 1, 2, 4, 5, 7)
 F = Π (3, 6, 8, 9, 10, 11, 12, 13, 14, 15)
 F` = Σ (3, 6, 8, 9, 10, 11, 12, 13, 14, 15).
 F` = Π (0, 1, 2, 4, 5, 7)
 Let F(A,B,C)= A B + A’ C, express F as a sum of minterms
 F(A,B,C)= A B (C+C’) + A’ C (B+B’)
 = ABC + ABC’ + A’BC + A’B’C
 = Σ(1, 3, 6, 7)
 Short Cut Method:
◦ A B = 1 1 - This gives us the input combinations 110 and 111 which correspond to m6 and m7
◦ A’ C = 0 – 1 This gives us the input combinations 001and 011 which correspond to m1 and m3
 The AND operation on two functions corresponds to the intersection of the two sets of minterms of the functions
 The OR operation on two functions corresponds to the union of the two sets of minterms of the functions
 Example
◦ Let F(A,B,C)=Σm(1, 3, 6, 7) and G(A,B,C)=Σm(0,1, 2, 4,6, 7)
◦ F . G = Σm(1, 6, 7)
◦ F + G = Σm(0,1, 2, 3, 4,6, 7)
◦ F’ . G = ?
◦ F’ = Σm(0, 2, 4, 5)
◦ F . G = Σm(0, 2, 4)
 The sum of minterms and the product of maxterms forms of
Boolean expressions are known as canonical forms.
 Canonical form means that all equivalent functions will have a
unique and equal representation.
 Two functions are equal if and only if they have the same sum of
minterms and the same product of maxterms.
 Example:
◦ Are the functions F1 = a' b' + a c + b c ' and
F2 = a' c' + a b + b' c Equal?
◦ F1 = a' b' + a c + b c ' = Σm(0, 1, 2 , 5, 6, 7)
◦ F2 = a' c' + a b + b' c = Σm(0, 1, 2 , 5, 6, 7)
◦ They are equal as they have the same set of minterms.
 A product term is a term with ANDed literals. Thus, AB, A’B, A’CD are all product
terms.
 A minterm is a special case of a product term where all input variables appear in the
product term either in the true or complement form.
 A sum term is a term with ORed literals. Thus, (A+B), (A’+B), (A’+C+D) are all sum
terms.
 A maxterm is a special case of a sum term where all input variables, either in the
true or complement form, are ORed together.
 Boolean functions can generally be expressed in the form of a Sum of
Products (SOP) or in the form of a Product of Sums (POS).
 The sum of minterms form is a special case of the SOP form where all
product terms are minterms.
 The product of maxterms form is a special case of the POS form
where all sum terms are maxterms.
 The SOP and POS forms are Standard forms for representing Boolean
functions.
 Sum of Products Expressions (SOP):
 Any SOP expression can be implemented in 2-levels of gates.
 The first level consists of a number of AND gates which equals the number
of product terms in the expression.
 Each AND gate implements one of the product terms in the expression.
 The second level consists of a SINGLE OR gate whose number of inputs
equals the number of product terms in the expression.
 Example: Implement the following SOP function
F = XZ + Y`Z + X`YZ
 Product of Sums Expression (POS):
 Any POS expression can be implemented in 2-levels of gates.
 The first level consists of a number of OR gates which equals the
number of sum terms in the expression.
 Each gate implements one of the sum terms in the expression.
 The second level consists of a SINGLE AND gate whose number of
inputs equals the number of sum terms.
 Example: Implement the following POS function
F = (X+Z )(Y`+Z)(X`+Y+Z )
 Deals with binary variables that take 2 discrete values (0 and 1), and with logic
operations
 Three basic logic operations:
◦ AND, OR, NOT
 Binary/logic variables are typically represented as letters: A,B,C,…,X,Y,Z

Boolean Algebra 2023/2/28

F(vars) = expression

Operators ( +, •, ‘ )
Variables

Constants( 0, 1 )
set of binary
Groupings (parenthesis)
variables
Example: F(a,b) = a’•b + b’
G(x,y,z) = x•(y+z’)

Boolean Algebra 2023/2/28

 George Boole (1815-1864): “An investigation of the laws of thought”
 Terminology:
◦ Literal: A variable or its complement
◦ Product term: literals connected by •
◦ Sum term: literals connected by +

Boolean Algebra 2023/2/28

 1854: Logical algebra was published by George Boole  known today as “Boolean
Algebra”
 It’s a convenient way and systematic way of expressing and analyzing the operation
of logic circuits.
 1938: Claude Shannon was the first to apply Boole’s work to the analysis and
design of logic circuits.
 Variable – a symbol used to represent a logical quantity.
 Complement – the inverse of a variable and is indicated by a bar over the variable.
 Literal – a variable or the complement of a variable.
 Boolean addition is equivalent to the OR operation

1+1 = 1 1+0 = 1 0+1 = 1 0+0 = 0

A sum term is produced by an OR operation with no AND ops

involved.
i.e. A  B, A  B , A  B  C , A  B  C  D
A sum term is equal to 1 when one or more of the literals in
the term are 1.
A sum term is equal to 0 only if each of the literals is 0.
 Boolean multiplication is equivalent to the AND operation

0·0 = 0 0·1 = 1·0 = 0 1·1 = 1

0

A product term is produced by an AND operation with no OR

ops involved.
i.e.
A product term is equal to 1 only if each of the literals in the
term is 1.
A product term is equal to 0 when one or more of the literals
are 0.
 The basic laws of Boolean algebra:
◦ The commutative laws
◦ The associative laws
◦ The distributive laws
 The commutative law of addition for two variables is
written as: A+B = B+A

 The commutative law of multiplication for two variables is

written as: AB = BA

B
A
B A+B
 A B+A

A
B
AB  B
A
BA
 The associative law of addition for 3 variables is written as: A+(B+C) = (A+B)+C

 The associative
A
law of multiplication for A3 variables
A+B
is written as: A(BC) = (AB)C
B
A+(B+C)
 B
(A+B)+C
C B+C C


A A AB
A(BC)
B B
(AB)C
C BC C
  The distributive law is written for 3 variables as follows:
A(B+C) = AB + AC

B A AB
B+C
B
C
A
X  A
X

C AC

X=A(B+C) X=AB+AC
1. A  0  A 7. A  A  A
2. A  1  1 8. A  A  0
3. A  0  0 9. A  A
4. A  1  A 10. A  AB  A
5. A  A  A 11. A  A B  A  B
6. A  A  1 12.( A  B )( A  C )  A  BC
___________________________________________________________
A, B, and C can represent a single variable or a combination of variables.
 DeMorgan’s theorems provide mathematical verification of:
◦ the equivalency of the NAND and negative-OR gates
◦ the equivalency of the NOR and negative-AND gates.
 The complement of two or more NAND Negative-OR
ANDed variables is equivalent to the
OR of the complements of the
individual variables.
X Y  X  Y

 The complement of two or more ORed

variables is equivalent to the AND of
NOR Negative-AND
the complements of the individual
variables.
X  Y  X Y
 Apply DeMorgan’s theorems to the expressions:

X Y  Z
X Y  Z
X Y  Z
W  X Y  Z
 Apply DeMorgan’s theorems to the expressions:

( A  B  C)D
ABC  DEF
AB  C D  EF
A  BC  D( E  F )
 Boolean algebra provides a concise way to express the operation of a logic circuit
formed by a combination of logic gatese
 So that the output can be determined for various combinations of input values.
 To derive the Boolean expression for a given logic circuit, begin at the left-most
inputs and work toward the final output, writing the expression for each gate.

C CD
D
B+CD
B

A(B+CD)
A
 Once the Boolean expression for a given logic circuit has been determined, a truth
table that shows the output for all possible values of the input variables can be
developed.
◦ Let’s take the previous circuit as the example:
A(B+CD)
◦ There are four variables, hence 16 (24) combinations of values are possible.
 Evaluating the expression
◦ To evaluate the expression A(B+CD), first find the values of the variables that
make the expression equal to 1 (using the rules for Boolean add & mult).
◦ In this case, the expression equals 1 only if A=1 and B+CD=1 because
A(B+CD) = 1·1 = 1
 Evaluating the expression (cont’)
◦ Now, determine when B+CD term equals 1.
◦ The term B+CD=1 if either B=1 or CD=1 or if both B and CD equal
1 because
B+CD = 1+0 = 1
B+CD = 0+1 = 1
B+CD = 1+1 = 1
 The term CD=1 only if C=1 and D=1
 Evaluating the expression (cont’)
◦ Summary:
◦ A(B+CD)=1
 When A=1 and B=1 regardless of the values of C and D
 When A=1 and C=1 and D=1 regardless of the value of B
◦ The expression A(B+CD)=0 for all other value combinations of the variables.
 INPUTS
INPUTS OUTPUT
OUTPUT
 Putting the results in truth table AA BB CC DD A(B+CD)
A(B+CD)
format 00 00 00 00 0
00 00 00 11 0

A(B+CD)=1 00 00 11 00 0
00 00 11 11 0
00 11 00 00 0
When A=1 and B=1 00 11 00 11 0
regardless of the 00 11 11 00 0

values of C and D 00 11 11 11 0
11 00 00 00 0
11 00 00 11 0
When A=1 and C=1 and 11 00 11 00 0

D=1 regardless of the 11 00 11 11 1

11 11 00 00 11
value of B 11 11 00 11 1
11 11 11 00 11
11 11 11 11 11
Let X: boolean variable, 0,1: constants

1. X + 0 = X -- Zero Axiom
2. X • 1 = X -- Unit Axiom
3. X + 1 = 1 -- Unit Property
4. X • 0 = 0 -- Zero Property
Let X: boolean variable, 0,1: constants

5. X + X = X -- Idepotence
6. X • X = X -- Idepotence
7. X + X’ = 1 -- Complement
8. X • X’ = 0 -- Complement
9. (X’)’ = X -- Involution
 The dual of an expression is obtained by exchanging (• and +),
and (1 and 0) in it, provided that the precedence of operations
is not changed.
 Cannot exchange x with x’
 Example:
◦ Find H(x,y,z), the dual of F(x,y,z) = x’yz’ + x’y’z
◦ H = (x’+y+z’) (x’+y’+ z)
With respect to duality, Identities 1 – 8 have the following
relationship:

1. X + 0 = X 2. X • 1 = X (dual of 1)
3. X + 1 = 1 4. X • 0 = 0 (dual of 3)
5. X + X = X 6. X • X = X (dual of 5)
7. X + X’ = 1 8. X • X’ = 0 (dual of 8)
 Let X,Y, and Z: boolean variables

10. X + Y = Y + X 11. X • Y = Y • X -- Commutative

12. X + (Y+Z) = (X+Y) + Z 13. X•(Y•Z) = (X•Y)•Z -- Associative
14. X•(Y+Z) = X•Y + X•Z 15. X+(Y•Z) = (X+Y) • (X+Z) -- Distributive
16. (X + Y)’ = X’ • Y’ 17. (X • Y)’ = X’ + Y’
-- DeMorgan’s In general,
( X1 + X2 + … + Xn )’ = X1’•X2’• … •Xn’, and
( X1•X2•… •Xn )’ = X1’ + X2’ + … + Xn’
1. x + x•y = x
2. x•(x+y) = x (dual)
 Proof:
x + x•y = x•1 + x•y
= x•(1+y)
= x•1
=x
QED (2 true by duality, why?)

Boolean Algebra 2023/2/28

1. x + x•y = x is true, so (x + x•y)’=x’
2. (x + x•y)’=x’•(x’+y’)
3. x’•(x’+y’) =x’
4. Let X=x’, Y=y’
5. X•(X+Y) =X, which is the dual of x + x•y = x.
6. The above process can be applied to any formula. So if a
formula is valid, then its dual must also be valid.
7. Proving one formula also proves its dual.

Boolean Algebra 2023/2/28

1. xy + x’z + yz = xy + x’z
2. (x+y)•(x’+z)•(y+z) = (x+y)•(x’+z) -- (dual)
 Proof:
xy + x’z + yz = xy + x’z + (x+x’)yz
= xy + x’z + xyz + x’yz
= (xy + xyz) + (x’z + x’zy)
= xy + x’z
QED (2 true by duality).

Boolean Algebra 2023/2/28

 Enumerates all possible combinations x y z F1 F2 F3
of variable values and the 0 0 0 0 1 1
corresponding function value
0 0 1 0 0 1
 Truth tables for some arbitrary functions
F1(x,y,z), F2(x,y,z), and F3(x,y,z) are 0 1 0 0 0 1
shown to the right. 0 1 1 0 1 1
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 1 0 1
Boolean Algebra 2023/2/28
 Truth table: a unique representation of a Boolean function
 If two functions have identical truth tables, the functions are equivalent (and vice-
versa).
 Truth tables can be used to prove equality theorems.
 However, the size of a truth table grows exponentially with the number of variables
involved, hence unwieldy. This motivates the use of Boolean Algebra.

Boolean Algebra 2023/2/28

 Boolean algebra is a useful tool for simplifying digital circuits.
 Why do it? Simpler can mean cheaper, smaller, faster.
 Example: Simplify F = x’yz + x’yz’ + xz.
F = x’yz + x’yz’ + xz
= x’y(z+z’) + xz
= x’y•1 + xz
= x’y + xz

Boolean Algebra 2023/2/28

 Example: Prove
x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’
 Proof:
x’y’z’+ x’yz’+ xyz’
= x’y’z’ + x’yz’ + x’yz’ + xyz’
= x’z’(y’+y) + yz’(x’+x)
= x’z’•1 + yz’•1
= x’z’ + yz’
QED.

Boolean Algebra 2023/2/28

 The complement of a function is derived by interchanging (•
and +), and (1 and 0), and complementing each variable.
 Otherwise, interchange 1s to 0s in the truth table column
showing F.
 The complement of a function IS NOT THE SAME as the
dual of a function.

Boolean Algebra 2023/2/28

 Find G(x,y,z), the complement of
F(x,y,z) = xy’z’ + x’yz

 G = F’ = (xy’z’ + x’yz)’
= (xy’z’)’ • (x’yz)’ DeMorgan
= (x’+y+z) • (x+y’+z’) DeMorgan again

 Note: The complement of a function can also be derived by

finding the function’s dual, and then complementing all of the
literals

Boolean Algebra 2023/2/28

 Minterms and x y z Minterm Maxterm
Maxterms are easy 0 0 0 x’y’z’ = m0 x+y+z = M0
to denote using a
0 0 1 x’y’z = m1 x+y+z’ = M1
truth table.
0 1 0 x’yz’ = m2 x+y’+z = M2
 Example:
Assume 3 variables 0 1 1 x’yz = m3 x+y’+z’= M3
x,y,z 1 0 0 xy’z’ = m4 x’+y+z = M4
(order is fixed) 1 0 1 xy’z = m5 x’+y+z’ = M5
1 1 0 xyz’ = m6 x’+y’+z = M6
1 1 1 xyz = m7 x’+y’+z’ = M7

Boolean Algebra 2023/2/28

 GATE LEVEL MINIMIZATION
◦ KARNAUGH MAP
◦ TABULAR MINIMIZATION METHOD
 COMBINATIONAL LOGIC
◦ BINARY ADDER –SUBTRACTER
◦ DECIMAL ADDER
◦ BINARY MMULTIPLIER
◦ MAGNITUDE COMPARATOR
◦ DECODER, ENCODER
◦ MULTIPLEXERS AND DEMULTIPLEXER
 GATE LEVEL MINIMIZATION
◦ KARNAUGH MAP
◦ TABULAR MINIMIZATION METHOD
◦ POS AND SOP IMPLIMENTATION
◦ NAND & NOR IMPLIMENTATION NOR
◦ OTHER TWO LEVEL IMPLIMENTATION
◦ XOR IMPLIMENTATION
 Karnaugh maps (K-maps) are graphical representations of boolean functions.
 One map cell corresponds to a row in the truth table.
 Also, one map cell corresponds to a minterm or a maxterm in the boolean expression
 Multiple-cell areas of the map correspond to standard terms.

Boolean Algebra 2023/2/28

 x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1
OR 0 m0 m2
2 3 1 3
1 m2 m3 1 m1 m3

NOTE: ordering of variables is IMPORTANT for f(x1,x2), x1

is the row, x2 is the column.
Cell 0 represents x1’x2’; Cell 1 represents x1’x2; etc. If a
minterm is present in the function, then a 1 is placed in the
corresponding cell.

Boolean Algebra 2023/2/28

 Any two adjacent cells in the map differ by ONLY one variable, which appears
complemented in one cell and uncomplemented in the other.
 Example:
m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and m2 (=x1x2’) but NOT m3 (=x1x2)

Boolean Algebra 2023/2/28

 f(x1,x2) = x1’x2’+ x1’x2 + x1x2’
= m0 + m 1 + m 2
= x 1’ + x 2’
 1s placed in K-map for specified x2
minterms m0, m1, m2
 Grouping (ORing) of 1s allows x1 0 1
simplification 0 1
 What (simpler) function is
represented by each dashed
rectangle? 0 1 1
◦ x 1 ’ = m0 + m1 2 3
◦ x 2 ’ = m0 + m 2
 Note m0 covered twice
1 1 0

Boolean Algebra 2023/2/28

 Enter 1s in the K-map for each product term in the function
 Group adjacent K-map cells containing 1s to obtain a product with fewer variables.
Group size must be in power of 2 (2, 4, 8, …)
 Handle “boundary wrap” for K-maps of 3 or more variables.
 Realize that answer may not be unique

Boolean Algebra 2023/2/28

 yz
x 00 01 11 10
0 1 3 2
0 m0 m1 m3 m2
4 5 7 6
1 m4 m5 m7 m6

-Note: variable ordering is (x,y,z); yz specifies column, x specifies row.

-Each cell is adjacent to three other cells (left or right or top or bottom
or edge wrap)

Boolean Algebra 2023/2/28

 minterm
The types of structures that are either
minterms or are generated by repeated
application of the minimization
theorem on a three variable map are
shown at right.
Groups of 1, 2, 4, 8 are possible.

group of 2 terms

group of 4 terms
Boolean Algebra 2023/2/28
 Enter minterms of the Boolean function into the map, then group terms
 Example: f(a,b,c) = a’c + abc + bc’
 Result: f(a,b,c) = a’c+ b

a bc
1 1 1
1 1
1 1 1
1 1

Boolean Algebra 2023/2/28

 yz
X 00 01 11 10

 f1(x, y, z) = ∑ m(2,3,5,7) 0 1 1
1 1 1
 f1(x, y, z) = x’y + xz
 f2(x, y, z) = ∑ m (0,1,2,3,6)

1 1 1 1
f2(x, y, z) = x’+yz’
1

Boolean Algebra 2023/2/28

 YZ

WX 00 01 11 10

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

 Top cells are adjacent to bottom cells. Left-edge cells

are adjacent to right-edge cells.
 Note variable ordering (WXYZ).

Boolean Algebra 2023/2/28

 One square represents a minterm of 4 literals.
 A rectangle of 2 adjacent squares represents a product term of
3 literals.
 A rectangle of 4 squares represents a product term of 2 literals.
 A rectangle of 8 squares represents a product term of 1 literal.
 A rectangle of 16 squares produces a function that is equal to
logic 1.

Boolean Algebra 2023/2/28

 Simplify the following Boolean function (A,B,C,D) =
∑m(0,1,2,4,5,7,8,9,10,12,13).
 First put the function g( ) into the map, and then group as
many 1s as possible.
cd
ab
1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1

1 1 1 1 1 1

g(A,B,C,D) = c’+b’d’+a’bd
Boolean Algebra 2023/2/28
 There may be a combination of input values which
◦ will never occur
◦ if they do occur, the output is of no concern.
 The function value for such combinations is called a don't care.
 They are denoted with x or –. Each x may be arbitrarily assigned the
value 0 or 1 in an implementation.
 Don’t cares can be used to further simplify a function

Boolean Algebra 2023/2/28

 Treat don't cares as if they are 1s to generate PIs.
 Delete PI's that cover only don't care minterms.
 Treat the covering of remaining don't care minterms as optional in the selection
process (i.e. they may be, but need not be, covered).

Boolean Algebra 2023/2/28

 cd
ab 00 01 11 10
00 0 1 0 1
01 1 1 0 1
 Simplify the function f(a,b,c,d) 11 0 0 x x
whose K-map is shown at the right. 10 1 1 x x
 f = a’c’d+ab’+cd’+a’bc’
or 0 1 0 1
 f = a’c’d+ab’+cd’+a’bd’ 1 1 0 1
0 0 x x
1 1 x x

0 1 0 1
1 1 0 1
0 0 x x
1 1 x x

Boolean Algebra 2023/2/28

 cd
ab
x 1 0 0
1 x 0 x
 Simplify the function g(a,b,c,d) 1 x x 1
whose K-map is shown at right. 0 x x 0
 g = a’c’+ ab
or x 1 0 0
 g = a’c’+b’d 1 x 0 x
1 x x 1
0 x x 0

x 1 0 0
1 x 0 x
1 x x 1
0 x x 0

Boolean Algebra 2023/2/28

 What do we do for functions with more variables?
 You can “code up” a minimizer (Computer-Aided Design, CAD)
◦ Quine-McCluskey algorithm
◦ Iterated consensus
 We won’t discuss these techniques here

Boolean Algebra 2023/2/28

 NAND and NOR Gates
◦ NAND and NOR circuits
◦ Two-level Implementations
◦ Multilevel Implementations
 Exclusive-OR (XOR) Gates
◦ Odd Function
◦ Parity Generation and Checking

Boolean Algebra 2023/2/28

 We can construct any combinational circuit with AND, OR,
and NOT gates

 Additional logic gates are used for practical reasons

Boolean Algebra 2023/2/28

Boolean Algebra 2023/2/28
 Known as a “Universal” gate because ANY digital circuit can
be implemented with NAND gates alone.
 To prove the above, it suffices to show that AND, OR, and
NOT can be implemented using NAND gates only.

Boolean Algebra 2023/2/28

 F = (X•X)’ X F = X’
X = X’+X’
= X’

X X F
F = ((X•Y)’)’
Y Y X•Y
= (X’+Y’)’
= X’’•Y’’
= X•Y
X X
F = (X’•Y’)’ F=
= X’’+Y’’ X+Y
Y = X+Y Y

Boolean Algebra 2023/2/28

 To easily derive a NAND implementation of a boolean
function:
◦ Find a simplified SOP
◦ SOP is an AND-OR circuit
◦ Change AND-OR circuit to a NAND circuit
◦ Use the alternative symbols below

Boolean Algebra 2023/2/28

 Two-level implementations

a) Original SOP
b) Implementation with NANDs

Boolean Algebra 2023/2/28

Verify:
(a) G = WXY + YZ
(b) G = ( (WXY)’ • (YZ)’ )’
= (WXY)’’ + (YZ)’’ = WXY + YZ

Boolean Algebra 2023/2/28

(a) Original SOP AND-NOT
(b) Double inversion and grouping
NOT-OR
(c) Replacement with NANDs
Boolean Algebra 2023/2/28
F (X,Y,Z) = m(0,6)
1. Express F in SOP form:
F = X’Y’Z’ + XYZ’
2. Obtain the AND-OR implementation for F.
3. Add bubbles and inverters to transform AND-OR to NAND-
NAND gates.

Boolean Algebra 2023/2/28

Two-level implementation with NANDs
F = X’Y’Z’ + XYZ’

Boolean Algebra 2023/2/28

Starting from a multilevel circuit:
1. Convert all AND gates to NAND gates with AND-NOT
graphic symbols.
2. Convert all OR gates to NAND gates with NOT-OR graphic
symbols.
3. Check all the bubbles in the diagram. For every bubble that
is not counteracted by another bubble along the same line,
insert a NOT gate or complement the input literal from its
original appearance.

Boolean Algebra 2023/2/28

Boolean Algebra 2023/2/28
 Also a “Universal” gate because ANY digital circuit can be
implemented with NOR gates alone.
 This can be similarly proven as with the NAND gate.

Boolean Algebra 2023/2/28

 To easily derive a NOR implementation of a boolean function:
◦ Find a simplified POS
◦ POS is an OR-AND circuit
◦ Change OR-AND circuit to a NOR circuit
◦ Use the alternative symbols below

Boolean Algebra 2023/2/28

F(X,Y,Z) = m(0,6)
1. Express F’ in SOP form:
a)F’ = m(1,2,3,4,5,7)
= X’Y’Z + X’YZ’ + X’YZ + XY’Z’ + XY’Z +
XYZ
b)F’ = XY’ + X’Y + Z
2. Take the complement of F’ to get F in the POS form: F =
(F’)' = (X'+Y)(X+Y')Z'
3. Obtain the OR-AND implementation for F.
4. Add bubbles and inverters to transform OR-AND
implementation to NOR-NOR implementation.

Boolean Algebra 2023/2/28

Two-level implementation with NORs
F = (F’)' = (X'+Y)(X+Y')Z'

Boolean Algebra 2023/2/28

 X Y F = XY
XOR: “not-equal” gate 0 0 0
0 1 1
X F 1 0 1
Y 1 1 0

X Y F = XY
XNOR: “equal” gate
0 0 1
0 1 0
X F
1 0 0
Y 1 1 1

Boolean Algebra 2023/2/28

 XOR (also ) : the “not-equal” function
 XOR(X,Y) = X  Y = X’Y + XY’
 Identities:
◦ X0=X
◦ X  1 = X’
◦ XX=0
◦ X  X’ = 1
 Properties:
◦ XY=YX
◦ (X  Y)  W = X  ( Y  W)

Boolean Algebra 2023/2/28

 XOR(a,b) = ab’ + a’b
 Straightforward: 5 gates
◦ 2 inverters, two 2-input ANDs, one 2-input OR
◦ 2 inverters & 3 2-input NANDs
 Nonstraightforward:
◦ 4 NAND gates

Boolean Algebra 2023/2/28

Boolean Algebra 2023/2/28
 COMBINATIONAL LOGIC
◦ BINARY ADDER –SUBTRACTER
◦ DECIMAL ADDER
◦ BINARY MMULTIPLIER
◦ MAGNITUDE COMPARATOR
◦ DECODER, ENCODER
◦ MULTIPLEXERS AND DEMULTIPLEXER
 Logic circuits for digital systems may be combinational or
sequential.
 A combinational circuit consists of input variables, logic gates,
and output variables.

119
 To obtain the output Boolean functions from a logic diagram,
proceed as follows:
1. Label all gate outputs that are a function of input variables with arbitrary
symbols. Determine the Boolean functions for each gate output.

2. Label the gates that are a function of input variables and previously labeled
gates with other arbitrary symbols. Find the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.

4. By repeated substitution of previously defined functions, obtain the output

Boolean functions in terms of input variables.
F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1;
F1 = T3 + T2
F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

121
 We can derive the truth table in Table 4-1 by using the circuit of
Fig.4-2.

122
1. Table4-2 is a Code-Conversion example, first, we can list the
relation of the BCD and Excess-3 codes in the truth table.

123
2. For each symbol of the Excess-3 code, we use 1’s to draw the
map for simplifying Boolean function.

124
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)

125
 A combinational circuit that performs the addition of two bits is
called a half adder.
 The truth table for the half adder is listed below:

S: Sum
C: Carry

S = x’y + xy’
C = xy

126
 One that performs the addition of three bits(two
significant bits and a previous carry) is a full adder.

128
 C

S = x’y’z + x’yz’ + xy’z’ + xyz

C = xy + xz + yz
129
130
 Full-adder can also implemented with two half
adders and one OR gate (Carry Look-Ahead adder).
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

131
 This is also called
Ripple Carry
Adder ,because of
the construction
with full adders
are connected in
cascade.

132
 Fig.4-9 causes a unstable factor on carry bit, and
produces a longest propagation delay.
 The signal from Ci to the output carry Ci+1, propagates
through an AND and OR gates, so, for an n-bit RCA,
there are 2n gate levels for the carry to propagate
from input to output.

133
 Because the propagation delay will affect the output signals
on different time, so the signals are given enough time to
get the precise and stable outputs.
 The most widely used technique employs the principle of
carry look-ahead to improve the speed of the algorithm.

134
 Pi = Ai ⊕ Bi steady state value
Gi = AiBi steady state value
Output sum and carry
Si = Pi ⊕ Ci
Ci+1 = Gi + PiCi
Gi : carry generate Pi : carry propagate
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

 C3 does not have to wait for C2 and C1 to

propagate.
 C3 is propagated at the same time as C2 and C1.

136
 Delay time of n-bit CLAA = XOR + (AND + OR) + XOR

137
M = 1subtractor ; M = 0adder

138
BCD adder can’t exceed 9 on each input digit. K is the carry.

139
 When the binary sum is greater than 1001, we obtain a non-valid
BCD representation.
 The addition of binary 6(0110) to the binary sum converts it to the
correct BCD representation and also produces an output carry as
required.
 To distinguish them from binary 1000 and 1001, which also have a
1 in position Z8, we specify further that either Z4 or Z2 must have a
1.
C = K + Z8Z4 + Z8Z2
 A decimal parallel
adder that adds n
decimal digits needs n
BCD adder stages.
 The output carry from
one stage must be
If =1
connected to the input
carry of the next
0110
higher-order stage.

141
 Usually there are more bits in the partial products and it is necessary
to use full adders to produce the sum of the partial products.

And

142
 For J multiplier bits and K
multiplicand bits we need (J X K)
AND gates and (J − 1) K-bit
adders to produce a product of
J+K bits.
 K=4 and J=3, we need 12 AND
gates and two 4-bit adders.

143
 The equality relation of
each pair of bits can be
expressed logically with an
exclusive-NOR function as:

A = A3A2A1A0 ; B =
B3B2B1B0

xi=AiBi+Ai’Bi’ for i =
0, 1, 2, 3

(A = B) = x3x2x1x0

144
 We inspect the relative magnitudes
of pairs of MSB. If equal, we
compare the next lower significant
pair of digits until a pair of unequal
digits is reached.

 If the corresponding digit of A is 1

and that of B is 0, we conclude that
A>B.
(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B
’0
(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B
0
145
 The decoder is called n-to-m-line decoder, where m≤2n .
 the decoder is also used in conjunction with other code converters such as a BCD-to-
seven_segment decoder.
 3-to-8 line decoder: For each possible input combination, there are seven outputs that
are equal to 0 and only one that is equal to 1.
 Some decoders are constructed with NAND gates, it becomes
more economical to generate the decoder minterms in their
complemented form.
 As indicated by the truth table , only one output can be equal to 0
at any given time, all other outputs are equal to 1.

148
 A decoder with an enable input is referred to as a
decoder/demultiplexer.
 The truth table of demultiplexer is the same with decoder.

A B

D0

Demultiplexer D1
E
D2
D3
 From table 4-4, we obtain the functions for the combinational circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

151
 An encoder is the inverse operation of a decoder.
 We can derive the Boolean functions by table 4-7
z = D 1 + D3 + D 5 + D 7
y = D2 + D3 + D6 + D 7
x = D4 + D5 + D6 + D 7

152
 If two inputs are active simultaneously, the output produces an undefined combination. We
can establish an input priority to ensure that only one input is encoded.
 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated
when all the inputs are 0; the output is the same as when D0 is equal to 1.
 The discrepancy tables on Table 4-7 and Table 4-8 can resolve aforesaid condition by
providing one more output to indicate that at least one input is equal to 1.
V=0no valid inputs
V=1valid inputs

X’s in output columns represent

don’t-care conditions
X’s in the input columns are
useful for representing a truth
table in condensed form.
Instead of listing all 16
minterms of four variables.

154
 0
 Implementation of 0
table 4-8 0
0
x = D2 + D3
y = D3 + D1D’2
V = D 0 + D1 + D 2 + D 3

155
S = 0, Y = I0 Truth Table S Y = S’I0
+ SI1
S = 1, Y = I1 0 I0
1
I1

156
 Multiplexer circuits can be combined with common selection
inputs to provide multiple-bit selection logic. Compare with
Fig4-24.

I0 Y

I1

158
 A more efficient method for implementing a Boolean
function of n variables with a multiplexer that has n-1
selection inputs.
F(x, y, z) = (1,2,6,7)

159
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

160
 A multiplexer can be constructed with three-state gates.

161
 There are two basic types of design methodologies: top-down
and bottom-up.
 Top-down: the top-level block is defined and then the sub-blocks
necessary to build the top-level block are identified.(Fig.4-9
binary adder)
 Bottom-up: the building blocks are first identified and then
combined to build the top-level block.(Example 4-2 4-bit adder)

162
Gates statement: gate name(output, input, control)
>> bufif1(OUT, A, control);
A = OUT when control = 1, OUT = z when control = 0;
>> notif0(Y, B, enable);
Y = B’ when enable = 0, Y = z when enable = 1;

163
 HDL uses the keyword tri
to indicate that the output
has multiple drivers.

module muxtri (A, B, select, OUT);

input A,B,select;
output OUT;
tri OUT;
bufif1 (OUT,A,select);
bufif0 (OUT,B,select);
endmodule

164
Sequential
Circuits
  Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements
 Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

166
 Latches and flip-flops (FFs) are the basic building
blocks of sequential circuits.

◦ latch: bistable memory device with level sensitive triggering

(no clock), watches all of its inputs continuously and changes
its outputs, independent of a clocking signal.
◦ flip-flop: bistable memory device with edge-triggering (with
clock), samples its inputs, and changes its output only at
times determined by a clocking signal.

167
  SR Latch
S R Q0 Q Q’
0 1 Q = Q0
0 0 0

R
0 0
Q

S Q
0 1

Initial Value
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
1 Q=0
R
1 0 0 1 0 0
Q

S Q
0 1
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 Q=0
Q 0 1 1

S Q
0 0
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 Q=0
0 1 1 0 1
Q 1 0 Q=1
1 0 0

S Q
1 1
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 Q=0
0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 Q=1
1 0 1

S Q
1 0
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 Q=0
0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0
0 0 Q = Q’
1 1 0

S Q
1 10
  SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
0 0 Q = Q’
1 1 1
S Q
1 0
  SR Latch
S R Q
R Q No change
0 0 Q0
Reset
0 1 0
Set
1 0 1
S Q Invalid
1 1 Q=Q’=0

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
  SR Latch
S R Q
R Q No change
0 0 Q0
Reset
0 1 0
Set
1 0 1
S Q Invalid
1 1 Q=Q’=0

S S’ Q
Q
R’ Invalid
0 0 Q=Q’=1 Set
Q 0 1 1 Reset
R
1 0 0 No change
1 1 Q0
  SR Latch with Control Input
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
No change
0 x x Q0
No change
1 0 0 Q0
Reset
1 0 1 0 Set
1 1 0 1 Invalid
1 1 1 Q=Q’
  D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

t
C D Q Output may
0 x Q0 No change change
Reset
1 0 0
Set
1 1 1
  D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

C D Q Output may
No change change
0 x Q0
Reset
1 0 0
Set
1 1 1
 Controlled latches are level-triggered

C
 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

  Master-Slave D Flip-Flop

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
  Edge-Triggered D Flip-Flop
D Q

Q Positive Edge
CLK

Q
D Q

D Negative Edge
  JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
  T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q
D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q No change
0 0 Q(t)
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q
0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)
T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
  Analysis / Derivation

Q(t
J K Q(t+1)
) No change
J Q 0 0 0 0
0 0 1 1 Reset
K Q 0 1 0
0 1 1 Set
1 0 0
1 0 1 Toggle
1 1 0
1 1 1
  Analysis / Derivation

Q(t
J K Q(t+1)
) No change
J Q 0 0 0 0
0 0 1 1 Reset
K Q 0 1 0 0
0 1 1 0 Set
1 0 0
1 0 1 Toggle
1 1 0
1 1 1
  Analysis / Derivation

Q(t
J K Q(t+1)
) No change
J Q 0 0 0 0
0 0 1 1 Reset
K Q 0 1 0 0
0 1 1 0 Set
1 0 0 1
1 0 1 1 Toggle
1 1 0
1 1 1
  Analysis / Derivation

Q(t
J K Q(t+1)
) No change
J Q 0 0 0 0
0 0 1 1 Reset
K Q 0 1 0 0
0 1 1 0 Set
1 0 0 1
1 0 1 1 Toggle
1 1 0 1
1 1 1 0
  Analysis / Derivation

Q(t
J K Q(t+1)
)
J Q 0 0 0 0 K
0 0 1 1 0 1 0 0
K Q 0 1 0 0 J 1 1 0 1
0 1 1 0 Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Q(t+1) = JQ’ + K’Q
  Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset
  Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset
  Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0

Q
CLR
Reset
  Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q
CLR
Reset
  Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset
 The Mealy model: the outputs are functions of
both the present state and inputs (Fig. 5-15).
◦ The outputs may change if the inputs change during
the clock pulse period.
 The outputs may have momentary false values unless
the inputs are synchronized with the clocks.
 The Moore model: the outputs are functions
of the present state only (Fig. 5-20).
◦ The outputs are synchronous with the clocks.
Fig. 5.21 Block diagram of Mealy and Moore state machine
 State Reduction
Reductions on the
number of flip-flops
and the number of
gates.
◦ A reduction in the
number of states may
result in a reduction in
the number of flip-flops.
◦ An example state
diagram showing in Fig.
5.25.

Fig. 5.25 State diagram

 State: a a b c d e f f g f g a
Input: 0 1 0 1 0 1 1 0 1 0 0
◦ Only the input-output
sequences are 0 0 0 0 0 1 1 0 1 0 0
Output:

important.
◦ Two circuits are
equivalent
 Have identical outputs for
all input sequences;
 The number of states is
not important.

Fig. 5.25 State diagram

 Equivalent states
◦ Two states are said to be equivalent
 For each member of the set of inputs, they give exactly
the same output and send the circuit to the same state
or to an equivalent state.
 One of them can be removed.
 Reducing the state table
◦ e = g (remove g);
◦ d = f (remove f);
 ◦ The reduced finite state machine

State: a a b c d e d d e d e a
Input: 0 1 0 1 0 1 1 0 1 0 0
Output: 0 0 0 0 0 1 1 0 1 0 0
◦ The checking of each
pair of states for
possible equivalence can
be done systematically
using Implication Table.
◦ The unused states are
treated as don't-care
condition  fewer
combinational gates.

Fig. 5.26 Reduced State diagram

 State Assignment
 To minimize the cost of the combinational
circuits.
◦ Three possible binary state assignments. (m states
need n-bits, where 2n > m)
◦ Any binary number assignment is satisfactory as
long as each state is assigned a unique number.
◦ Use binary assignment 1.
 Sequential circuits are digital circuits in which
the outputs depend not only on the current
inputs, but also on the previous state of the
output.
 They basic sequential circuit elements can be
divided in two categories:
 Level-sensitive (Latches)
◦ High-level sensitive
◦ Low-level sensitive
 Edge-triggered (Flip-flops)
◦ Rising (positive) edge triggered
◦ Falling (negative) edge triggered
◦ Dual-edge triggered

ACOE161 - Digital Logic for 209

Computers - Frederick University
The Set/Reset latch is the most basic unit of sequential digital
circuits. It has two inputs (S and R) and two outputs outputs Q and
Q’. The two outputs must always be complementary, i.e if Q is 0
then Q’ must be 1, and vice-versa. The S input sets the Q output to
a logic 1. The R input resets the Q output to a logic 0.

Circuit Diagram Truth Table

R
Q S R Q+ Q΄+ Function

0 0 Q Q΄ Latch
0 1 0 1 Reset
1 0 1 0 Set
Q
S 1 1 0 0 Illegal

S
Q Logic Symbol

S Q

R Q
Q
R

ACOE161 - Digital Logic for 210

Computers - Frederick University
To be able to control when the S and R inputs of the SR latch can be
applied to the latch and thus change the outputs, an extra input is
used. This input is called the Enable. If the Enable is 0 then the S
and R inputs have no effect on the outputs of the SR latch. If the
Enable is 1 then the Gated SR latch behaves as a normal SR latch.

Circuit Diagram Truth Table Truth Table

S EN S R Q+ EN S R Q+ Function
S Q Q
0 0 0 Q 0 X X
EN

R Q Q 0 0 1 Q 1 0 0
R
0 1 0 Q 1 0 1
0 1 1 Q 1 1 0
Logic Symbol
1 0 0 Q 1 1 1

S Q 1 0 1 0
EN 1 1 0 1
R Q
1 1 1 U

ACOE161 - Digital Logic for 211

Computers - Frederick University
Complete the timing diagrams for :
(a) Simple SR Latch
(b) SR Latch with Enable input.
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

Set Enable

Reset Set

Reset
Q

ACOE161 - Digital Logic for 212

Computers - Frederick University
A problem with the SR latch is that the S and R inputs can not be at
logic 1 at the same time. To ensure that this can not happen, the S
and R inputs can by connected through an inverter. In this case the
Q output is always the same as the input, and the latch is called the
Data or D latch. The D latch is used in Registers and memory
devices.

Circuit Diagram Truth Table Truth Table

D EN D Q Q+ EN D Q+ Function
S Q Q
0 0 0 Q 0 0
EN
0 0 1 Q 0 1
R Q Q
0 1 0 Q 1 0
0 1 1 Q 1 1
Logic Symbol
1 0 0 0
D Q
1 0 1 0
EN
1 1 0 1
Q
1 1 1 1

ACOE161 - Digital Logic for 213

Computers - Frederick University
Another way to ensure that the S and R inputs can not be at logic 1
simultaneously, is to cross connect the Q and Q’ outputs with the S
and R inputs through AND gates. The latch obtained is called the JK
latch. In the J and K inputs are both 1 then the Q output will change
state (Toggle) for as long as the Enable 1, thus the output will be
unstable. This problem is avoided by ensuring that the Enable is at
logic 1 only for a very short time, using edge detection circuits.
Circuit Diagram Truth Table Truth Table

EN J K Q Q+ EN J K Q+ Function
J S Q Q
0 X X X Q 0 X X
EN
1 0 0 0 0 1 0 0
K R Q Q
1 0 0 1 1 1 0 1
1 0 1 0 0 1 1 0
Logic Symbol
1 0 1 1 0 1 1 1
J Q 1
1 1 0 0
EN
1 1 0 1 1
K Q
1 1 1 0 1
1 1 1 1 0

ACOE161 - Digital Logic for 214

Computers - Frederick University
 Latches are also called transparent or level
triggered flip flops, because the change on the
outputs will follow the changes of the inputs as
long as the Enable input is set.
 Edge triggered flip flops are the flip flops that
change there outputs only at the transition of the
Enable input. The enable is called the Clock input.

ACOE161 - Digital Logic for 215

Computers - Frederick University
Edge detection circuits are used to detect the transition of the
Enable from logic 0 to logic 1 (positive edge) or from logic 1 to logic
0 (negative edge). The operation of the edge detection circuits
shown below is based on the fact that there is a time delay between
the change of the input of a gate and the change at the output.
This delay is in the order of a few nanoseconds. The Enable in this
case is called the Clock (CLK)

Positive Edge Detection Negative Edge Detection

EN
EN' EN
EN'
EN
EN
EN

EN EN

EN

EN
EN

EN' EN'

ACOE161 - Digital Logic for 216

Computers - Frederick University
The JK edge triggered flip flop can be obtained by inserting an edge
detection circuit at the Enable (CLK) input of a JK latch. This ensures
that the outputs of the flip flop will change only when the CLK
changes (0 to 1 for +ve edge or 1 to 0 for –ve edge)

Positive Edge JK Flip Flop Negative Edge JK Flip Flop

J J
S Q Q S Q Q

CLK CLK

R Q Q R Q Q
K K

CLK J K QN+1 Function CLK J K QN+1 Function

Logic Symbol Logic Symbol
X X Q X X
J Q J Q
0 0 Q 0 0
CLK CLK
K Q 0 1 0 K Q 0 1
1 0 1 1 0
1 1 Q’ 1 1

ACOE161 - Digital Logic for 217

Computers - Frederick University
The D edge triggered flip flop can be obtained by connecting the J
with the K inputs of a JK flip through an inverter as shown below.
The D edge trigger can also be obtained by connecting the S with
the R inputs of a SR edge triggered flip flop through an inverter.

Positive Edge D Flip Flop Negative Edge D Flip Flop

D J Q Q D J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function
D Q X Q D Q X Q
CLK 0 CLK 0
0 0
Q Q 1
1 1 1

ACOE161 - Digital Logic for 218

Computers - Frederick University
The T edge triggered flip flop can be obtained by connecting the J
with the K inputs of a JK flip directly. When T is zero then both J and
K are zero and the Q output does not change. When T is one then
both J and K are one and the Q output will change to the opposite
state, or toggle.

Positive Edge T Flip Flop Negative Edge T Flip Flop

T J Q Q T J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK T QN+1 Function Logic Symbol CLK T QN+1 Function
T Q X Q T Q X Q
CLK 0 Q CLK 0 Q
Q 1 Q΄ Q 1 Q΄

ACOE161 - Digital Logic for 219

Computers - Frederick University
Two extra inputs are often found on flip flops, that either clear or
preset the output. These inputs are effective at any time, thus are
called asynchronous. If the Clear is at logic 0 then the output is
forced to 0, irrespective of the other normal inputs. If the Preset is
at logic 0 then the output is forced to 1, irrespective of the other
normal inputs. The preset and the clear inputs can not be 0
simultaneously. In the Preset and Clear are both 1 then the flip flop
behaves according to its normal truth table.

Positive Edge JK Flip Flop with Preset and Clear

CLK PR CLR J K QN+1 Function

PRESET
PR
0 0 X X
J Q
0 1 X X 1
1 0 X X 0
K Q 1 1 0 0 Q
CLR
1 1 0 1 0
CLEAR
1 1 1 0 1
1 1 1 1 Q’

ACOE161 - Digital Logic for 220

Computers - Frederick University
Complete the timing diagrams for :
(a) D Latch
(b) JK Latch
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

Enable Enable

Data (D) J

K
Q

ACOE161 - Digital Logic for 221

Computers - Frederick University
Complete the timing diagrams for :
(a) Positive Edge Triggered JK Flip Flop
(b) Negative Edge Triggered JK Flip Flop
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

CLK CLK

J J

K K

Q Q

ACOE161 - Digital Logic for 222

Computers - Frederick University
Complete the timing diagrams for :
(a) Positive Edge Triggered D Flip Flop
(b) Positive Edge Triggered T Flip Flop
(c) Negative Edge Triggered T Flip Flop
(d) Negative Edge Triggered D Flip Flop

(a) (b)

CLK CLK

D D

Q Q

(c) (d)

CLK CLK

T T

Q Q

ACOE161 - Digital Logic for 223

Computers - Frederick University
Complete the timing diagrams for :
(a) Positive Edge Triggered JK Flip Flop
(b) Negative Edge Triggered JK Flip Flop.
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

CLK CLK

J J

K K

CLR CLR

PR PR

Q Q

ACOE161 - Digital Logic for 224

Computers - Frederick University
A Master Slave flip flop is obtained by
connecting two SR latches as shown below. This
flip flop reads the inputs
Master whenSlavethe clock is 1
and changes the output when the clock is at CLK J
Logic Symbol Truth Table

Q K Q Function

logic zero.
J S Q S Q Q
J
CLK 0 0
CLK
K R Q R Q Q Q 0 1
K
1 0
1 1

(a) Positive Master Slave JK Flip Flop (b) Negative Master Slave JK Flip Flop

CLK CLK

J J

K K

Q Q

ACOE161 - Digital Logic for 225

Computers - Frederick University
A Master Slave flip flop is obtained by
connecting two SR latches as shown below. This
flip flop reads the inputs
Master
when
Slave
the clock is 1
Logic Symbol Truth Table

and changes the output when the clock is at CLK J

J
S Q S Q Q Q K Q Function

logic zero.
J
CLK 0 0
R Q R Q0 Q Q 1
K
K
1 0
1 1

(a) Positive Master Slave JK Flip Flop (b) Negative Master Slave JK Flip Flop

CLK CLK

J J

K K

Q Q

ACOE161 - Digital Logic for 226

Computers - Frederick University
 A0

2-to-1 SET
MUX
D Q

A1

CLR Q

Clock

1 2 3 4 5 6 7 8 9 10
Clock

A0

A1

D
Q

ACOE161 - Digital Logic for 227

Computers - Frederick University
 SET
D Q

CLR Q

Clock

1 2 3 4 5 6 7 8 9 10
Clock

Q’

ACOE161 - Digital Logic for 228

Computers - Frederick University
 CP
X S
FULL ADDER
Y
C X
Z

Y
SET
Q D/T
CP Z
Q CLR

ACOE161 - Digital Logic for 229

Computers - Frederick University
 A register that goes through a prescribed sequence
of states upon the application of input pulses is
called a counter.
The input pulses may be clock pulses or they may
originate from some external source and may occur
at a fixed interval of time or at random.
The sequence of states may follow the same binary
number sequence or any other sequence of states .
A counter that follows the binary number sequence is
called a binary counter.
An n-bit binary counter consists of n flip flops and
can count in binary from o through (2^n)-1.
Counters are available in 2 categories: ripple counters
and synchronous counters.
In a ripple counter, the flip flop output transition
serves as a source for triggering other flip flops.
 A binary ripple counter consists of a series
connection of complementing flip flops(T or JK),
with the output of each flip flop connected to
the CP input of the next higher order flip flop.
The flip flop holding the least significant bit
receives the incoming count pulses.
In the diagram of 4-bit binary ripple counter, all
J and K inputs are equal to 1.
The small circle in the CP input indicates that
the flip flop complements during a negative-
going transition or when the output to which it
is connected goes from 1 to 0.
 From the table it is obvious that the lowest-
order bit A1 must be complemented with each
count pulse.
Every time A1 goes from 1 to 0, it complements
A2.
Every time A2 goes from 1 to 0, it complements
A3, and so on.
The flip flops change once at a time in rapid
succession, and the signal propagates through
the counter in a ripple fashion.
Ripple counters are also called as asynchronous
counters
 A decimal counter follows a sequence of ten
states and returns to 0 after the count of 9.
Such a counter must have at least 4 flip flops to
represent each decimal digit is represented by
the binary code used to represent a decimal digit.
The sequence of states in a decimal counter is
dictated by the binary code used to represent a
decimal digit.
In the diagram, the output of Q1 is applied to the
C inputs of both Q2 and Q8 and the output of Q2
is applied to the C input of Q4.
The J and K inputs are connected either to a
permanent 1 signal or to outputs of other flip
flops.
A ripple counter is an asynchronous sequential
 State diagram of a decimal BCD
counter

 When the C input goes from 1 to 0, the flip flop is set if J=1,
is cleared if K=1, is complemented if J=K=1, and is left
unchanged if J=K=0.
BCD ripple counter
 Synchronous counters are different from ripple
counters in that clock pulses are applied to the
inputs of all flip flops simultaneously rather
than one at a time in succession as in a ripple
counter.
The decision whether a flip flop is to be
complemented or not is determined from the
values of the data inputs such as T or J and K at
the time of the clock edge.
If T=0 or J=K=0, the flip flop does not change
state.
If T=1 or J=K=1, the flip flop complements.
The design of a synchronous binary counter is so simple that
there is no need to go through a sequential logic design
process.
In a synchronous binary counter, the flip flop in the least
significant position is complemented with every pulse.
A flip flop in any other position is complemented when all
the bits in the lower significant positions are equal to 1.
For eg, if the present state of a 4-bit counter is
A3A2A1A0=0011, the next count is 0100.
A is always complemented because the present state of
0

A =1.0

A is complemented because the present state of A A =11.

2 1 0

However A is not complemented because the present state

3

of A A A =011, which does not give an all 1’s condition.

2 1 0
4-bit synchronous
binary counter
 In the diagram, the C inputs of all flip flops are
connected to a common clock.
The counter is enabled with the count enable input.
If the enable input is 0, all J and K inputs are equal
to 0 and the clock does not change the state of the
counter.
The first stage A0 has its J and K equal to 1 if the
counter is enabled.
The other J and K inputs are equal to 1 if all
previous least significant stages are equal to 1 and
count is enabled.
The chain of AND gates generates the required
logic for the J and K inputs in each stage.
The counter can be extended to any number of
stages, with each stage having an additional flip
flop and an AND gate that gives an output of 1 if all
previous flip flop outputs are 1
A synchronous count down binary counter goes through
the binary states in reverse order from 1111 down to
0000 and back to 1111 to repeat the count.
The bit in the least significant position is complemented
with each pulse.
A bit in any other position is complemented if all lower
significant bits are equal to 0.
For eg, the next state after the present state of 0100 is
0011.
The least significant bit is always complemented.
The second significant bit is complemented because the
first 2 bits are equal to 0.
The 3rd significant bit is complemented because the 1st
2 bits are equal to 0.
But the 4th bit does not change because not all lower
significant bits are equal to 0.
4-bit up-down binary counter
 Both up counting and down counting can be combined in
one circuit to form a counter capable of counting either
up or down.
It has an up control input and a down control input.
When the up input is 1, the circuit counts up, since the T
inputs receive their signals from the values of the
previous normal outputs of the flip flops.
When the up input is 1 and the down input is 0, the circuit
counts up, since the T inputs receive their signals from
the values of the normal outputs of the flip flops.
When the down input is 1 and the up input is 0, the circuit
counts down, since the complemented outputs of the
previous flip flops are applied to the T inputs.
When the up and down inputs are both 0, the circuit does
not change state and remains in the same count.
When the up and down inputs are both 1, the circuit
counts up.
A BCD counter counts in binary-coded decimal
from 0000 to 1001 and back to 0000.
The flip flop input conditions for the T flip flops are
obtained from the present and next state
conditions.
The output is equal to 1 when the present state is
1001.
In this way, y can enable the count of the next
higher significant decade while the same pulse
switches the present decade from 1001 to 0000.
The flip flop input equations can be simplified by
means of maps.
The unused terms are taken as don’t care terms.
The circuit can be easily drawn with 4 T flip flops, 5
AND gates and 1 OR gate.
Synchronous BCD counters can be cascaded to form
a counter for decimal numbers of any length.
Procedure to Design Synchronous Counters

The procedure to design a synchronous counter is listed here.

• Obtain the truth table of the logic sequence for intended
counter to be designed. Alternatively obtain the state diagram of
the counter.
• Determine the number and type of flip-flop to be used.
• From the excitation table of the flip-flop, determine the next
state logic.
• From the output state, use Karnaugh map for simplification to
derive the
circuit output functions and the flip-flop output functions.
• Draw the logic circuit diagram.
Ring Counter
 Johnson Counter

The Johnson counter, also known as the twisted-ring

counter, is exactly the same as the ring counter except
that the inverted output of the last flip-flop is connected
to the input of the first flip-flop.
Let’s say, starts from 000, 100, 110, 111, 011 and 001,
and the sequence is repeated so long as there is input
pulse.
 Clock Pulse
FFA FFB FFC FFD
No
0 0 0 0 0
1 1 0 0 0
Truth Table for a 4-bit Johnson 2 1 1 0 0
Ring Counter 3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
 The generation of pseudo-random bit sequences is particularly useful in
communication and computing systems
 Pseudo-random sequences are normally generated using a circuit called linear-
feedback shift register (LFSR)
 it consists simply of a tapped circular shift register with the taps feeding a modulo-2
adder (XOR gate) whose output is fed back to the first flip-flop
The shift register must start from a nonzero state
PROGRAMMABLE
DEVICES
 All use AND-OR structure- differ in which is programmable
Fixed ANDarray
Programmable Programmable OR
Inputs (decoder) Outputs
connections array

Programmable read-only memory (PROM)

Programmable Programmable AND Fixed ORarray

Inputs Outputs
connections array

Programmable array logic (PAL)device

Programmable Programmable AND Programmable Programmable OR

Inputs Outputs
connections array connections array

Programmable logic array (PLA)

Ahmad Almulhem, KFUPM2010
24
Note: This PROM has 4 memory locations of 4 bits each

representation using gates simplified representation

25
representation using gates simplified representation

26
• AND array and ORarray
are programmable
• XORis available to complement
an output if needed

• Example:
• 3 inputs/2 outputs
• F1= A B’ + A C+ A’ B C’
• F2 = (AC + BC)’

Source: Mano’stextbook

Ahmad Almulhem, KFUPM 2010

• Fixed ORarray and
programmable AND array
• Opposite of ROM
• Feed back is used to support more
product terms
• AND output can not beshared here!

• Example:
• 4 inputs/4 outputs with fixed 3- input OR
gates
• W = A B C’ + A’ B’ CD’
• X =?
• Y= ?
• Z=?
Source: Mano’stextbook
Ahmad Almulhem, KFUPM2010
29
 Use a PROM to implement an: AB F1 F2 F3 F4
• inverter F1 =A
00 1 0 1 0
• OR F2 = A+B F3
• NAND = A·B F4 = A 01 1 1 1 1
• XOR B 10 0 1 1 1
11 0 1 0 0

Truth table is transferred directly

to the PROMgrid.

30
• Xilinx FPGAs
• Configurable Logic Block
(CLB)
• Programmable logic and FFs
• Programmable
Interconnects
• Switch Matrices
• Horizontal/vertical lines
• I/O Block (IOB)
• Programmable I/O pins

Source: Mano’stextbook

Ahmad Almulhem, KFUPM 2010

– a programmable device using more complex cells
• Xilinx
– Virtex-II/Virtex-4: Feature- packed • Actel
high-performance SRAM-based FPGA
– Anti-fuse based FPGAs
– Spartan 3: low-cost feature reduced
version • Radiation tolerant
– CoolRunner: CPLDs – Flash-based FPGAs
• Altera • Lattice
– Stratix/Stratix-II
• High-performance SRAM-based – Flash-based FPGAs
FPGAs – CPLDs (EEPROM)
– Cyclone/Cyclone-II
• Low-cost feature reduced version for • QuickLogic
cost-critical applications
– MAX3000/7000 CPLDs
– ViaLink-based FPGAs
– MAX-II: Flash-based FPGA

33
• Internal SRAM
• Embedded Multipliers and DSP
blocks
• Embedded logic analyzer
• Embedded CPUs
• High speed I/O (~10GHz)
• DDR/DDRII/DDRIII SDRAM
interfaces
• PLLs
 The term random access as applied to RAM comes from the fact that any storage location, also known as any
memory address, can be accessed directly. Originally, the term Random Access Memory was used to distinguish
regular core memory from offline memory.
 Offline memory typically referred to magnetic tape from which a specific piece of data could only be accessed by
locating the address sequentially, starting at the beginning of the tape. RAM is organized and controlled in a way
that enables data to be stored and retrieved directly to and from specific locations.
 Other types of storage -- such as the hard drive and CD-ROM-- are also accessed directly or randomly, but the
term random access isn't used to describe these other types of storage.
 RAM is similar in concept to a set of boxes in which each box can hold a 0 or a 1. Each box has a unique address
that is found by counting across the columns and down the rows. A set of RAM boxes is called an array, and each
box is known as a cell.
 To find a specific cell, the RAM controller sends the column and row address down a thin electrical line etched
into the chip. Each row and column in a RAM array has its own address line. Any data that's read flows back on a
separate data line.
 RAM is physically small and stored in microchips. It's also small in terms of the amount of data it can hold. A
typical laptop computer may come with 8 gigabytes of RAM, while a hard disk can hold 10 terabytes.
RAM comes in two primary forms:
 Dynamic Random Access Memory (DRAM) makes up the typical computing device's RAM
and, as was previously noted, it needs that power to be on to retain stored data.
 Each DRAM cell has a charge or lack of charge held in an electrical capacitor. This data must
be constantly refreshed with an electronic charge every few milliseconds to compensate for
leaks from the capacitor. A transistor serves as a gate, determining whether a capacitor's value
can be read or written.
 Static Random Access Memory (SRAM) also needs constant power to hold on to data, but it
doesn't need to be continually refreshed the way DRAM does.
 In SRAM, instead of a capacitor holding the charge, the transistor acts as a switch, with one
position serving as 1 and the other position as 0. Static RAM requires several transistors to
retain one bit of data compared to dynamic RAM which needs only one transistor per bit. As a
result, SRAM chips are much larger and more expensive than an equivalent amount of DRAM.
One-transistor RTL NOR gate
Multi-transistor RTL NOR gate
 Resistor–transistor logic (RTL) (sometimes also transistor–resistor logic (TRL)) is a class of digital
circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching
devices. RTL is the earliest class of transistorized digital logic circuit used; other classes include diode–
transistor logic (DTL) and transistor–transistor logic (TTL). RTL circuits were first constructed
with discrete components, but in 1961 it became the first digital logic family to be produced as
a monolithic integrated circuit.
 The logical operation OR is performed by applying consecutively the two arithmetic
operations addition and comparison (the input resistor network acts as a parallel voltage summer with
equally weighted inputs and the following common-emitter transistor stage as a voltage
comparator with a threshold about 0.7 V). The equivalent resistance of all the resistors connected to
logical "1" and the equivalent resistance of all the resistors connected to logical "0" form the two legs
of a composed voltage divider driving the transistor. The base resistances and the number of the inputs
are chosen (limited) so that only one logical "1" is sufficient to create base-emitter voltage exceeding
the threshold and, as a result, saturating the transistor. If all the input voltages are low (logical "0"), the
transistor is cut-off. The pull-down resistor R1 biases the transistor to the appropriate on-off threshold.
The output is inverted since the collector-emitter voltage of transistor Q1 is taken as output, and is high
when the inputs are low. Thus, the analog resistive network and the analog transistor stage perform the
logic function NOR
Advantages
 The primary advantage of RTL technology was that it used a minimum number of
transistors. In circuits using discrete components, before integrated circuits, transistors were
the most expensive component to produce. Early IC logic production (such as Fairchild's in
1961) used the same approach briefly, but quickly transitioned to higher-performance
circuits such as diode–transistor logic and then transistor–transistor logic (starting in 1963
at Sylvania Electric Products), since diodes and transistors were no more expensive than
resistors in the IC.
Limitations
 The disadvantage of RTL is its high power dissipation when the transistor is switched on, by
current flowing in the collector and base resistors. This requires that more current be
supplied to and heat be removed from RTL circuits. In contrast, TTL circuits with "totem-
pole" output stage minimize both of these requirements.
 Another limitation of RTL is its limited fan-in: 3 inputs being the limit for many circuit
designs, before it completely loses usable noise immunity. [citation needed] It has a low noise
margin. Lancaster says that integrated circuit RTL NOR gates (which have one transistor
per input) may be constructed with "any reasonable number" of logic inputs, and gives an
example of an 8-input NOR gate.
 DTL was initially made with discrete transistors and resistors before being integrated onto silicon.
 One early form of DTL, used by IBM Corp in the 360 family of computers, was really a hybrid technology.
 Transistor and diode chips were glued to a ceramic substrate and aluminum resistor paste was deposited on the
substrate to make resistors.
 Finally the ceramic base and components were hermetically sealed in an aluminum can. This family was used
extensively in IBM products in the middle to late 1960's.
 While this family was not a true integrated circuit, it was very successful and was less expensive than true
integrated circuits for several years.
 By the early 1970's integrated circuits became quite common and DTL gave way to TTL which was more
appropriate to integrated circuit technology.
 While DTL is no longer commercially used, we will discuss it because it is similar to and easier to understand
than TTL, and because designers still find the configuration of value.
 First, however, we will discuss diode logic which is the front end of the DTL gate and performs the actual
logic operation.
 Transistor–transistor logic (TTL) is a logic family built from bipolar junction transistors. Its
name signifies that transistors perform both the logic function (the first "transistor") and the
amplifying function (the second "transistor"), as opposed to resistor–transistor logic (RTL)
or diode–transistor logic (DTL).
 TTL integrated circuits (ICs) were widely used in applications such as computers, industrial
controls, test equipment and instrumentation, consumer electronics, and synthesizers.
Sometimes TTL-compatible logic levels are not associated directly with TTL integrated
circuits, for example, they may be used at the inputs and outputs of electronic instruments.
 After their introduction in integrated circuit form in 1963 by Sylvania Electric Products, TTL
integrated circuits were manufactured by several semiconductor companies. The 7400
series by Texas Instruments became particularly popular. TTL manufacturers offered a wide
range of logic gates, flip-flops, counters, and other circuits. Variations of the original TTL
circuit design offered higher speed or lower power dissipation to allow design optimization.
TTL devices were originally made in ceramic and plastic dual in-line package(s) and in flat-
pack form. Some TTL chips are now also made in surface-mount technology packages.
 The ECL circuit operation is considered below with assumption that the
input voltage is applied to T1 base, while T2 input is unused or a logical
"0" is applied.
 During the transition, the core of the circuit – the emitter-coupled pair (T1
and T3) – acts as a differential amplifier with single-ended input. The
"long-tail" current source (RE) sets the total current flowing through the
two legs of the pair.
 The input voltage controls the current flowing through the transistors by
sharing it between the two legs, steering it all to one side when not near
the switching point.
 The gain is higher than at the end states (see below) and the circuit
switches quickly.
  The metal-oxide (SiO2)-semiconductor (Si) is the most common microelectronic structures nowadays. The two terminals of MOS-
Capacitor consist of the main structures in MOS devices and it is the simplest structure of MOS devices. Therefore, it's essential to
understand the mechanisms and characteristics of how MOS-C operates. The mechanisms under static biasing conditions can be
visualized from two diagrams.
Energy band diagram
Block-charge diagram
The characteristics of MOS-C can be visualized by C-V (Capacitance verses Voltage) curves.
 Introduction
 The principals of forming MOS structure are similar to the metal-semiconductor (MS) contact structures, but the MOS structure is like
sandwich structures which have a thin layer of silicon oxides in the middle between metal and semiconductor (Si) layer. Figure 1 below
shows a schematic of an ideal MOS-C device. For an ideal MOS-C structure, some properties should follow below.
The metallic gate should thick enough to be equipotential region, where every points has the same potential in the space, under a.c and d.c
biasing conditions. The oxides layer in the middle should be a perfect insulator with zero current flowing through under all static biasing
conditions. There should be no charge centers located on the oxide-semiconductor interface. The semiconductor should be uniformly doped
with donors or acceptors as p-type or n-type semiconductors. The semiconductor (Si) should be thick enough for charges to encounter a field
free region (Si bulk) before reaching the back contact. The Ohmic contacts should be established on the backside of the MOS device.
The schematic of an ideal MOS-C device
Energy Band and Block Charge Diagrams

The flat band diagram of MOS-C in Capacitance verses voltage of

equilibrium with n-type MOS-C device for n-type
semiconductor, (b) the block charge semiconductor.
diagrams of flat band MOS-C.

Accumulation of n-type MOS devices (a)

band diagram (b) block charge diagram

Accumulation of n-type MOS devices (a) band diagram (b) block

charge diagram
CMOS Inverter
 CMOS circuits are constructed in such a way that all P-type metal–oxide–semiconductor (PMOS)
transistors must have either an input from the voltage source or from another PMOS transistor.
 Similarly, all NMOS transistors must have either an input from ground or from another NMOS
transistor. The composition of a PMOS transistor creates low resistance between its source and drain
contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied.
 On the other hand, the composition of an NMOS transistor creates high resistance between source
and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.
 CMOS accomplishes current reduction by complementing every NMOSFET with a PMOSFET and
connecting both gates and both drains together. A high voltage on the gates will cause the NMOSFET
to conduct and the PMOSFET not to conduct, while a low voltage on the gates causes the reverse.
 This arrangement greatly reduces power consumption and heat generation. However, during the
switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another.
 This induces a brief spike in power consumption and becomes a serious issue at high frequencies.
 TOGGLE SPEED POWER PER GATE @ TYPICAL SUPPLY INTRODUCTION
FAMILY DESCRIPTION PRPOGATION DELAY (ns) REMARKS
(MHZ) 1MHZ (mw) VOLTAGE RANGE YEAR

3.3 or 5 (2-6 or 4.5-

CMOS AC/ACT 3 125 0.5 1985 ACT has TTL compatible levels
5.5)

CMOS HC/HCT 9 50 0.5 5 (2-6 or 4.5-5.5) 1982 HCT has TTL compatible levels

Approximately half speed and

CMOS 4000B/74C 30 5 1.2 10V (3-18) 1970
power at 5 volts

Introduced by Signetics, Fairchild

DTL Diode–transistor logic 25 10 5 1962 930 line became industry
standard in 1964

ECL ECL III 1 500 60 -5.2(-5.19 - -5.21) 1968 Improved ECL

first integrated logic circuit

ECL MECL I 8 31 -5.2 1962
commercially produced

ECL ECL 10K 2 125 25 -5.2(-5.19 - -5.21) 1971 Motorola

ECL ECL 100K 0.75 350 40 -4.5(-4.2 - -5.2) 1981

ECL ECL 100KH 1 250 25 -5.2(-4.9 - -5.5) 1981

PMOS MEM 1000 300 1 9 -27 and -13 1967 Introduced by General Instrument

the first CPU built from

RTL Resistor–transistor logic 500 4 10 3.3 1963 integrated circuits (the Apollo
Guidance Computer) used RTL.

TTL Original series 10 25 10 5 (4.75-5.25) 1964 Several manufacturers

TTL L 33 3 1 5 (4.75-5.25) 1964 Low power

TTL H 6 43 22 5 (4.75-5.25) 1964 High speed

TTL S 3 100 19 5 (4.75-5.25) 1969 Schottky high speed

TTL LS 10 40 2 5 (4.75-5.25) 1976 Low power Schottky high speed

TTL ALS 4 50 1.3 5 (4.5-5.5) 1976 Advanced Low power Schottky

TTL F 3.5 100 5.4 5 (4.75-5.25) 1979 Fast

TTL AS 2 105 8 5 (4.5-5.5) 1980 Advanced Schottky

TTL G 1.5 1125 (1.125 GHz) 1.65 - 3.6 2004 First GHz 7400 series logic

TTL Original series 10 25 10 5 (4.75-5.25) 1964 Several manufacturers

TTL L 33 3 1 5 (4.75-5.25) 1964 Low power

TTL H 6 43 22 5 (4.75-5.25) 1964 High speed

TTL S 3 100 19 5 (4.75-5.25) 1969 Schottky high speed

TTL LS 10 40 2 5 (4.75-5.25) 1976 Low power Schottky high speed

TTL ALS 4 50 1.3 5 (4.5-5.5) 1976 Advanced Low power Schottky

TTL F 3.5 100 5.4 5 (4.75-5.25) 1979 Fast

TTL AS 2 105 8 5 (4.5-5.5) 1980 Advanced Schottky

TTL G 1.5 1125 (1.125 GHz) 1.65 - 3.6 2004 First GHz 7400 series logic

the first CPU built from integrated

RTL Resistor–transistor logic 500 4 10 3.3 1963 circuits (the Apollo Guidance
Computer) used RTL.

PMOS MEM 1000 300 1 9 -27 and -13 1967 Introduced by General Instrument

ECL ECL III 1 500 60 -5.2(-5.19 - -5.21) 1968 Improved ECL

first integrated logic circuit

ECL MECL I 8 31 -5.2 1962
commercially produced