GOVERNMENT POLYTECHNIC, AHEMDABAD

EC DEPARTMENT
6th SEM
Subject : VLSI Subject Code :- 3361104
Lecture Notes for CH-1
Q-1 What is VLSI ?

 Very Large Scale Integration

 100s of thousands of transistors on a single integrated circuits or chip
 Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands
of transistors into a single chip.
 VLSI began in the 1970s when Complex semiconductor and communication technologies were being
developed.
 The microprocessor is a VLSI device.
 Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform.
An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of
these into one chip.
 The current cutting-edge technologies such as high resolution and low bit-rate video and cellular
communications provide the end-users a marvelous amount of applications, processing power and portability.
This trend is expected to grow rapidly, with very important implications on VLSI design and systems design.

Q-2 Write advantages and Disadvantages of VLSI

 Advantages :- 1. Smaller Size 2. Lower Cost 3. Lower Power Consumption 4. Higher Reliability 5. More
Functionality
 Disadvantages :- 1. Long design and Fabrication Time 2. Higher risk to project

Q-3 What are four generations of Integration Circuits?

 SSI (Small Scale Integration)

 MSI (Medium Scale Integration)
 LSI (Large Scale Integration)
 VLSI (Very Large Scale Integration)

Q -4 Explain VLSI Design Flow with Y Chart

 The design process, at various levels, is usually evolutionary in nature.
 It starts with a given set of requirements.
 Initial design is developed and tested against the requirements.
 When requirements are not met, the design has to be improved.
 If such improvement is either not possible or too costly, then the revision of requirements and its impact
analysis must be considered.
 The Y-chart (first introduced by D. Gajski) shown in Fig. 1.4 illustrates a design flow for most logic chips, using
design activities on three different domains which resemble the letter Y.

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  The Y-chart consists of three major domains, namely:

1. Behavioral domain,
2. Structural domain,
3. Geometrical layout domain.

 The design flow starts from the algorithm that describes the behavior of the target chip.
 The corresponding architecture of the processor is first defined.
 It is mapped onto the chip surface by floorplanning of Chip .
 The next design evolution in the behavioral domain defines finite state machines.
 Finite state Machines are structurally implemented with functional modules such as registers and arithmetic
logic units (ALUs).
 These modules are then geometrically placed onto the chip surface using CAD tools for automatic module
placement followed by routing, with a goal of minimizing the interconnects area and signal delays.
 The third evolution starts with a behavioral module description.
 Individual modules are then implemented with leaf cells(Logic Cells).
 Then logic gates which can be placed and interconnected by using a cell placement & routing program.
 The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level
implementation of leaf cells and mask generation.

In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use.

Q-5 Draw and Explain simplified VLSI design Flow

 The VLSI IC circuits design flow is shown in the figure below.

 The various levels of design are numbered and the blocks show processes in the design flow.
 Specifications comes first, they describe abstractly, the functionality, interface, and the architecture of the
digital IC circuit to be designed.
 Behavioral description is then created to analyze the design in terms of functionality, performance,
compliance to given standards, and other specifications.

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  RTL description is done and simulated to test functionality.
 RTL description is then converted to a gate-level netlist A gatelevel netlist is a description of the circuit in
terms of gates and connections between them, which are made in such a way that they meet the timing,
power and area specifications.
Finally, a physical layout is made, which will be verified and then sent to fabrication.

 Above figure provides a more simplified view of the VLSI design flow, taking into account the various
representations, or abstractions of design - behavioral, logic, circuit and mask layout.
 Note that the verification of design plays a very important role in every step during this process.
 The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a
later stage, which ultimately increases the time-to-market.
 Although the design process has been described in linear fashion for simplicity, in reality there are many
iterations back and forth, especially between any two neighboring steps, and occasionally even remotely
separated pairs.
 Although top-down design flow provides an excellent design process control, in reality, there is no truly
unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined.
 For instance, if a chip designer defined architecture without close estimation of the corresponding chip area,
then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a
case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and
the design process must be repeated.
 Such changes may require significant modification of the original requirements.

Q -6 Explain Design Hierarchy with example

 The design hierarchy involves the principle of "Divide and Conquer."

 It is nothing but dividing the task into smaller tasks until it reaches to its simplest level.

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  This process is most suitable because the last evolution of design has become so simple that its manufacturing
becomes easier.
 This technique involves dividing a module into sub- modules and then repeating this operation on the sub-
modules until the complexity of the smaller parts becomes manageable.
 This approach is very similar to the software case where large programs are split into smaller and smaller
sections until simple subroutines, with well-defined functions and interfaces can be written.
 As an example of structural hierarchy, Fig. 1 shows the structural decomposition of a CMOS four-bit adder into
its components.
 Here, the whole chip of 16 bit adder is divided into four modules of 4-bit adders.
 Further, dividing the 4-bit adder into 1-bit adder or half adder.
 1 bit addition is the simplest designing process and its internal circuit (which can be realized by simple Boolean
function) is also easy to fabricate on the chip.
 Now, connecting all the last four adders, we can design a 4-bit adder and moving on, we can design a 16-bit
adder
 Figure 2. shows the hierarchical decomposition of a four-bit adder in physical domain (geometrical layout) ,
resulting in a simple floorplan.
 This physical view describes the external geometry of the adder, the locations of input and output pins, and
how pin locations allow some signals (in this case the carry signals) to be transferred from one sub-block to the
other without external routing.

Figure-1: Structural decomposition of a four-bit adder circuit

Figure-2: Hierarchical decomposition of a four-bit adder in geometrical domain.

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Q-7 Write Short note on Field Programmable Gate Array (FPGA)
 The full form of FPGA is “Field Programmable Gate Array”.
 It contains ten thousand to more than a million logic gates with programmable interconnection.
 Programmable interconnections are available for users or designers to perform given functions easily.
 This design style provides a means for fast prototyping and also for cost-effective chip design, especially for
low-volume applications.
 A typical field programmable gate array (FPGA) chip consists of
(1) I/O buffers,
(2) an array of configurable logic blocks (CLBs), and
(3) Programmable interconnect structures.

1. Configurable logic blocks (CLBs)

 CLB performs the logic operation given to the module
 CLB can be Independent combinational function generator,Clock signal terminal, Flip Flop or User –
Programmable multiplexer
 Number of CLB determines the complexity of FPGA chip

2. The programming of the interconnects

 The inter connection between CLB and I/O blocks are made with the help of horizontal routing channels,
vertical routing channels and PSM (Programmable Multiplexers).
 It is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS
pass transistors.
CLB performs the logic operation given to the module. The number of CLB it contains only decides the complexity of
FPGA. The functionality of CLB’s and PSM are designed by VHDL or any other hardware descriptive language. After
programming, CLB and PSM are placed on chip and connected with each other with routing channels.
Advantages
 It requires very small time; starting from design process to functional chip.
 No physical manufacturing steps are involved in it.
 The only disadvantage is, it is costly than other styles
Design Flow of FPGA
1. Behavioral description of its functionality (using a hardware description language such as VHDL)
2. Technology-mapped (or partitioned) into circuits or logic cells (At this stage, the chip design is completely
described in terms of available logic cells)
3. Assign individual logic cells to CLBs and determines the routing pattern among the cells in accordance with the
netlist.

A general architecture of FPGA from XILINX is shown in Fig. 1.12. A more detailed view showing the locations of switch
matrices used for interconnect routing is given in Fig. 1.13.

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 Figure-1.12: General architecture of Xilinx FPGAs.

Figure-1.13: Detailed view of switch matrices and interconnection routing between CLBs.

Q-8 Write short note on Gate Array Design

 The gate array (GA) ranks second after the FPGA, in terms of fast prototyping capability.
 While the design implementation of the FPGA chip is done with user programming, that of the gate array is
done with metal mask design and processing.
 Gate array implementation requires a two-step manufacturing process:
1. The first phase, which is based on standard masks, results in an array of uncommitted transistors
on each GA chip. These uncommitted chips can be stored for later customization
2. In the Second Phase, the uncommitted chips are customized by defining the metal interconnects
between the transistors of the array (Fig. 1.15). Since the patterning of metallic interconnects is
done at the end of the chip fabrication, the turn-around time can be still short, a few days to a few
weeks.

 Advantage :-
 For Gate Array Design, chip utilization factor ( used chip area/ total chip area)is higher than that of the FPGA
and so chip speed is high.
 since more customized design can be achieved with metal mask designs.

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  The current gate array chips can implement as many as hundreds of thousands of logic gates.

Q-9 Write short note on Standard cell-based Design

 The standard-cells based design is one of the most prevalent full custom design styles which require
development of a full custom mask set.
 The standard cell is also called the polycell.
 In this design style, all of the commonly used logic cells are developed, characterized, and stored in a standard
cell library.
 A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI
gates, D-latches, and flip-flops.
 Each gate type can have multiple implementations to provide adequate driving capability for different fanouts.
 For instance, the inverter gate can have standard size transistors, double size transistors, and quadruple size
transistors so that the chip designer can choose the proper size to achieve high circuit speed and layout
density.
 The characterization of each cell is done for several different categories. It consists of

1. delay time vs. load capacitance

2. circuit simulation model
3. timing simulation model
4. fault simulation model
5. cell data for place-and-route
6. mask data

 To enable automated placement of the cells and routing of inter-cell connections, each cell layout is designed
with a fixed height, so that a number of cells can be abutted side-by-side to form rows.
 The power and ground rails typically run parallel to the upper and lower boundaries of the cell, thus,
neighboring cells share a common power and ground bus.
 The input and output pins are located on the upper and lower boundaries of the cell.
 Generally the nMOS transistors are located closer to the ground rail while the pMOS transistors are placed
closer to the power rail
 Figure shows a floorplan for standard-cell based design.
 The physical design and layout of logic cells ensure that when cells are placed into rows, their heights are
matched and neighboring cells can be abutted side-by-side, which provides natural connections for power and
ground lines in each row.
 The signal delay, noise margins, and power consumption of each cell should be also optimized with proper
sizing of transistors using circuit simulation.
 If a number of cells must share the same input and/or output signals, a common signal bus structure can also
be incorporated into the standard-cell-based chip layout.
 Standard-cell based designs may consist of several such macro-blocks, each corresponding to a specific unit of
the system architecture such as ALU, control logic, etc.
 After chip logic design is done using standard cells in the library, the most challenging task is to place individual
cells into rows and interconnect them in a way that meets stringent design goals in circuit speed, chip area, and
power consumption.
 Many advanced CAD tools for place-and-route have been developed and used to achieve such goals.
 For timing critical paths, proper gate sizing is often practiced to meet the timing requirements.
 In many VLSI chips, such as microprocessors and digital signal processing chips, standard-cells based design is
used to implement complex control logic modules.
 Some full custom chips can be also implemented exclusively with standard cells.

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 Figure : A simplified floorplan of standard-cells-based design.

Q-10 Write Short Note on Full Custom Design

 Although the standard-cells based design is often called full custom design, in a strict sense, it is somewhat less
than fully custom since the cells are pre-designed for general use and the same cells are utilized in many different
chip designs.
 In a full-custom design, the entire mask design is made new, without the use of any library.
 The development cost of this design style is High.
 So the concept of design reuse is becoming famous to reduce design cycle time and development cost.
 In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually
by the designer, design productivity is usually very low - typically 10 to 20 transistors per day, per designer.
 In digital CMOS VLSI, full-custom design is hardly used due to the high labor cost.
 These design styles include the design of high-volume products such as memory chips, high-performance
microprocessors and FPGA.
 For logic chip design, a good negotiation can be obtained using a combination of different design styles on the
same chip.

Q-11 Give comparison between full custom and semi-custom design

FULL CUSTOM DESIGN SEMI CUSTOM DESIGN

It uses pre-designed logic cell(and gates, OR gate,

All mask layers are customized in full custom design multiplexers) known as standard cells.

In full custom design, all logic cells, circuits or layouts are

designed specifically. Design doesn't use pretested or pre-
characterized cells. Designer used pre-tested or pre-characterized cell.

This approach is considered only when there is no suitable Widely used

existing

Offers high performance lower cost as compared to semi. More cost. Low performance.

Design time and complexity is more. Design time and complexity is less

Eg: Microprocessor Eg. Digital logics

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 GOVERNMENT POLYTECHNIC, AHEMDABAD
EC DEPARTMENT
6th SEM
Subject : VLSI Subject Code :- 3361104
Lecture Notes for CH-1

Q-1 Explain MOS Structure with necessary diagram/ Explain Energy Band Diagram for MOS

[A] MOS LAYER :-

The MOS(Metal-Oxide-Semiconductor) Structure consist of 3 layers

As shown in the figure, MOS structure contains three layers −

1. The Metal Gate Electrode

2. The Insulating Oxide Layer (SiO2)

3. P – type Semiconductor (Substrate)

 MOS structure forms a capacitor, with gate and substrate are as two plates and oxide layer as the dielectric
material.
 The thickness of dielectric material (SiO2) is usually between 10 nm and 50 nm.
 Carrier concentration and distribution within the substrate can be manipulated by external voltage applied
to gate and substrate terminal.
[B] Basic electric properties of P – Type semiconductor substrate. :-
 Concentration of carrier in semiconductor material is always following the Mass Action Law.

 Mass Action Law is given by – n.p = ni2 , Where n= electron carrier concentration
P = Holes carrier concentration
ni = intrinsic carrier concentration of Silicon
 Assume, Substrate is uniformly doped with acceptor (p-type) concentration, So, electron and hole
concentration in p–type substrate is
npo = ni2 / NA & Ppo = NA
 Here, doping concentration NA is (1015 to 1016 cm−3) greater than intrinsic concentration ni.

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 [ C] Energy Band Diagram of MOS
(1) Energy ;Band Diagram of P type Si Substrate

 As shown in the figure, the band gap between conduction band and valance band is 1.1eV.
 Fermi potential ΦF = (Ei - EFp)/q (Potential diff. between Intrinsic Fermi level and bulk Fermi level)

 Electron affinity (qx.) :- The potential difference between conduction band and free space
 Work Function (qΦS) :- Energy required for an electron to move from Fermi level to free space is called work
function

(2) Energy Band diagram of MOS System ( Metal, Oxide, Semiconductor as separate components)
 The following figure shows the energy band diagram of components that make up the MOS.

 As shown in the above figure, insulating SiO2 layer has large energy band gap of 8eV and work function is 0.95
eV.
 Metal gate has work function of 4.1eV.
 Here, the work functions are different so it will create voltage drop across the MOS system.

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(3) Energy Band diagram of Combined MOS System
The figure given below shows the combined energy band diagram of MOS system.

 As shown in this figure, the Fermi potential level of metal gate and semiconductor (Si) are at same
potential. (Efp = Efm)
 Fermi potential at surface is called surface potential ΦS and it is smaller than Fermi potential ΦF in
magnitude.

Q-2 Explain with neat sketch Mos System under external bias

 In MOS there is an oxide layer below the Gate terminal. Since oxide is a very good insulator, it contributes to
an oxide capacitance in the circuit.
 Normally, the capacitance value of a capacitor doesn't change with values of voltage applied across its
terminals.
 However, this is not the case with MOS capacitor. We find that the capacitance of MOS capacitor changes its
value with the variation in Gate voltage.
 This is because application of gate voltage results in band bending in silicon substrate and hence variation in
charge concentration at Si-SiO2 interface

Modes of operation

Depending upon the value of gate voltage applied, the MOS capacitor works in three modes :

[1] Accumulation: - (Accumulation of holes near the Si-SiO2 interface. )

1. When Vg <0, the holes in p-type substrate are attracted to the semiconductor-oxide interface.
2. There is accumulation of holes (assuming nMOSFET) at the Si-SiO2 interface.
3. The oxide electric field is directed towards the gate electrode.
4. The negative surface potential causes the energy band to bend up-ward near the surface

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 Fig. MOS System under external bias (Accumulation)

[2] Depletion: (Created near the Si-SiO2 interface. ) :-

1. When we apply Vg > 0 (Small), the holes at the interface are repelled and pushed back into the substrate
leaving a depleted layer.
2. These holes will leave negatively charged fixed acceptor ions behind.
3. Thus a depletion region is created near the surface
4. Vg > 0 (Small), and as the substrate bias is zero, the oxide electric field will be directed towards the substrate in
this case.
5. The positive surface potential causes the energy bands to bend downwards near the surface.

Fig. MOS System under external bias (Depletion)

[3] Inversion :- (Si-SiO2 surface is inverted)

1. When we apply Vg > 0 (Large), attracts additional minority carriers(electrons) from the p-type substrate to the
surface.
2. The n-type region created near the surface by the positive gate bias is called the inversion layer and this
condition is called surface inversion.
3. The thin inversion layer on the surface with a large mobile electron concentration can be utilized for conducting
current between two terminals of the MOS transistor.
4. When surface is inverted, the density of mobile electron at the surface is same as the density of the holes in the
p-type substrate.

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 5. Once the surface is inverted, any further increase in Vg cause increase of mobile electron at the surface, but the
depletion depth will remains constant.
6. As Vg > 0 (Large), surface potential increases which cause more downward bending of the energy band.
7. Ei (Mid-gap energy level) < EFP (Fermi Level) on the surface so we can say that in this region, the the p-type si
substrate becomes n-type.

Fig. MOS System under external bias (Inversion)

Q -3 Draw only energy band diagram of MOS system under external bias

Q-4 Why MOSFET is preferred than FET

FETs have a few disadvantages like high drain resistance, moderate input impedance and slower operation. To
overcome these disadvantages, the MOSFET which is an advanced FET is invented. Practically it look likes as shown

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 Q-5 Compare BJT, FET and MOSFET
Now that we have discussed all the above three, let us try to compare some of their properties.

TERMS BJT FET MOSFET

Current Voltage controlled Voltage Controlled

Device type
controlled

Current flow Bipolar Unipolar Unipolar

Not
Terminals Interchangeable Interchangeable
interchangeable

Operational modes No modes Depletion mode only Both Enhancement and Depletion modes

Input impedance Low High Very high

Output resistance Moderate Moderate Low

Operational speed Low Moderate High

Noise High Low Low

Thermal stability Low Better High

Q-6 Explain Structure and operation of MOSFET transistor

 The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semiconductor device which is
widely used for switching and amplifying electronic signals in the electronic devices.
 The MOSFET is a core of integrated circuit and it can be designed and fabricated in a single chip because of
these very small sizes.
 The MOSFET is a four terminal device with source(S), gate (G), drain (D) and body (B) terminals.
 Body of the MOSFET is frequently connected to the source terminal so making it a three terminal device like
field effect transistor.
 The MOSFET is very far the most common transistor and can be used in both analog and digital circuits.

Construction of a MOSFET

 The construction of a MOSFET is a bit similar to the FET.

 It consists of a p-type substrate, in which two n+ diffusion regions, the drain and the source are formed.
 A thin oxide layer is deposited on the substrate
 A metal gate is deposited on the top of this insulator
 This oxide layer acts as an insulator (sio2 insulates from the substrate), and hence the MOSFET has another
name as IGFET.
 Depending upon the substrate used, they are called as P-type and N-type MOSFETs.

 The following figure shows the construction of a MOSFET.

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  The distance between the drain and source regions is called channel length L and the lateral extent of the
channel is channel width W.

Classification of MOSFETs
Depending upon the type of materials used in the construction, and the type of operation, the MOSFETs are classified
as in the following figure

Types of MOSFET

Enhancement MOSFET Depletion MOSFET

* At Zero gate voltage, Conducting channel is not * At Zero gate voltage, Conducting channel is already
exist. exist.
* VTO > 0 * VTO < 0

N - Channel P - Channel N - Channel P - Channel

(substrate is P-type , (substrate is N-type , (substrate is P-type , (substrate is N-type ,
source and drain region source and drain region source and drain region source and drain
are n+) are p+) are n+) region are p+)

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Operation of MOSFET :-
Principle :- Control the current conduction between the source and the drain using the electric field generated by the
gate voltge and Drain Voltage.
(1) Depletion Region :-

 The Source, Drain and Body(Substrate) terminals are connected to ground.

 Small Positive Voltage (< VTO) is applied to Gate terminal. So Channel is created between Source and Drain.
 Due to small VGS, the holes are repelled back into the substrate.
 So the surface of p type substrate is depleted as shown in above figure.
 Hence the current conduction between source and drain is not possible.
(2) Linear Region

 Here we kept VGS >VTO , so inversion layer is established on the surface.

 Hence n-channel is established between source and drain .
 Now we will apply VDS >0 (Small) , ID will flow from source to drain through the channel.
 ID is proportional to VDS. So this is called the linear mode or linear region.
 Here, channel act as a voltage-controlled-resistor.
(3) At the Edge of Saturation Region

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  Here we kept VGS >VTO to establish the channel and will increase VDS.
 As we increase VDS , the inversion layer charge and Channel Depth at the drain end start to decrease.
 For VDS = VDSAT, the inversion charge at the drain end is reduced to zero, which is called pinch-off-
point.

(4) Beyond Saturation Region :-

 Further than the pinch off point, i.e. for VDS > VDSAT, a depleted region forms near to the drain and
extends towards the source with increasing drain voltage.
 This mode is called beyond saturation mode or beyond saturation region
 In this region, the inversion layer near the drain decreases, the effective channel length is reduced.
 The channel end voltage remains constant (=VDSAT)
 So most of the exceed voltage(VDS-VDSAT) will drop across the pinch-off section (between channel-end
and drain) hence high electric field region created there.
 So electrons coming from the source to the channel-end will be entered into the high electric field
region and accelerated toward the drain end.

Q-7 Explain Gradual Channel Approximation/ Explain MOSFET Current-Voltage characteristic

We are modeling the terminal characteristics of a MOSFET and thus want i D(vDS, vGS, vBS), iB(vDS, vGS, vBS), and iG(vDS, vGS,
vBS). We restrict our model to VDS ≥ 0 and VBS ≤ 0, so the diodes at the source and drain are always reverse biased; in this
case iB ≈ 0. Because of the insulating nature of the oxide beneath the gate, we also have i G = 0, and our problem
reduces to finding iD(vDS, vGS, vBS).

it is so named because we assume that the voltages vary gradually along the channel from the drain to the source. At
the same time, they vary quickly perpendicularly to the channel moving from the gate to the bulk semiconductor.

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  Consider that the n-channel MOSFET operating in the linear mode.
 Here VS = VB = 0. VGS and VDS control the drain current ID.
 We have kept VGS > VTO to create a channel between source and drain.
 The x-direction (as shown in above fig.) is perpendicular to surface and y-direction is parallel to the
surface.
 It is assumed that
(1) Threshold voltage VTO is constant along the entire channel length.
(2) Entire channel length between source and drain is inverted.
 The y-coordinate (y=0) is at source end of the channel. So the channel Voltage Vc(y=0) = 0
 The y-coordinate (y=L) is at drain end of the channel and the channel voltage Vc(y=L) =VDS
 Here (1) VGS > VTO and (2) VDS <= VGS-VTO,
 Total total electron charge in the surface inversion layer is
Q(y) = - COX . [VGS-VC(y)-VTO]-----------------------------------------Eq-I

 Now consider the geometry of channel region as shown in below figure.

 Let us take a small region of dy length of channel as shown in figure

 The incremental resistance offered by this region is
dR = - dy/(WμnQ(y)) (Negative sign is due to polarity of inversion layer charge)—Eq-2
μn = constant surface mobility
 Put value of Eq-1 into Eq-2,
dR = dy/( COX W μn [VGS-VC(y)-VTO ])
 As per the ohm’s law, dVc = Id dR, so
dVc = Id dy/( COX W μn [VGS-VC(y)-VTO ])
 Now to obtain the ID current over the whole channel region, we will integrate along y=0 to y=L and over
the channel voltage Vc(y) = 0 to Vc(y)=VDS
𝐿 VDS
∫𝑦=0 Id 𝑑𝑦 = COX W μn ∫VC=0(VGS − VTO − VC(y)) dVc

 Hence for Linear Region (i.e. VDS <= VGS-VTO),

𝑾
Id = μn COX [2 (VGS-VTO)VDS - VDS2 ] -------------------------------Eq-3
𝑳

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  For Saturation Region :- (i.e. VDS > VGS-VTO),
Substitute VDS = VGS-VTO in equa-3,

𝛍𝐧 𝐂𝐎𝐗 𝑾
Id(Sat) = (VGS –VTO)2
𝟐 𝑳

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 GOVERNMENT POLYTECHNIC, AHEMDABAD
EC DEPARTMENT
6th SEM
Subject : VLSI Subject Code :- 3361104
Lecture Notes for CH-2

Q-1 Explain the working of MOS Inverter

Principle of Operation

The logic symbol and truth table of ideal inverter is shown in figure given below. Here A is the input and B is the
inverted output represented by their node voltages. Using positive logic, the Boolean value of logic 1 is represented by
Vdd and logic 0 is represented by 0. Vth is the inverter threshold voltage, which is V dd /2, where Vdd is the output
voltage.
The output is switched from 0 to Vdd when input is less than Vth. So, for 0<Vin<Vth output is equal to logic 0 input and
Vth<Vin< Vdd is equal to logic 1 input for inverter.

The characteristics shown in the figure are ideal. The generalized circuit structure of an nMOS inverter is shown in the
figure below.

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From the given figure, we can see that the input voltage of inverter is equal to the gate to source voltage of nMOS
transistor and output voltage of inverter is equal to drain to source voltage of nMOS transistor. The source to substrate
voltage of nMOS is also called driver for transistor which is grounded; so VSS = 0. The output node is connected with a
lumped capacitance used for VTC.

Q-2 Explain operation of resistive load inverter

The basic structure of a resistive load inverter is shown in the figure given below. Here, enhancement type nMOS acts
as the driver transistor. The load consists of a simple linear resistor R L. The power supply of the circuit is VDD and the
drain current ID is equal to the load current IR.

Circuit Operation
When the input of the driver transistor is less than threshold voltage VTH (Vin < VTH), driver transistor is in the cut – off
region and does not conduct any current. So, the voltage drop across the load resistor is ZERO and output voltage is
equal to the VDD. Now, when the input voltage increases further, driver transistor will start conducting the non-zero
current and nMOS goes in saturation region.
Mathematically,
𝐾𝑛
ID = 2
[VGS − VTO]2

Increasing the input voltage further, driver transistor will enter into the linear region and output of the driver
transistor decreases.
𝐾𝑛
ID= 2[VGS − VTO]2 𝑉𝐷𝑆
2

VTC of the resistive load inverter, shown below, indicates the operating mode of driver transistor and voltage points.

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The various operating regions of the driver transistor and the corresponding input-output conditions are listed in the
following table. Following Table shows Operating regions of the driver transistor in the resistive-load inverter

Input Voltage Range Operating Mode

Vin < VTO Cut-off

VTO < Vin < VOUT + VTO Saturation

Vin > VOUT + VTO Linear

Table : Operating region of driver transistor in the resistive load inverter

The five critical voltage points, which determine the steady-state input-output behavior of the inverter are
VOL = VDD
VOH =
1
VIL = VIL = VTO +
𝐾𝑛𝑅𝐿
VIH =

Q-3 Describe inverter circuit with saturated and Linear Enhancement type load.

The main advantage of using MOSFET as load device is that the silicon area occupied by the transistor is smaller than
the area occupied by the resistive load. Here, MOSFET is active load and inverter with active load gives a better
performance than the inverter with resistive load.

Enhancement Load NMOS

Two inverters with enhancement-type load device are shown in the figure. Load transistor can be operated either, in
saturation region or in linear region, depending on the bias voltage applied to its gate terminal. The saturated
enhancement load inverter is shown in the fig. (a). It requires a single voltage supply and simple fabrication process
and so VOH is limited to the VDD − VT.

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The linear enhancement load inverter is shown in the fig. (b). It always operates in linear region; so V OH level is equal
to VDD.
Linear load inverter has higher noise margin compared to the saturated enhancement inverter. But, the disadvantage
of linear enhancement inverter is, it requires two separate power supply and both the circuits suffer from high power
dissipation. Therefore, enhancement inverters are not used in any large-scale digital applications.

Q-5 Compare enhancement load NMOS and Depletion Load NMOS.

------self Assignment---------------

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Q -6 Describe inverter circuit with Depletion type load.

Depletion Load NMOS

Drawbacks of the enhancement load inverter can be overcome by using depletion load inverter. Compared to
enhancement load inverter, depletion load inverter requires few more fabrication steps for channel implant to adjust
the threshold voltage of load.
The advantages of the depletion load inverter are - sharp VTC transition, improved switching speed ,better noise
margin, single power supply and smaller overall layout area.
As shown in the figure, the gate and source terminal of load are connected; So, V GS = 0. Thus, the threshold voltage of
the load is negative. Hence,
VGS,load > VT,load

is satisfied
Therefore, load device always has a conduction channel regardless of input and output voltage level.
When the load transistor is in saturation region, the load current is given by
ID,load=Kn,load2[−VT,load(Vout)]2ID,load=Kn,load2[−VT,load(Vout)]2

When the load transistor is in linear region, the load current is given by

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ID,load=Kn,load2[2|VT,load(Vout)|.(VDD−Vout)−(VDD−Vout)2]ID,load=Kn,load2[2|VT,load(Vout)|.(VDD−Vout)−(VDD−V
out)2]

The voltage transfer characteristics of the depletion load inverter is shown in the figure given below −

Q-7 Explain CMOS Inverter with Different Operating Modes of nMOS and pMOS transistor.

CMOS Inverter – Circuit, Operation and Description

The CMOS inverter circuit is shown in the figure. Here, nMOS and pMOS transistors work as driver transistors; when
one transistor is ON, other is OFF.

This configuration is called complementary MOS (CMOS). The input is connected to the gate terminal of both the
transistors such that both can be driven directly with input voltages. Substrate of the nMOS is connected to the
ground and substrate of the pMOS is connected to the power supply, VDD.
So VSB = 0 for both the transistors.
VGS,n = Vin

VDS,n = Vout And,

VGS,p = Vin−VDD

VDS,p = Vout−VDD

 When the input of nMOS is smaller than the threshold voltage (Vin < VTO,n), the nMOS is cut – off and pMOS is in
linear region. So, the drain current of both the transistors is zero.
ID,n = ID,p = 0

Therefore, the output voltage VOH is equal to the supply voltage.

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Vout = VOH =VDD

 When the input voltage is greater than the VDD + VTO,p, the pMOS transistor is in the cutoff region and the nMOS is
in the linear region, so the drain current of both the transistors is zero.
ID,n = ID,p = 0

Therefore, the output voltage VOL is equal to zero.

Vout = VOL = 0
 The nMOS operates in the saturation region if Vin > VTO and if following conditions are satisfied.
VDS,n ≥ VGS,n −VTO,n

Vout ≥ Vin−VTO,n

 The pMOS operates in the saturation region if Vin < VDD + VTO,p and if following conditions are satisfied.
VDS,p ≤ VGS,p − VTO,p

Vout ≤ Vin−VTO,p

For different value of input voltages, the operating regions are listed below for both transistors.

Region Vin Vout nMOS pMOS

A < VTO, n VOH Cut – off Linear

B VIL High ≈ VOH Saturation Linear

C Vth Vth Saturation Saturation

D VIH Low ≈ VOL Linear Saturation

E > (VDD + VTO, p) VOL Linear Cut – off

The VTC of CMOS is shown in the figure below −

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Q- Describe the working of Cascaded stages

VLSI Interview Questions and Answers

Q-1 Give the variety of Integrated Circuits ?

1. More specialized Circuits

2. Application Specific Integrated Circuits (ASICs)
3. System on-chip

2. Define noise Margin? (Remember)

Noise margin represents the amount of noise voltage on the input of a gate so that the output will not be corrupted. It
is closely relate to the dc characteristics. and it is also known as noise immunity.

Noise Margin
Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of
circuit. Noise margin does makes sure that any signal which is logic ‘1’ with finite noise added to it, is still recognized as
logic ‘1’ and not logic ‘0’. It is basically the difference between signal value and the noise value. Refer to the diagram
below.

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Consider the following output characteristics of a CMOS inverter. Ideally, When input voltage is logic ‘0’, output voltage
is supposed to logic ‘1’. Hence Vil (V input low) is ‘0’V and Voh (V output high) is ‘Vdd’V.
Vil = 0
Voh = Vdd
Ideally, when input voltage is logic ‘1’, output voltage is supposed to be at logic ‘0’. Hence, Vih (V input high) is ‘Vdd’,
and Vol (V output low) is ‘0’V.
Vih = Vdd
Vol = 0
Noise Margins could be defined as follows :
NMl (NOISE MARGIN low) = Vil – Vol = 0 – 0 = 0
NMh (NOISE MARGIN high) = Voh – Vih = Vdd – Vdd = 0

But due to voltage droop and ground bounce, Vih is usually slightly less than Vdd i.e. Vdd’, whereas Vil is slightly higher
that Vss i.e. Vss’.
Hence Noise margins for a practical circuit is defined as follows :

NMl (NOISE MARGIN low) = Vil – Vol = Vss’ – 0 = Vss’

NMh (NOISE MARGIN high) = Voh – Vih = Vdd – Vdd’

Hence, if input voltage (Vin) lies somewhere between Vol and Vil, it would be detected as logic ‘0’, and would result in
an output which is acceptable. Similarly, if input voltage (Vin) lies between Vih and Voh, it would be detected as logic
‘1’ and would result in an output which is acceptable.

Q-3 What is meant by body effect?(Remember)

Vth is not constant with respect to voltage difference between substrate and source of transistor. This is known as
body effect. It is otherwise known as substrate-bias effect.

Q-4 . Define inversion layer? (Remember)

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When a higher positive potential greater than critical threshold is applied, it attracts more positive charge to the gate.
These holes are repelled further and a small number of free electrons in the body are attracted to the region beneath
the gate. This conductive layer of electrons in the p-type body is called inversion layer.

Q-5. Why nMos technology is preferred more than PMOS technology ?

N-Channel transistors have greater switching speed when compared to PMOS transistors. Hence, NMOS is preferred
than PMOS.

Q-6. Give the expression for rise time and fall time in cmos inverter circuit.(Apply)

Rise time:
The time needed for Vout to rise fron 0.1 Vdd to 0.9 Vdd is called rise time.
tr =ln(9) τp
tr =2.2 τp
Fall time:
The time needed for Vout to fall from 0.9 vdd to 0.1 Vdd is called fall time.
tf =ln(9) τn
tf =2.2 τn

Q-7. What are the steps involved in manufacturing of IC? (Remember)

The steps are
1. Wafer preparation
2. Epitaxial growth
3. Oxidation
4. Photo lithography
5. Diffusion and Ion implantation
6. Isolation
7. Metallization

Q-8. What are the 3-modes of n-MOS enhancement transistor? (Remember)

The three modes are

1. Accumulation Mode
2. Deletion Mode
3. Inversion Mode

Q-9. What are the different regions in nMOS depending upon voltages? (Remember)

There are three different regions in nMOS transistor depending upon the operating voltages i.e Vgs & Vds

1. When Vgs < Vt & Vds =0 -cut off region

2. When Vgs > Vt & Vds < Vgs-Vt -Linear region
3. When Vgs > Vt &Vds >Vgs-Vt -Saturation region

Q-10. What is CMOS Technology ?

The fabrication of an IC using CMOS transistor is known as CMOS technology. CMOS transistor is nothing but an
inverter, made up of an n-MOS and p-MOS transistor connected in series

Q-11. Give the advantages of CMOS IC ?

1. Size is less
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 2. High Speed
3. Less Power Dissipation
Q-12. Why does the present VLSI circuits use MOSFETs instead of BJTs?

Compared to BJTs, MOSFETs can be made very small as they occupy very small silicon area on IC chip and are relatively
simple in terms of manufacturing. Moreover digital and memory ICs can be implemented with circuits that use only
MOSFETs i.e. no resistors, diodes, etc.

Q-13. What are the various regions of operation of MOSFET? How are those regions used?

MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as
amplifier.

Q-14. What is threshold voltage?

The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in
the channel region to form a conducting channel is called threshold voltage (Vt is positive for NMOS and negative for
PMOS).

Q-15. What does it mean “the channel is pinched off”?

For a MOSFET when VGS is greater than Vt, a channel is induced. As we increase VDS current starts flowing from Drain
to Source (triode region). When we further increase VDS, till the voltage between gate and channel at the drain end to
become Vt, i.e. VGS – VDS = Vt, the channel depth at Drain end decreases almost to zero, and the channel is said to be
pinched off. This is where a MOSFET enters saturation region.

Q-16. Explain the three regions of operation of a MOSFET.

Cut-off region: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.
Triode region: When VGS ≥ Vt, a channel will be induced and current starts flowing if VDS > 0. MOSFET will be in triode
region as long as VDS < VGS – Vt.
Saturation region: When VGS ≥ Vt, and VDS ≥ VGS – Vt, the channel will be in saturation mode, where the current
value saturates. There will be little or no effect on MOSFET when VDS is further increased.

Q-17. What is channel-length modulation?

In practice, when VDS is further increased beyond saturation point, it does have some effect on the characteristics of
the MOSFET. When VDS is increased the channel pinch-off point starts moving away from the Drain and towards the
Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length
Modulation.

Q-18. Explain depletion region.

When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region
of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a
carrier-depletion region.

Q-19. What is body effect?

Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all
MOSFETs the body substrate is connected to the most negative power supply (in case of PMOS most positive power

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supply). Which causes a reverse bias voltage between source and body that effects the transistor operation, by
widening the depletion region? The widened depletion region will result in the reduction of channel depth. To restore
the channel depth to its normal depth the VGS has to be increased. This is effectively seen as change in the threshold
voltage – Vt. This effect, which is caused by applying some voltage to body is known as body effect.

Q-20 . Give various factors on which threshold voltage depends.

As discussed in the above question, the Vt depends on the voltage connected to the Body terminal. It also depends on
the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.

Q-21. What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) – In BJT, we see
current due to both the carriers : Electrons and Holes. BJT is a current controlled device and MOSFET is a voltage
controlled device.

Q-22. Why are most interrupts active low?

If you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or
discharged based on low to high and high to low transition, respectively. when it goes from high to low it depends on
the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than
charging. Hence designers prefer active low interrupt signals.

Q-23. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?

To limit the height of the stack. The higher the stack the slower the gate will be. In NAND and NOR gates the number of
gates present in the stack is usually same as the number of inputs plus one. So inputs are limited to four.

Q-24.On what factors does the resistance of metal depend on?

R = (p.l)/A
Where
R = Resistance of the metal.
p = Resistivity of the metal.
A = is the cross sectional area.
l = length of the metal.
With increase in length or decrease in cross sectional area resistance of the metal wire increases. Resistivity(p) is the
material property which depends on temperature. In general, resistivity of metals increases with temperature.

Q-25 What are the important aspects of VLSI optimization?

Power, Area, and Speed.

Q-26. What are the sources of power dissipation?

 Dynamic power consumption, due to logic transitions causing logic gates to charge/discharge load capacitance.

 Short-circuit current, this occurs when p-tree and n-tree shorted (for a while) during logic transition.

 Leakage current, this is a very important source of power dissipation in nano technology, it increases with
decrease in lambda value. It is caused due to diode leakages around transistors and n-wells.

Q-27. What is the need for power reduction?

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Low power increases noise immunity, increases batter life, decreases cooling and packaging costs.

Q-28. Give some low power design techniques.

Voltage scaling, transistor resizing, pipelining and parallelism, power management modes like standby modes, etc.

Q-29. Give a disadvantage of voltage scaling technique for power reduction.

When voltage is scaled, designers tend to decrease threshold voltage to maintain good noise margins. But decreasing
threshold voltages increases leakage currents exponentially.

Q-30.Give an expression for switching power dissipation.

Pswitching = (1/2)CVdd2f
Where
Pswitching = Switching power.
C = Load capacitance.
Vdd = Supply voltage.
f = Operating frequency.

Q-31. Will glitches in a logic circuit cause power wastage?

Yes, because they cause unexpected transitions in logic gates.

Q-32. What is Channel-length modulation?

The current between drain and source terminals is constant and independent of the applied voltage over the
terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the
applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the
effective channel.
Q-33. Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source
of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

Q-34. Define Rise time

Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

Q-35. Define Fall time

Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

Q-36. Define Delay time

Delay time, td is the time difference between input transition (50%) and the 50% output level. This is the time taken
for a logic transition to pass from input to output.

Q-37. What are two components of Power dissipation?

There are two components that establish the amount of power dissipated in a CMOS circuit. These are:

i) Static dissipation due to leakage current or other current drawn continuously from the power supply.

ii) Dynamic dissipation due to - Switching transient current – Charging and discharging of load capacitances.

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Q-38. In saturation region, what are the factors that affect Ids?

i. Distance between source and drain.

ii. Channel width
iii. Threshold Voltage
iv. Thickness of oxide layer
v. Dielectric constant of gate insulator
vi. Carrier mobility.

Q-39 . What are the advantages of CMOS inverter over the other inverter configurations ?

a. The steady state power dissipation of the CMOS inverter circuit is negligible.
b. The voltage transfer characteristic (VTC) exhibits a full output voltage wing between 0V and VDD. This results in high
noise margin.

Q-40 . Draw the circuit of a CMOS inverter.

Q-41. Draw the circuit of a nMOS inverter.

Q-42. Plot the current-voltage characteristics of a nMOS transistor.

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Q-43. Define accumulation mode.
The initial distribution of mobile positive holes in a p type silicon substrate of a MOS transistor for a voltage much less
than the threshold voltage

Q-44. What is intrinsic and extrinsic semiconductor?

The pure silicon is known as Intrinsic Semiconductor. When impurity is added with pure silicon, it is electrical
properties are varied. This is known as Extrinsic semiconductor.

Q-45. What is CLB?

CLB means Configurable Log ic Block.

Q-46. What are the two types of MOSFET?

Two types of MOSET are n -channel MOSET and p-channel MOSFET. These are known as n-MOS and

Q-47. What is AOI logic function?

AND OR Invert logic funct ion (AOI) implements operation in the or der of AND, OR, NOT operations. So this logic
function is known as AOI logic function.

Q-48. Explain what is the depletion region?

When positive voltage is transmitted across Gate, it causes the free holes (positive charge) to be pushed back or
repelled from the region of the substrate under the Gate. When these holes are pushed down the substrate, they
leave behind a carrier depletion region.

Q-49. What are the different layers in MOS transistors?

Drain , Source & Gate
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Q-50. What is Enhancement mode transistor?
The device that is normally cut-off with zero gate bias.

Q-51. What is Depletion mode Device?

The Device that conduct with zero gate bias.

Q-52.When the channel is said to be pinched –off?

If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage effectively pinches off the channel
near the drain.

Q-53.Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short channel devices
the ratio between the lateral & vertical dimensions are reduced.

Q-54. What is pull down device?

A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down device.

Q-55.What is pull up device?

A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device.

Q-56. Why NMOS technology is preferred more than PMOS technology?

N- Channel transistors has greater switching speed when compared tp PMOS transistors.
What is the disadvantage of cmos?
(i) Consideration of (W/L) ratio
(ii) In only nmos, vin is connected to driver, but in cmos vin is connected to load & driver,t herefore the input
capacitance also increases. Space occupied is more

Q-57. Difference between latches and Flip-flop.

A latch is level-sensitive while a flip-flop is edge triggered. A latch stores when the clock level is low and is transparent
when the level is high. A flip-flop stores when the rises and is mostly never transparent.

Q-58. What is a FPGA?

A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively
large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can
implement circuits of upto about 20,000 equivalent gates.

Q-59 .What is the full custom ASIC design?

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In a full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout specifically for one ASIC. It
makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the
entire design.

Q-60. What are four generations of Integration Circuits?

_ SSI (Small Scale Integration)

_ MSI (Medium Scale Integration)
_ LSI (Large Scale Integration)
_ VLSI (Very Large Scale Integration)

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