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FPGA based development platform for implementation of brushless DC motor

control

Conference Paper · November 2013

DOI: 10.1109/TELFOR.2013.6716310

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21st Telecommunications forum TELFOR 2013 Serbia, Belgrade, November 26-28, 2013.

FPGA based development platform for

Implementation of Brushless DC Motor Control
Milos M. Nikolic, Nebojsa U. Pjevalica, Jelena V. Kovacevic Member, IEEE, Ilija P. Djukic

between the stator current and back electromotive force

Abstract — Development of motor control techniques in (EMF). Brushed DC motors are characterized with high
last decade improved motor efficiency and wider usage area maintenance due to the presence of brushes. From the
of BLDC motors. In modern industry one of the most above mentioned it is obvious that there is a huge potential
important constraints is the product price. In motor industry
for BLDC motors to replace both of these. Replacing these
there are not many application specific integrated circuits
(ASIC) solutions for motor control. One of reasons is very inefficient motors with more efficient brushless dc
high price of ASIC development and its validation and (BLDC) motors will result in substantial energy savings.
production. To decrease the development time and time Beside the energy saving, BLDC motors have many other
needed for validation a custom FPGA platform can be used. advantages over brushed DC motors and induction motors.
With the prices of FPGA components which are decreasing Some of them are a high reliability, long operating life (no
rapidly, such platform can even become a commercial
brush erosion), noiseless operation, better speed versus
solution. Modular and flexible design offers the opportunity
to use various approaches during the development phase. torque characteristics, high dynamic response, higher
Such embedded system is not designed for general processing speed ranges, and reduction of electromagnetic
but for specific application which makes it a good starting interference [3]. In addition, the ratio of delivered torque
point in the ASIC development. This paper presents design versus the size of the motor is higher, making it useful in
and implementation of an FPGA based development applications where space and weight are critical factors,
platform for Brushless DC (BLDC) motor control using
Xilinx FPGA – Virtex6. Experimental verification is
especially in aerospace applications [1][3][4].
performed on Hall sensor control application, as on of the Over the last decade, ongoing improvements in power
most common motor control configurations. semiconductors and controller ICs as well as the
Keywords — Brushless DC (BLDC) motor, Development permanent-magnet brushless motor production have made
environment, Hall sensors, field programmable gate array it possible to manufacture reliable cost-effective solutions
(FPGA), inverters, motor control. for a broad range of adjustable speed applications [5].
However, in this moment one of further improvements
I. INTRODUCTION
could be done by production of BLDC motor controller as
R EDUCING power consumption is required in today’s
products in every segment of industry. In the past few
decades global economy faced high energy prices,
an ASIC, but there are some challenges.
In the first place, motor control requires drive unit
which includes power switches, current sensing devices
therefore most newly developed variable speed motor and control logic, question is which of these blocks should
drives aimed energy saving applications such as in HVAC be inside of integrated circuit and which should remain
systems [1]. external. Typically power switches and current sensors are
It is common that more than 5 000 000 000 motors are outside. With such resource allocation, control logic is
built every year worldwide. The fact is that the most of typically implemented in variety of processor or
them are single phase induction motors or brushed DC microcontroller platforms, while ASIC, as quite
motors [2]. Single phase induction motors are demanding and usually less flexible implementation has
characterized by low efficiency because of the ohmic loss low market share. On the other hand ASIC solution
in the rotor and due to the phase angle displacement enables high speed hardware response to all critical events
related to safety and system protection, much faster than
This work was partially supported by the Ministry of Education, any processor related solution. Also control loop if
Science and Technological Development of the Republic of Serbia under implemented in RTL with dedicated hardware allocated
Grant 32030 for arithmetic and logic operations shrinks response time
Milos M. Nikolic is with the RT-RK Institute for Computer Based and makes system faster which is crucial for high speed –
Systems, Narodnog Fronta 23a, 21000 Novi Sad, Serbia, (phone: +381-
21-4801291; e-mail: [email protected]).
top performance drives.
Nebojsa U. Pjevalica is with the RT-RK Institute for Computer Based Development of motor controller requires reliable
Systems, Narodnog Fronta 23a, 21000 Novi Sad, Serbia, (phone: +381- simulation environment but the absence of the reliable
21-4801291; e-mail: [email protected]). motor model in RTL simulation environment, which
Jelena V. Kovaceivc, University of Novi Sad, Faculty of Technical
Sciences, Trg Dositeja Obradovića 6, 21000 Novi Sad, Serbia, (phone: should provide response signals in wide motor operation
+381-21-4801168; e-mail: [email protected]). area is causing that ASIC verification using simulation
Ilija M. Djukic is with the RT-RK Institute for Computer Based environment becomes too risky from the point of
Systems, Narodnog Fronta 23a, 21000 Novi Sad, Serbia, (phone: +381-
21-4801260; e-mail: [email protected]). reliability. Also, modeling of motors using graphical

978-1-4799-1420-3/13/$31.00 ©2013 IEEE 632

environments, and connecting them to the classic RTL B. Commutation logic
simulation are causing that the simulation time is BLDC motor commutation is controlled electronically.
increasing from minutes and hours to days and weeks, Mechanical revolution of the motor is the movement of the
which makes time-to-market unacceptable. Therefore, motor rotor for 360 degrees.
environment for verification of BLDC motor control ASIC
should be something else but simulation.
Fast prototyping allows early validation [6][7], shortens
the time-to-market. Instead of long simulation, the real
time execution on the platform gives the immediate results
and characteristics that can be measured with equipment
used for motor efficiency evaluation.
Other reason that led to the development of the
prototype platform is the opportunity to use real motor as
an object of testing, since it is hard to define simulation or
emulation model of motor which will respond on all input
signals properly with unique noise sources. This is found
really important especially in the areas where sensor less
algorithms are using back EMF signal for position
estimation.
II. BLDC MOTOR CONTROL SYSTEM ARCHITECTURE
The whole system is shown in Fig. 1. This is general
system setup, which have to be consisted of, besides the
motor and load, power electronic inverter board
commutation system and control unit that controls the
system.

Fig. 3 Back EMF and phase current variation with rotor

electrical angle
In case that rotor is designed with one pair of poles, means
one magnet, than the electrical revolution is equal to
mechanical revolution. In case that motor is designed with
more than one magnet poles, which is done with purpose
to make the motor characteristics smoother, mechanical
Fig. 1 BLDC motor system architecture
revolution is represented as:
Power electronics l= p•n (1)
where:
S1 D1 S3 D3 S5 D5 A
l – Number of electrical rotation
n – Number of mechanical rotation
p – Number of pole pairs
C M In Fig. 3 currents and back EMF are in all three phases
S2 D2 S4 D4 S6 D6 B
of motor for the BLDC motor with trapezoidal flux
distribution. The goal is to produce constant output power
which means that the output torque should be constant. To
achieve this, phase currents have to be quasi square,
Fig. 2 Three phase inverter bridge configuration similar to currents in Fig. 3. For a star-connected motor,
the whole working process can be switched into six
A. Brushless DC Motor Inverter modes, where, in every phase, two out of three phases are
The power electronics inverter bridge actually transfers conducting, while third is open.
the PWM signals from the control system, which generates
C. Control System for Brushless DC Motor
low voltage signals (up to 5V), to the motor which should
be powered with high voltages (usually 20-400V Control system is collecting input data, such as Hall
depending on the motor usage area). Depending on the sensor inputs, phase currents and voltages, and provides
motor type, inverter bridge components are selected to control signals for the system. It should generate PWM
meet voltage and switching speed requirements. signals to control the power switches in the inverter block.
In Fig. 2 triple half bridge system with standard six In case of presence of Hall sensors, commutation is
switches is presented. This is typical inverter bridge that is based on the inputs from the Hall sensors, and the
used for motor control. sequence how the windings should be powered is shown in
TABLE 1.

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 TABLE 1 SWITCHES DRIVE PATTERN FOR CLOCKWISE DIRECTION FPGA control board. Its main part is FPGA Xilinx Virtex
HALL
SENSORS
ACTIVE SWITCH 6, XC6VLX130T [8]. To provide the ability to connect to
PHASE C B A
C C B B A A inverter board on one side and PC application or different
HIGH LOW HIGH LOW HIGH LOW
controlling device such as DSP or microcontroller, board
1 1 0 1 0 1 0 0 1 0
also includes various interfaces. Within the board there is
2 1 0 0 1 0 0 0 0 1
corresponding FPGA JTAG programming interface,
3 1 1 0 1 0 0 1 0 0 LEDs, switches, 48 GPIO pins, 3 potentiometers, interface
4 0 1 0 0 1 1 0 0 0 to inverter board and SPI interface aimed for connection to
5 0 1 1 0 0 1 0 0 1 μC or DSP IC. UART can be used as a connection with
6 0 0 1 0 0 0 1 1 0 PC as additional debug interface beside JTAG.
In sensor less algorithm for position detection, control
block is responsible of switching signals generation, which
is dependent on various input signals, depending on the
chosen algorithm.

Fig. 5 Control board block diagram

The control board is shown in Fig. 6.

Fig. 4 Inverter board

III. DEVELOPMENT PLATFORM ARCHITECTURE

Considering all mentioned development platform is
designed for motor control and it consists of two major
parts: inverter board with six switch topology and digital
control board which can be used for control algorithm
development. Details about each of the boards are
following.
A. Inverter board Fig. 6 Digital control board
FPGA and its surrounding are forming the control part
Developed inverter board is designed using 6 switches,
of the board. On the other side this board also has 8-
following the topology shown in Fig. 2. This board
channel ADC which provides capability of monitoring of
consists of the switching components and surrounding
various input signals. To inputs lines of ADC there can be
logic which includes over current protection and delay
connected voltage signal from the virtual neutral point,
circuits between every two switches in one half bridge to
signals from the current sensors, voltage signal from all
prevent the situation that both of switches in one half
three windings, signals from 3 potentiometers and various
bridge are conductive. Developed inverter board is shown
external signals routed directly or over the current mirrors
in Fig. 4. Other than main functionality, it is intended to be
or comparator circuit.
the pedestal for the development platform, so it has
FPGA of this size is chosen to meet both, requirements
connectors for the control board and available connections
for development of algorithm (sensor less algorithms) and
for motor terminals, so the motor can be directly
requirements for enough resources for debugging logic
connected to it.
like Xilinx ChipScopePro analyzer [9]. Also, the new
DC link ground line has a shunt resistor as main current
technology used in such part is helping to meet all timings
sensing transducer. Signal is conditioned and amplified,
in the design. In Fig. 7 are both boards connected together
also transferred towards control board.
in development platform.
B. Control board
Beside the inverter board we have also developed
control board. Fig. 5 shows the block diagram of the

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 Fig. 7 Development platform
Fig. 9 Terminal voltages (motor is spinning
IV. CONCLUSION under current controlled PWM)
In order to demonstrate the functionality of the Tests with these two driving schemes are showing that
developed platform, a simple control algorithm using Hall the hardware setup can meet requirements such as high
sensors for position detection is used. Also, FPGA is power and complex control algorithm. The board is
generating PWM signals for inverter board. The Anaheim developed to provide flexibility and expandability.
BLY173S-24V-4000 motor is used for experiments. The board with current sensors for direct current
Beside the developed platform and motor, the monitoring is also developed and successfully tested as
experimental setup requires power supply of 24V DC. well as adapter board with μC connected through SPI,
The results of motor spinning are shown in Fig. 8 and which can be used for development of control algorithms
Fig. 9. Fig. 8 is showing three voltages on motor windings using higher level languages at early stage of the
in case of motor control using Hall sensors for position development phase.
detection and PWM voltage signal applied to the Results are showing that the developed platform has
corresponding phases as shown in TABLE 1. Fig. 9 is proper functionality. When all interfaces are taken into a
showing three voltages on motor windings in case of count the platform has the potential to be the basic element
motor control using Hall sensors for position detection and for development of various control algorithms including
with current controlled PWM. sensorless control.

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