Mid-Sem 1 QP - Answerkey
Mid-Sem 1 QP - Answerkey
Mid-Semester Test
(EC-2 Regular Answer Key)
Q.1. In a system, parallelization is done using 8 processors. A program has been updated with
60% parallelizable code and 40% sequential. Calculate the speed-up attained. [2 Marks]
Q.3. An 8-way set associative cache of size 64 KB (1KB = 1024 bytes) is used in a system with
32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET.
Considering block size of 1024, give the number of bits of the TAG field. [2 Marks]
No of tag bits(19), Index(3), Offset(10)
Q.4. Explain the role and physical location of each level of cache (L1, L2, L3) in the memory
hierarchy. Discuss the potential advantages and disadvantages of adding additional levels of
cache (e.g., L4) to the memory hierarchy. Consider factors such as access time, power
consumption, and cost in your answer. [4 Marks]
Role and physical location of all three cache(2), Advantage & disadvantage(2)
Q.5. Give example of temporal locality and spacial locality in terms of cache. [2 Marks]
Temporal locality example (1), special locality example (1)
Q.6. Construct a use-case where you would prefer using Virtual Machines over containers. Justify
your decision. [4 Marks]
Use case that needs lot of/frequent changes to be done even after deployment
Q.7. Describe virtual cluster and draw a supporting diagram. Also, correlate virtual cluster with
cloud computing. [6 Marks]
Virtual Cluster definition(2), Diagram(1), correlation of virtual cluster and cloud
computing (3)
Q.8. Correlate the concept of ISA virtualization, hardware virtualization, and hardware assisted
virtualization giving appropriate scenario/example. [6 Marks]
Concept of ISA, hardware, and hardware assisted virtualization 1.5 each (4.5),
scenario/diagram (1.5)
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