COMPUTER ORGANIZATION AND ARCHITECTURE

Unit-I
Basic Structure of Computers: Functional Units, Basic Operational Concepts, Basic I/O Operations, Bus
Structures, Instruction Cycle, Data Transfer, Data Manipulation and Program Control, Addressing Modes.
Functional Units:

Functional Units of Digital System

 A computer organization describes the functions and design of the various units of a digital system.
 A general-purpose computer system is the best-known example of a digital system. Other examples
include telephone switching exchanges, digital voltmeters, digital counters, electronic calculators and
digital displays.
 Computer architecture deals with the specification of the instruction set and the hardware units that
implement the instructions.
 Computer hardware consists of electronic circuits, displays, magnetic and optic storage media and also
the communication facilities.
 Functional units are a part of a CPU that performs the operations and calculations called for by the
computer program.
 Functional units of a computer system are parts of the CPU (Central Processing Unit) that performs the
operations and calculations called for by the computer program. A computer consists of five main
components namely, Input unit, Central Processing Unit, Memory unit Arithmetic & logical unit,
Control unit and an Output unit.

Input unit
  Input units are used by the computer to read the data. The most commonly used input devices are
keyboards, mouse, joysticks, trackballs, microphones, etc.
 However, the most well-known input device is a keyboard. Whenever a key is pressed, the
corresponding letter or digit is automatically translated into its corresponding binary code and
transmitted over a cable to either the memory or the processor.

Central processing unit

 Central processing unit commonly known as CPU can be referred as an electronic circuitry within a
computer that carries out the instructions given by a computer program by performing the basic
arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

Memory unit

 The Memory unit can be referred to as the storage area in which programs are kept which are running,
and that contains data needed by the running programs.
 The Memory unit can be categorized in two ways namely, primary memory and secondary memory.
 It enables a processor to access running execution applications and services that are temporarily stored
in a specific memory location.
 Primary storage is the fastest memory that operates at electronic speeds. Primary memory contains a
large number of semiconductor storage cells, capable of storing a bit of information. The word length of
a computer is between 16-64 bits.
 It is also known as the volatile form of memory, means when the computer is shut down, anything
contained in RAM is lost.
 Cache memory is also a kind of memory which is used to fetch the data very soon. They are highly
coupled with the processor.
 The most common examples of primary memory are RAM and ROM.
 Secondary memory is used when a large amount of data and programs have to be stored for a long-term
basis.
 It is also known as the Non-volatile memory form of memory, means the data is stored permanently
irrespective of shut down.
 The most common examples of secondary memory are magnetic disks, magnetic tapes, and optical
disks.

Arithmetic & logical unit

 Most of all the arithmetic and logical operations of a computer are executed in the ALU (Arithmetic and
Logical Unit) of the processor. It performs arithmetic operations like addition, subtraction,
multiplication, division and also the logical operations like AND, OR, NOT operations.

Control unit

 The control unit is a component of a computer's central processing unit that coordinates the operation of
the processor. It tells the computer's memory, arithmetic/logic unit and input and output devices how to
respond to a program's instructions.
 The control unit is also known as the nerve center of a computer system.
  Let's us consider an example of addition of two operands by the instruction given as Add LOCA, RO.
This instruction adds the memory location LOCA to the operand in the register RO and places the sum
in the register RO. This instruction internally performs several steps.

Output Unit

 The primary function of the output unit is to send the processed results to the user. Output devices
display information in a way that the user can understand.
 Output devices are pieces of equipment that are used to generate information or any other response
processed by the computer. These devices display information that has been held or generated within a
computer.
 The most common example of an output device is a monitor.

Basic Operational Concepts

 The primary function of a computer system is to execute a program, sequence of instructions. These
instructions are stored in computer memory.
 These instructions are executed to process data which are already loaded in the computer memory
through some input devices.
 After processing the data, the result is either stored in the memory for further reference, or it is sent to
the outside world through some output port.

 To perform the execution of an instruction, in addition to the arithmetic logic unit, and control unit, the
processor contains a number of registers used for temporary storage of data and some special function
registers.
 The special function registers include program counters (PC), instruction registers (IR), memory address
registers (MAR) and memory and memory data registers (MDR).
  The Program counter is one of the most critical registers in CPU.
 The Program counter monitors the execution of instructions. It keeps track on which instruction is being
executed and what the next instruction will be.
 The instruction register IR is used to hold the instruction that is currently being executed.
 The contents of IR are available to the control unit, which generate the timing signals that control, the
various processing elements involved in executing the instruction.
 The two registers MAR and MDR are used to handle the data transfer between the main memory and the
processor.
 The MAR holds the address of the main memory to or from which data is to be transferred.
 The MDR contains the data to be written into or read from the addressed word of the main memory.
 Whenever the processor is asked to communicate with devices, we say that the processor is servicing the
devices. The processor can service these devices in one of the two ways.
 One way is to use the polling routine, and the other way is to use an interrupt.
 Polling enables the processor software to check each of the input and output devices frequently. During
this check, the processor tests to see if any devices need servicing or not.
 Interrupt method provides an external asynchronous input that informs the processor that it should
complete whatever instruction that is currently being executed and fetch a new routine that will service
the requesting device.

Basic I/O Operations:

The method that is used to transfer information between internal storage and external I/O devices is known as
I/O interface. The CPU is interfaced using special communication links by the peripherals connected to any
computer system. These communication links are used to resolve the differences between CPU and peripheral.
There exists special hardware components between CPU and peripherals to supervise and synchronize all the
input and output transfers that are called interface units.

Mode of Transfer:

The binary information that is received from an external device is usually stored in the memory unit. The
information that is transferred from the CPU to the external device is originated from the memory unit. CPU
merely processes the information but the source and target is always the memory unit. Data transfer between
CPU and the I/O devices may be done in different modes.

Data transfer to and from the peripherals may be done in any of the three possible ways

1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).

Now let’s discuss each mode one by one.

1. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer program.
Each data item transfer is initiated by an instruction in the program. Usually the transfer is from a CPU
register and memory. In this case it requires constant monitoring by the CPU of the peripheral devices.
 Example of Programmed I/O: In this case, the I/O device does not have direct access to the memory
unit. A transfer from I/O device to memory requires the execution of several instructions by the CPU,
including an input instruction to transfer the data from device to the CPU and store instruction to
transfer the data from CPU to memory. In programmed I/O, the CPU stays in the program loop until the
I/O unit indicates that it is ready for data transfer. This is a time consuming process since it needlessly
keeps the CPU busy. This situation can be avoided by using an interrupt facility. This is discussed
below.

2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This
situation can very well be avoided by using an interrupt driven method for data transfer. By using
interrupt facility and special commands to inform the interface to issue an interrupt request signal
whenever data is available from any device. In the meantime the CPU can proceed for any other
program execution. The interface meanwhile keeps monitoring the device. Whenever it is determined
that the device is ready for data transfer it initiates an interrupt request signal to the computer. Upon
detection of an external interrupt signal the CPU stops momentarily the task that it was already
performing, branches to the service program to process the I/O transfer, and then return to the task it was
originally performing.
3. Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and
memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly
communicate with each other using the memory buses, removing the intervention of the CPU. This type
of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and
it has no control over the memory buses. The DMA controller takes over the buses to manage the
transfer directly between the I/O devices and the memory unit.

Bus structure:

Bus is a group of conducting wires which carries information, all the peripherals are connected to
microprocessor through Bus.

Diagram to represent bus organization :

There are three types of buses.

1. Address b:us
It is a group of conducting wires which carries address only.Address bus is unidirectional because data
flow in one direction, from microprocessor to memory or from microprocessor to Input/output devices
(That is, Out of Microprocessor).

Length of Address Bus of 8085 microprocessor is 16 Bit (That is, Four Hexadecimal Digits), ranging
from 0000 H to FFFF H, (H denotes Hexadecimal). The microprocessor 8085 can transfer maximum 16
bit address which means it can address 65, 536 different memory location.

The Length of the address bus determines the amount of memory a system can address.Such as a system
with a 32-bit address bus can address 2^32 memory locations.If each memory location holds one byte,
the addressable memory space is 4 GB.However, the actual amount of memory that can be accessed is
usually much less than this theoretical limit due to chipset and motherboard limitations.
 2. Data Bus:
It is a group of conducting wires which carries Data only.Data bus is bidirectional because data flow in
both directions, from microprocessor to memory or Input/Output devices and from memory or
Input/Output devices to microprocessor.

Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two Hexadecimal Digits), ranging from 00
H to FF H. (H denotes Hexadecimal).

When it is write operation, the processor will put the data (to be written) on the data bus, when it is read
operation, the memory controller will get the data from specific memory block and put it into the data
bus.

The width of the data bus is directly related to the largest number that the bus can carry, such as an 8 bit
bus can represent 2 to the power of 8 unique values, this equates to the number 0 to 255.A 16 bit bus can
carry 0 to 65535.

3. Control bus :
It is a group of conducting wires, which is used to generate timing and control signals to control all the
associated peripherals, microprocessor uses control bus to process data, that is what to do with selected
memory location. Some control signals are:
o Memory read
o Memory write
o I/O read
o I/O Write
o Opcode fetch

If one line of control bus may be the read/write line.If the wire is low (no electricity flowing) then the
memory is read, if the wire is high (electricity is flowing) then the memory is written.

Instruction Cycles

Registers Involved In Each Instruction Cycle:

 Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies
the address in memory for a read or write operation.
 Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the
value to be stored in memory or the last value read from the memory.
 Program Counter(PC) : Holds the address of the next instruction to be fetched.
 Instruction Register(IR) : Holds the last instruction fetched.
The Instruction Cycle :

Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-operations. In the
above examples, there is one sequence each for the Fetch, Indirect, Execute and Interrupt Cycles.

Different Instruction Cycles:

The Fetch Cycle –

At the beginning of the fetch cycle, the address of the next instruction to be executed is in the Program
Counter(PC).

Step 1: The address in the program counter is moved to the memory address register(MAR), as this is
the only register which is connected to address lines of the system bus.

Step 2: The address in MAR is placed on the address bus, now the control unit issues a READ
command on the control bus, and the result appears on the data bus and is then copied into the memory
buffer register(MBR). Program counter is incremented by one, to get ready for the next instruction.
(These two action can be performed simultaneously to save time)

Step 3: The content of the MBR is moved to the instruction register(IR).

Thus, a simple Fetch Cycle consist of three steps and four micro-operation. Symbolically, we can write
these sequence of events as follows:-
 Decode :

1.The instruction is broken up into parts that have significance to other portions of the CPU.

2.The way in which the numerical instruction value is interpreted is defined by the CPU's instruction set
architecture (ISA).

3.Opcode, indicates which operation to perform.

4.The remaining parts of the number usually provide information required for that instruction, such as
operands for an addition operation.

5.Such operands may be given as a constant value or as a place to locate a value: a register or a memory
address, as determined by some addressing mode.

Execute :

1.During this step, various portions of the CPU are connected so they can perform the desired operation.

2.If, for instance, an addition operation was requested, an arithmetic logic unit (ALU) will be connected to a
set of inputs and a set of outputs.

3.The inputs provide the numbers to be added, and the outputs will contain the final sum.

Write back :

After completion of operation in ALU the results are stored in CPU registers or memory locations.

Data Transfer

Data transfer instructions move data from one place in the computer to another without changing the data.
Typical transfers are between memory and processor registers, between processor registers and input and
output registers, and among the processor registers themselves.

Synchronous Data Transfer in Computer Organization

In Synchronous data transfer, the sending and receiving units are enabled with same clock signal. It is
possible between two units when each of them knows the behavior of the other. The master performs a
sequence of instructions for data transfer in a predefined order. All these actions are synchronized with the
common clock. The master is designed to supply the data at a time when the slave is definitely ready for it.
Usually, the master will introduce sufficient delay to take into account the slow response of the slave, without
any request from the slave.

The master does not expect any acknowledgment signal from the slave when data is sent by the master to the
slave. Similarly, when data from the slave is read by the master, neither the slave informs that the data has been
placed on the data bus nor the master acknowledges that the data has been read. Both the master and slave
perform their own task of transferring data at a designed clock period. Since both devices know the behavior
(response time) of each other, no difficulty arises.
Prior to transferring data, the master must logically select the slave either by sending slave’s address or sending
“device select” signal to the slave. But there is no acknowledgment signal from the slave to the master if the
device is selected.

Timing diagram of the synchronous read operation is given below:

Data transfer instructions:

Data transfer instructions move data from one place in the computer to another without changing the data.
Typical transfers are between memory and processor registers, between processor registers and input and
output registers, and among the processor registers themselves.

Data transfer instructions :

Data tranfer instructions are the instructions which transfers data in the microprocessor. They are also called
copy instructions.

Following is the table showing the list of data transfer instructions:

OPCODE OPERAND EXPLANATION EXAMPLE

MOV D, S D=S MOV AX, [SI]
PUSH D pushes D to the stack PUSH DX
POP D pops the stack to D POP AS
PUSHA None put all the registers into the stack PUSHA
POPA None gets words from the stack to all registers POPA
XCHG D, S exchanges contents of D snd S XCHG [2050], AX
IN D, S copies a byte or word from S to D IN AX, DX
OUT D, S copies a byte or word from D to S OUT 05, AL
XLAT none translates a byte in AL using a table in the memory XLAT
LAHF none loads AH with the lower byte of the flag register LAHF
SAHF none stores AH register to lower byte of the flag register SAHF
OPCODE OPERAND EXPLANATION EXAMPLE
PUSHF none copies the flag register at the top of the stack PUSHF
POPF none copies a word at the top of the stack to the flag register POPF

Here D stands for destination and S stands for source.

D and S can either be register, data or memory address.

Data Manipulation Instructions:

Data manipulation instructions perform operations on data and provide the computational capabilities for the
computer. There are three types of data manipulation instructions: Arithmetic instructions, Logical and bit
manipulation instructions, and Shift instructions.

Machine Instructions

Machine Instructions are commands or programs written in machine code of a machine (computer) that it can
recognize and execute.

 A machine instruction consists of several bytes in memory that tells the processor to perform one
machine operation.
 The processor looks at machine instructions in main memory one after another, and performs one
machine operation for each machine instruction.
 The collection of machine instructions in main memory is called a machine language program.

Machine code or machine language is a set of instructions executed directly by a computer’s central processing
unit (CPU). Each instruction performs a very specific task, such as a load, a jump, or an ALU operation on a
unit of data in a CPU register or memory. Every program directly executed by a CPU is made up of a series of
such instructions.

The general format of a machine instruction is

[Label:] Mnemonic [Operand, Operand] [;

Comments]

 Brackets indicate that a field is optional

 Label is an identifier that is assigned the address of the first byte of the instruction in which it appears. It
must be followed by “:”
 Inclusion of spaces is arbitrary, except that at least one space must be inserted; no space would lead to
an ambiguity.
 Comment field begins with a semicolon “ ; ”

Example:

Here: MOV R5,#25H ;load 25H into R5

Machine instructions used in 8086 microprocessor

1. Data transfer instructions– move, load exchange, input, output.

 MOV :Move byte or word to register or memory .

 IN, OUT: Input byte or word from port, output word to port.
 LEA: Load effective address
 LDS, LES Load pointer using data segment, extra segment .
 PUSH, POP: Push word onto stack, pop word off stack.
 XCHG: Exchange byte or word.
 XLAT: Translate byte using look-up table.

2. Arithmetic instructions – add, subtract, increment, decrement, convert byte/word and compare.

 ADD, SUB: Add, subtract byte or word

 ADC, SBB :Add, subtract byte or word and carry (borrow).
 INC, DEC: Increment, decrement byte or word.
 NEG: Negate byte or word (two’s complement).
 CMP: Compare byte or word (subtract without storing).
 MUL, DIV: Multiply, divide byte or word (unsigned).
 IMUL, IDIV: Integer multiply, divide byte or word (signed)
 CBW, CWD: Convert byte to word, word to double word
 AAA, AAS, AAM,AAD: ASCII adjust for add, sub, mul, div .
 DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers)

3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test

 NOT : Logical NOT of byte or word (one’s complement)

 AND: Logical AND of byte or word
 OR: Logical OR of byte or word.
 XOR: Logical exclusive-OR of byte or word
 TEST: Test byte or word (AND without storing).
 SHL, SHR: Logical Shift rotate instruction shift left, right byte or word? by 1or CL
 SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
 ROL, ROR: Rotate left, right byte or word? by 1 or CL .
 RCL, RCR: Rotate left, right through carry byte or word? by 1 or CL.

4. String manipulation instruction – load, store, move, compare and scan for byte/word

 MOVS: Move byte or word string

 MOVSB, MOVSW: Move byte, word string.
 CMPS: Compare byte or word string.
 SCAS S: can byte or word string (comparing to A or AX)
 LODS, STOS: Load, store byte or word string to AL.

5. Control transfer instructions – conditional, unconditional, call subroutine and return from subroutine.
  JMP:Unconditional jump .it includes loop transfer and subroutine and interrupt instructions.
 JNZ:jump till the counter value decreases to zero.It runs the loop till the value stored in CX becomes
zero

6. Loop control instructions-(Program control instructions)

 LOOP: Loop unconditional, count in CX, short jump to target address.

 LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to target address.
 LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX, short jump to target address.
 JCXZ: Jump if CX equals zero (used to skip code in loop).
 Subroutine and Intrrupt instructions-
 CALL, RET: Call, return from procedure (inside or outside current segment).
 INT, INTO: Software interrupt, interrupt if overflow.IRET: Return from interrupt.

7. Processor control instructions-

Flag manipulation:

 STC, CLC, CMC: Set, clear, complement carry flag.

 STD, CLD: Set, clear direction flag.STI, CLI: Set, clear interrupt enable flag.
 PUSHF, POPF: Push flags onto stack, pop flags off stack.
 Arithmetic instructions in 8085 microprocessor
 Arithmetic Instructions are the instructions which perform basic arithmetic operations such as addition,
subtraction and a few more. In 8085 microprocessor, the destination operand is generally the
accumulator. In 8085 microprocessor, the destination operand is generally the accumulator.
 Following is the table showing the list of arithmetic instructions:

Opcode Operand Explanation Example

ADD R A=A+R ADD B
ADD M A = A + Mc ADD 2050
ADI 8-bit data A = A + 8-bit data ADI 50
ADC R A = A + R + prev. carry ADC B
ADC M A = A + Mc + prev. carry ADC 2050
ACI 8-bit data A = A + 8-bit data + prev. carry ACI 50
SUB R A=A–R SUB B
SUB M A = A – Mc SUB 2050
SUI 8-bit data A = A – 8-bit data SUI 50
SBB R A = A – R – prev. carry SBB B
SBB M A = A – Mc -prev. carry SBB 2050
SBI 8-bit data A = A – 8-bit data – prev. carry SBI 50
INR R R=R+1 INR B
INR M M = Mc + 1 INR 2050
INX r.p. r.p. = r.p. + 1 INX H
DCR R R=R–1 DCR B
Opcode Operand Explanation Example
DCR M M = Mc – 1 DCR 2050
DCX r.p. r.p. = r.p. – 1 DCX H
DAD r.p. HL = HL + r.p. DAD H

 In the table,
R stands for register
M stands for memory

Types of Addressing Modes

Below we have discussed different types of addressing modes one by one:

Immediate Mode

In this mode, the operand is specified in the instruction itself. An immediate mode instruction has an operand
field rather than the address field.

For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.

Register Mode

In this mode the operand is stored in the register and this register is present in CPU. The instruction has the
address of the Register where the operand is stored.

Advantages

 Shorter instructions and faster instruction fetch.

  Faster memory access to the operand(s)

Disadvantages

 Very limited address space

 Using multiple registers helps performance but it complicates the instructions.

Register Indirect Mode

In this mode, the instruction specifies the register whose contents give us the address of operand which is in
memory. Thus, the register contains the address of operand rather than the operand itself.

Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.

Direct Addressing Mode

In this mode, effective address of operand is present in instruction itself.

 Single memory reference to access data.

 No additional calculations to find the effective address of the operand.
For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.

NOTE: Effective Address is the location where operand is present.

Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored in memory. This
slows down the execution, as this includes multiple memory lookups to find the operand.

Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to obtain the effective
address of operand.

EA = A + (R), In this the address field holds two values, A(which is the base value) and R(that holds the
displacement), or vice versa.

Relative Addressing Mode

It is a version of Displacement addressing mode.

In this the contents of PC(Program Counter) is added to address part of instruction to obtain the effective
address.

EA = A + (PC), where EA is effective address and PC is program counter.

The operand is A cells away from the current cell(the one pointed to by PC)

Base Register Addressing Mode

It is again a version of Displacement addressing mode. This can be defined as EA = A + (R), where A is
displacement and R holds pointer to base address.

Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top two items
from the stack, add them, and will then PUSH the result to the top of the stack.