en INTRODUCTION TO ASICs 1.1 Types of ASICs 1.6 Summary 1.2 Design Flow 1.7. Problems 1.3 Case Study 1.8» Bibliography 1.4 Economics of ASICs 1.9 References 1.5 ASIC Cell Libraries sick”; bold typeface defines a new term) is an applicat t—at least that is what the acronym stands for. Before we evolution of the silicon ‘An ASIC (pronounced specific integrated circuit answer the question of what thar means we first look at the chip or integrated circuit (IC). Figure 1.1(a) shows an IC package (this is a pin-grid array, or PGA, shown upside down; the pins will go through holes in a printed-circuit board), People often in Figure 1.1(b), the silicon chip itself call the package a chip, but, as you can see i (more properly called a die) is mounted in, the cavity under the sealed lid. A PGA package is usually made from_a ceramic material, but plastic packages are also common. FIGURE 1.1. An integrated circuit (IC). (a) A pin-grid array (PGA) package. (b) The silicon die or chip is under the package lid,2 CHAPTER 1 ICs. This meant that, for INTRODUCTION TO ASICS 1s on a side 10 Over by the number of mnit of measure a forms the millimete! fan IC As aul from a few fa silicon die vari stead we often measure the SIZE & i ransistors that the IC contains: rcuit that pert input NAND gate. (2 vmyse the term gares stead of gate equiva vot to be confused with ithe gate terminal of © contains the equivalent ‘of 100,000 two- The physical size o! Linch on a side, but i logic gates or the number gate equivalent corresponds (0 @ WO" logic function, F = A-B). Often we ju ents when we are measuring chip i267 a transistor. For example, 100 k-gate I ICs of the early 1970s apt Ived from the first "The semiconductor industry has €VO'r s i and matured rapidly since then. Early small-scale integration (8 Oo ew few (1 to 10) logic gates—NAND gates, NOR gates: Fn oan tens of transistors. The era of ‘medium-scale integration Ms) increas ae ange of integrated logic available to counters ‘and similar, larger Sn pe ao FS ‘The era of large-scale integration (LSI) packed even une tone Ss the first microprocessors, into a single chip. The era of Very scale integration (VLSI) now offers 64-bit microprocessors, complete ‘with cache memory and floating-point arithmetic nits—well over a million Transistors—on a single Piece of. rijcon, As CMOS process technology improves. transistors continue to get smaller aig ICs hold more and more transivare: ‘Some people (especially in Japan) use the term ultralarge scale integration (ULSH), but most people stP atu * to start inventing new words. Chnology and the majority of loBtc ICs used Jed logic (ECL). Although vy large he term VLSI: otherwise we hav' ‘The earliest ICs used bipolar te + transistor logic (TTL) or emitter coup Xide-silicon (MOS) transistor fe interface. bipolar transistor, the metal- it to manufacture because of pro were gradually solved, metal-gate 7 developed in the 1970s. At that time ed less power t fewer masking steps. was denser, and consi ‘a given performance, an MOS IC was cheay d growth of the MOS IC market. : tes of the transistors were replaced by poly” silicon gates, but th ‘ed, The introduction of polysilicon as a gate svaterial was a major improvement in CMOS technology, making it easier to make two types of transistors, channel MOS and p-channel MOS transistors, on the ary MOS (CMOS, never CMOS) technology. The princi- consumption, Another advan= same IC—a complement: pal advantage of CMOS over NMOS js lower power brication process, allowing tage of a polysilicon gate was a simplification of the fa devices to be scaled down in size. a a | i MOS transistors in a two-input NAND gate (and a two-input eee soo convert between gates and transistors, you multiply the number of pts by fo obtin tl number of transistors. We can also measure an IC by the sills feats roughly half the length of the smallest transistor) imprinted on * dimensions are measured in microns (a micron, I 4m, is a mil- either transisto! invented before thi was initially difficu ‘As these problems NMOS) technology blems with the oxid channel MOS (nMOS or MOS technology required han equivalent bipolar per than a bipo- ar IC and led to investment an 980s the aluminum g By the early 1 he name MOS rem:INTRODUCTION TO ASICS Iionth of a meter). Thus we talk about a 0.5 Hm IC oF say fie IC is built in (or with) a 0.5 um process, meaning thatthe smallest transisvors 2 0.5 pm in length. We give a special label. 2 or lambda, to this smalles’ Sturt ize. Since lambda is equal to Fear of the smallest transistor length, 2 = 0.25 ym 1h 0.5 pm process. Many of the drawings in this book use a seale marked with lambda for the same reason we place a scale on a map. “A modern submicron CMOS process is now just AS complicated as'a submicron bipolar or BiCMOS (a combination of bipolar and CMOS) process. However, CMOS ICs have established a dominant position, are ‘manufactured in much’greater volume than any other technology, and therefore, because of the ‘economy of scale, Tee cost of CMOS ICs is less than a bipolar or BiCMOS IC for the same function. Bipolar and BICMOS ICs are still used for special needs For example, bipolar tech- nology is generally capable of handling higher voltages than CMOS. This makes bipolar and BiCMOS ICs useful in power electronics, carss telephone circuits, and analog/digital converters, ‘or standard ICs: You can select standard ICs from hem from distributors, Systems manufacturers and ‘a variety of different microelectronic soon. Some digital logi for example) are standard parts, catalogs and data books and buy t designers can use the same standard part in systems (systems that use microelectronics or ICs). began to realize the advantages With the advent of VLSI in the 1980s engineers of designing an IC that was customized or tailored to a particular system or applica fon eather than using standard ICs alone. Microelectronic system design then becomes a matter of defining the functions that you can implement using standard Ce and then implementing the remaining logic functions (sometimes called glue fogie) with one or more custom ICs. As VLSI became possible you could build a system from a smaller number of components by combining many standard ICs into e few custom ICs. Building a microelectronic system with fewer ICs allows you to reduce cost and improve reliability. h it is not appropriate to use a Of course, there are many situations in whic If you need a large custom IC for each and every part of an microelectronic system still best to use standard memory ICs, either amount of memory, for example, it is s dynamic random-access memory (DRAM or dRAM), or static RAM (SRAM or sRAM)., in conjunction with custom ICs. ‘One of the first conferences to be devoted to this rapidly emerging segment of the IC industry was the JEEE Custom Integrated Circuits, Conference (CICC), and the proceedings of this annual conference form a useful reference to the develop- ment of custom ICs. As different types of custom ICs began to evolve for different types of applications, these new ICs gave rise to a new term: application-specific IC, OPASIC. Now we have the IEEE International ASIC Conference, which tracks advances in ASICs separately from other types of custom ICs. Although the exact definition of an ASIC is difficult, we shall look at some examples to help clarify what people in the IC industry understand by the term. i ICs and their analog counterparts (4 CHAPTER 1 INTRODUCTION TO ASICS ; memory Examples of ICs that are nor ASICs include standard parts eee chips sold as a commodity item—ROMs, DRAM, and SRAM; mi TTL or TTL-equivalent ICs at SSI, MSI, and LSI levels. ae Examples of ICs that are ASICs include: a chip for @ toy ce accel for a satellite; a chip designed to handle the interface between m ' ini sroprocessor.as a cell processor for a workstation CPU; and a chip containing 4 microp! together with other logic. it is probably not an ees 8 general Tule, if you can find it in @ ca Ce ee etl mai ASIC, but there are some exceptions. For example, two ICs tht mi oN be considered ASICs are a controller chip for pen ne lad ASICs such as these are these examples are specific to an applicati many Sitferen system vendors (shades of a standard a Sometimes called application-specific standard products (ASSIS) ig “Trying to decide which members of the huge TC family 2 wplicaon-sPeet is tricky—after all, every IC has an application. For exam. le, people Panes consider an application-spepifi microprocessor to be an ASIC. T shall COS 0 fo design an ASIC that may include large cells such as microprocessors, OV Ait hot describe the, design of the microprocessors themselves. Defining a by Tooking at the application can be confusing, so we shall look at a di Hexen wy 39 categorize the IC family. The easiest way to recognize people is by their faces an physical characteristics: tall, short, thin. The easiest characteristics of ASICs to understand are physical ones too, and we shall look at these next. It is important to understand these differences because they affect such factors as the price of an ASIC and the way you design an ASIC. 1.1. Types of ASICs ICs are made on a thin (a few hundred microns thick), circular silicon wafer, with each wafer holding hundreds of die (sometimes people use dies or dice for the plural of die). The transistors and wiring are made from many layers (usually between 10 and 15 distinct layers) built on top of one another. Each successive mask layer has a pattern that is defined using a mask similar to a glass photographic slide. The first half-dozen or so layers define the transistors. The last half-dozen or so layers define the metal wires between the transistors (the interconnect). A full-custom IC includes some (possibly all) logic cells that are customized and all mask layers that are customized. A microprocessor is an example of a full- custom IC—designers spend many hours squeezing the most out of every last square mien of microprocessor chip space by hand. Customizing all of the IC features in eee designers 9 include analog circuits, optimized memory cells, or : imple. Full-custom ICs are the most expen-1.1 TYPES OF ASICS sive to manufacture and to design. The manufacturing lead time (the time it takes just to make an IC—not including design time) is typically eight weeks for a full: seetona IC. These specialized full-custom ICs are often intended for a specific appli- cation, so we might call some of them full-custom ASICs. s briefly next, but the members of the IC We shall discuss full-custom AST family that we are more interested in are semicustom ASICs, for which all of the logic cells are predesigned and some (possibly all) of the mask layers are custom- ized, Using predesigned cells from a cell library makes our Lives as designers much, vee caciee, There are two types of semicustom ASICS that we shall cover: Mandard-cell-based ASICs and gate-array-based ASICs. Following this we shall Succribe the programmable ASICs, for which all of the-logic cells are predesigned set none of the mask layers are customized, There are two types of programmable ASICe, the programmable logic device and, the newest member of the ASIC family. the field-programmable gate array. 1.11 Full-Custom ASICs Ina full-custom ASIC an engineer designs some or all of the logic cells, circuits, oF layout specifically for one ASIC. This means the designer abandons the approach of using pretested and precharacterized cells for all or part of that design. It makes Sense to take this approach only if there are no suitable existing cell libraries avail- able that can be used for the entire design. This might be because existing cell librar- jes are not fast enough, or the logic cells are not small enough or consume too much power. You may need to use full-custom design if the ASIC technology is new or SO Specialized that there are no existing cell libraries or because the ASIC is so special ized that some circuits must be custom designed. Fewer and fewer full-custom ICs are being designed because of the problems with these special parts of the ASIC. There is one growing member of this family, though, the mixed analog/digital ASIC, which we shall discuss next Bipolar technology has historically been used for precision analog functions, ‘There are some fundamental reasons for this. In all integrated circuits the matching of component characteristics between chips is very poor, while the matching of ‘characteristics between components on the same chip is excellent. Suppose we have transistors T1, T2, and T3 on an analog/digital ASIC. The three transistors are all the same size and are constructed in an identical fashion. Transistors T1 and T2 are located adjacent to each other and have the same orientation, Transistor T3 is the same size as Tl and T2 but is located on the other side of the chip from TI and T2 and has a different orientation. ICs are made in batches called wafer lots, A wafer lot is a group of silicon wafers that are all processed together. Usually there are between 5 and 30 wafers in a lot. Each wafer can contain tens or hundreds of chips ing on the size of the IC and the wafer.cl HAPTER 1 INTRODUCTION TO ASICS istics of transistors TI, T2, Ut we were to make measurements of the character and T3 we would find the following: = tors TI will have virtually identict | char: IC. We say that the transistors matel excellent. + Transistor T3 will match transistors TI and T2.0n the not as closely as T! matches T2.0n the same I . «Transistor T1, 72, and T3 will match fairly well with transistors T+ ie nil 73 on a different IC o fer, The matching will depend on how far apart the two ICs are 0 ‘Transistors on ICs from aif very well. «Transistors on ICs For many analog designs ( operation. For these circult designs pair crch other. Device physics diekeiet that a pair r ermieh more precisely than CMOS Transistors of a comparable SIZ°- ay has historically been more widely used for full-custom analog 4 Pe proved precision. Despite its Poo! analog properties, the use Of (CMOS tech: nology for analog functions is increasing. There are two reasons for this. The first reason is that «most widely available IC technology. Many CMOS is now by far th more CMOS ASICs and CMOS standard products are now BEiNs manufactured than bipolar ICs. The second reason it that increased levels of integration require mixing analog and digital functions on the SST TC: this has forced designers to find ways — to use CMOS technology 10 igners, using implement analog functions. Circuit desi Clever new techniques. have been Vet accessful in finding new ways to design analog CMOS circuits that can approach the acct to T2 on the same acteristics : sam between devices is th well or the tracking same IC very well, but yn the same Wal n the wafer. ferent wafers in the same wafer lot will | not match atch very poorly: tors is crucial to circuit nad, located adjacent {0 tors will always Bipolar technol lesign because of from different wafer lots will m: he close matching of trails -s of transistors are usé of bipolar transis ‘uracy of bipolar analog designs: ard-Cell-Based ASICs ‘A cell-based ASIC (cell-based IC, oF CBIC—a com nsabick") uses predesigned logic cells (AND gates, OR gates, multiplexers, and flip-flops. for example) known as standard cells, We could apply the term CBIC 10 any IC that uses cells, but it is generally accepted that a cell-based ASIC or CBIC means a standard-cell-based ASIC. ‘The standard-cell areas (also called flexible blocks) in a CBIC are built of rows ee cells—like a wall built of bricks. The standard-cell areas may be used in eae larger predesigned cells, perhaps ‘microcontrollers or even micto- eae blo i as _megacells. Megacells are also called megafunctions, full .cks, system-level macros (SLMs). fixed blocks, cores, oF Functional Standard Blocks (FSBs). 4.1.2 Stand: mon term in Japan, pronounced8 CHAPTER 1 INTRODUCTION TO ASICS mi— n-well —p| eek boundita box contact, [sietgt paitf —| via |__ cell abutment box (AB) -well —pe| Ee go paiff L_ i 1020 FIGURE 1.3 Looking down on the layout of a standard cell. This cell would be approxi- mately 25 microns wide on an ASIC with & (lambda) = 0.25 microns (a micronis 10-® m). Stan- dard cells are stacked like bricks in a wall, the abutment box (AB) defines the “edges” of the brick. The difference between the bounding box (BB) and the AB is the area of overlap between the bricks. Power supplies (labeled VDD and GND) run horizontally inside a stan- dard cell on a metal layer that lies above the transistor layers. Each different shaded and labeled pattern represents a different layer. This standard cell has center connectors (the three squares, labeled A1, B1, and Z) that allow the cell to connect to others. The layout was drawn using ROSE, a symbolic layout editor developed by Rockwell and Compass, and then imported into Tanner Research's L-Edit. design). You may then connect a flexible block built from several rows of standard cells to other standard-cell blocks or other full-custom logic blocks. For example, you might want to include a custom interface to a standard, predesigned microcon- troller together with some memory. The microcontroller block may be a fixed-size megacell, you might generate the memory using a memory compiler, and the custom logic and memory controller will be built from flexible standard-cell blocks, shaped to fit in the empty spaces on the ch1.1 TYPES OF ASICS .¢ predefined cells, but there is a Me transistor sizes in a standard cell 10 optimize speed fand performance, but the device sizes i" & gate array are fixed. This results in a ange off in performance and area in a gale Ay at the silicon level. The trade-off fermen area and performance is made at the library level for a standard-cell ASIC. ‘Modern CMOS ASICS use two, threes OF more levels (or layers) of metal for imerconnect. This allows wires t0 cross Over different layers in the same way that we use copper traces on ‘1 a printed-circuit board. In a two-level metal CMOS technology, conn: standard-cell inputs and outputs are teually made using the second level of metal (metal2, the upper level of metal) at the tops and bottoms of the cells. In a three-level ‘metal technology, connections may be internal to the logic cell (as they are in Figure 1.3). This allows for more sophisti- cated routing programs to take advantage of the extra metal layer to route intercon cect over the top of the logic cells. We shall cover the details of routing ASICs in Chapter 17. ‘A connection that needs to cross ove! i feedthrough. The term feedthrough can refer either to the piece of metal that is used to pass a signal through a cell or:to a space in a cell waitin 10 be used as a feedthrough—very confusing. Figure 1.4 shows two feedthroughs: one 'n cell A.14 and one in cell A.23. aoe evorievel and three-level metal technology, the power buses (VDD and GND) inside the standard cells normally use the lowest (closest to the transistors) layer of metal (metal). The width of each row of standard cells: is adjusted so that they may be aligned using spacer cells. The power buses. oF rails, are then con- ire od to additional vertical power rails using row-end cells at the aligned ends of each standard-cell block. If the rows of standard cells are long, then vertical power rails can also be run in metal2 through the cell rows using special power cells that just connect to VDD and GND. Usually the designer manually controls the number and width of the vertical power rails connected to the standard-cell blocks during physical design. A diagram of the power distribution scheme for a CBIC is shown in Figure 1.4. ‘All the mask layers of a CBIC are customized. This allows megacells (SRAM, a SCSI controller, or an MPEG decoder, for example) to be placed on the same IC with standard ces, Megacels are usually supplied by an ASIC or tibrary company complete with behavioral models and some way to test them (a test strategy). ASIC library companies also supply compilers to generate flexible DRAM, SRAM, and ROM blocks, Since all mask layers on a standard-cell design are customized, mem- ory desian is more efficient and denser than for gate arrays. ‘or logic that operates on multiple signals across a data bus—a (DP)—the use of standard cells may ot be the" et mien ‘ate ae ae Some ASIC library companies provide a datapath compiler that autor eye erates datapath logic. A datapath library typically c ot sara ibuetes Smulipliers and cimpleld ypically contains cells such as adder and simple arithmetic and logical units (ALUs). The con- Both cell-based and gate-array ASICS us difference—we can change | + a row, of standard cells) uses @10 CHAPTER 1 INTRODUCTION TO ASICS =| _ expanded view [Ch ofpar of flexible ne connection block 1 t fonnectign metal2 { Ai gowet ds 7 to power al} pa 2502, pads met ies terminal ygg vDD VES z7 Th cells feedthrough cell A.11 cell A23. spacer cells coll 14) cell A132 metalt power cell Lad. metal2, 504 metal rows of standard cells FIGURE 1.4 Routing the CBIC (cell-based IC) shown in Figure 1.2. The use of regularly shaped standard cells, such as the one in Figure 1.3, from a library allows ‘ASICs like this to be designed automatically. This ASIC uses two separate layers of metal interconnect (metal dnd meral2) running at right angles to each other (like traces on a printed-circult board). Peer aoctions between logic cells uses spaces (called channels) between the rows of cells. ASICs may have three (or more) layers of metal allowing the cell rows to touch with the interconnect running over the top of the cells. nectors of datapath library cells are results in faster and denser layout than using standard cells or a gate array. Standard-cell and gate-array libraries may contain hundreds of information for each library element. row-end h-matched to each other so that they fit together. Connecting datapath cells to form a datapath usually, but not always, ifferent logic cells, including combinational functions (NAND, NOR, AND, OR gates) with multi- ple inputs, as well as latches and flip-flops with different combinations of reset, pre- set and clocking options. The ASIC library company provides designers with a data book in paper or electronic form with all of the functional descriptions and timing1.1 (TYPES OF ASICS 1.1.3 Gate-Array-Based ASICs abbreviated to GA),or gate-array-based ASIC the trun- fon are predefined on the silicon wafer. The predefined pattern of transistors on a 'y is the base array, and the smallest ‘element that is replicated to make the aM. C. Escher drawing, oF tiles on a floor) is the base cell (some- ‘ve eal), Only the top few layers of metal, which define the ys are defined by the designer using custom masks. To distinguish this type of gate array from other tyPes of gate array, it is often called wo Nasked gate array (MGA). The designer chooses from a gate-array library of predesigned and precharacterized logic cells. The Jogic cells in a gate-array library Pree sfen ealled macros, The reason for this is that the base-cell layout is the same for cach logic cell, and only the interconnect (inside cells and berweet cells) is cus- tomized, 50 that there is a: similarity between gate-array macros and a software naeto. Inside IBM, gate-array macros are known as books (so that books are part of, ‘a library), but unfortunately: this descriptive term is not very widely used outside IBM. We can complete the diffusion steps that wafers (sometimes we call a gate array a pre only the metal interconnections are unique 10 an MGA, w ceers for different customers as needed. Using wafers prefabricated up to the allization steps reduces the'time needed to make an MGA. the turnaround time, to 4 few days or at most a couple of weeks. The costs forall the initial fabrication Steps for an MGA are shared for each customer and this reduces the cost of an MGA,com- pared to a full-custom or standard-cell ASIC design. There are the following. different types of MGA or gate-array-based ASICs: ymetimes, Ina gate array (: gate arra base array (like times called a primit interconnect between transist form the transistors and then stockpile diffused array for this reason). Since fe can use the stockpiled met- + Channeled gate arrays. + Channelless gate arrays. + Structured gate arrays. ese terms when they are used as adjectives explains their The hyphenation of thi construction. For example, in the term “channeled gate-array architecture,” the gare “array is channeled, as will be explained, There are two common ways of arranging (or arraying) the transistors on a MGA: in a channeled gate array we leave space between the rows of transistors for wiring: the routing on a channelless gate array ses rows of unused transistors, The channeled gate array was the first to be devel- ‘oped, but the channelless gate-array architecture is now more widely used, A struc- tured (or embedded) gate array can be either channeled or channelless but it includes (or embeds) a custom block "12 CHAPTER1 INTRODUCTION TO ASICS 1.1.4 Channeled Gate Array A Figure 1.5 shows a channeled gate array. The important features beled” MGA are: + Only the interconnect is customized. i e cells. «+ The interconnect uses predefined spaces between row’ of a i weeks. + Manufacturing lead time is between two days and two anepoSuBSSISssss09 base cell y die. The FIGURE 1.5 A channeled gate-arra aside for spaces between rows of the base cells are set interconnect. felefalsfal=fel=[=[e[e[a(efele[=[=lefele) + to a CBIC—both use rows of cells separated the space for interconnect whereas the ‘A channeled gate array is similar 1 by channels used for interconnect. One difference is that trween rows of cells are fixed in height in a channeled gate array, space between rows of cells may be adjusted in a CBIC. 1.1.5. Channelless Gate Array lless gate array (also known as a channel-free gate Figure 1.6 shows a chann ‘or SOG array). The important features of this type of array, sea-of-gates array, MGA are as follows: + Only some (the top few) mask layers ar tween two days and two weeks. e customized—the interconnect. + Manufacturing lead time is be! ‘The key difference between a channelless gate array and channeled gate artay is that there are no predefined areas set aside for routing between cells on a channelless gate array, Instead we route over the top of the gate-array devices. We can do this because we customize the contact layer that defines the connections between metall, the first layer of metal, and the transistors. When we use an area of transistors for routing in a channelless array, we do not make any contacts to the devices lying underneath; we simply leave the transistors unused.1.1" TYPES OF ASICS Doooscseseo0s0000 base cell FIGURE 1.6 Achannelless gate-array or sea-of- gates (SOG) array die. The core area of the die is Com pletely filled with an array of base cells (the base array). jauoSooouoooNS| array of, base cell (not all shown) fanoecoo0 SoDoBSooseSCoUooooS! TelelelelsleIeIeIeIele] (SleteleTeteleleleIe] “The logic density—the amount of logic that can be implemented in a given 6 i- con area-is higher for channelless gate arrays than for channeled gate arrays. This sully attributed to the difference in structure between the two types of array, In feet, the difference occurs because the contact mask is customized in a channelless fate array, but is not usually customized in a channeled gate array. This leads to jTencer cells in the channelless architectures. Customizing the contact layer in & Ghannelless gate array allows us to increase the density of gate-array cells because ‘we can route over the top of unused contact sites. 1.1:6 Structured Gate Array ‘An embedded gate array or structured gate array ( masterimage) combines some of the features of CBICs and MGAs. advantages of the MGA is the fixed gate-array base cell. This makes the implemen- tation of memory, for example, difficult and inefficient. In an embedded gate array we set aside some of the IC area and dedicate it to a specific function. This embed- ded area either can contain a different base cell that is more suitable for building memory cells, or it can contain a complete circuit block, such as a microcontroller. Figure 1.7 shows an embedded gate array. The important features of this type of MGA are the following: + Only the interconnect is customized. + Custom blocks (the same for each design) can be embedded. + Manufacturing lead time is between two days and two weeks. ‘An embedded gate array gives the’ improved area efficiency and increased per- formance of a CBIC but with the lower cost and faster turnaround of an MGA. One disadvantage of an embedded gate'array is that the embedded function is fixed. For example, if an embedded gate array contains an area set aside for a'32k-bit memory, {also known as masterslice or One of the dis- 1314 CHAPTER INTRODUCTION TO ASICS gD eoHSHBTROSGSSOSOS sl ‘embedded |O} | block al | 3) 5 S| a 3 3 FIGURE 1,7 A structured or embedded gate-array la a die showing an embedded block in the upper left corner fiom e | (a static random-access memory, for example). The p| a rest of the die is filled with an array of base cells. 8 array of | fel base cal S| io (not all aI fs shown) iS Spossseooooooodesccod) but we only need a 16k-bit memory, then we may have to waste half of the embed- ded memory function. However, this may still be more efficient and cheaper than implementing a 32 k-bit memory using macros on a SOG array. ‘ASIC vendors may offer several embedded gate array structures containing dif- ferent memory types and sizes as well as a variety of embedded functions. ASIC companies wishing to offer a wide range of embedded functions must ensure that enough customers use each different embedded gate array to give the cost advan- tages over a custom gate array or CBIC (the Sun Microsystems SPARCstation described in Section 1.3 made use of LSI Logic embedded gate arrays—and the 10K and 100K series of embedded gate arrays were two of LSI Logic’s most successful products). 1.1.7 Programmable Logic Devices Programmable logic devices (PLDs) are standard ICs that are available in standard. configurations from a catalog of parts and are sold in very high volume to many di ferent customers. However, PLDs may be configured or programmed to create a part ‘customized to a specific application, and so they also belong to the family of ASICs. PLDs use different technologies to allow programming of the device. Figure 1.8 shows a PLD and the following important features that all PLDs have in common: + No customized mask layers or logic cells + Fast design turnaround + A single large block of programmable interconnect, + A matrix of logic macrocells that usually consist of programmable array logic followed by a flip-flop or latch The simplest type of programmable IC is a read-only memory (ROM). The most common types of ROM use a metal fuse that can be blown permanently. (3 programmable ROM or PROM). An electrically programmable ROM, of1.1. TYPES OF ASICS la IS | ‘macrocell die. FIGURE 1.8. Aprogrammable logic device (PLO) The macrocells typically consist of programmable array [ogie followed by a flip-flop or latch. The macrocells are Gainected using a large programmable interconnect block. a | | Ig| Ip| 5 [sl | | | programmabie |5] interconnect [a EPROM, uses programmable MOS transistors whose characteristics are altered by applying a high voltage. You can erase an EPROM either by using another high volt- age (an electrically erasable PROM, or EEPROM) or by exposing the device t0 ultraviolet light (UV-erasable PROM, or UVPROM). There is another type of ROM that can be placed on any ASIC—a mask-programmable ROM (mask-programmed ROM or masked ROM). A masked ROM is a regular array of transistors permanently programmed using custom mask patterns. An embedded masked ROM is thus a large, specialized, logic cell. The same programmable technologies used to make ROMs can, be applied.to more flexible logic Structures. By using the programmable devices in a large array of ‘AND gates and an array of OR gates, we ereate a family of flexible and programma ‘ays. The company Monolithic Memories (bought ble logic devices called logic arr: by AMD) was the first to produce Programmable Array Logic (PAL®, a registered trademark of AMD) devices that you can use, for example, as transition decoders for state machines. A PAL can also include registers (flip-flops) to store the current state information so that you can use a PAL to make a complete state machine. Just as we have a mask-programmable ROM, we could place a logic array as a cell on a custom ASIC. This type of logic array is called a programmable I array (PLA). There is a difference between a PAL and a PLA: a PLA has a pro- grammable AND logic array, or AND plane, followed by a programmable OR logic array, o OR plane; a PAL has a programmable AND plane and, in contrast to a PLA, a fixed OR plane. :. Depending on how the PLD is programmed, we can have an erasable PLD (EPLD), or mask-programmed PLD (sometimes called a masked PLD but usually just PLD). The first PALs, PLAs, and PLDs were based on bipolar technology and used programmable fuses or links. CMOS PLDs usually employ floating-gate tran- sistors (see Section 4.3, "EPROM and EEPROM Technology”). TD oooSseeSCCo0su00o falaferelerelelslalelelelsle]eT=leTe[el 15 (elelefelelelsI=I=I«Ie] [squaoosaE16 CHAPTER 1 INTRODUCTION TO ASICS 1.1.8 Field-Programmable Gate Arrays A step above the PLD in complexity is the field-programmable gate array tween an FPGA and a PLD—an FPGA is (FPGA). There is very little difference bet 5 usually just larger and more complex than a PLD. In fact, some companies that man. tfacture. programmable ASICs call their products FPGAs and some call them complex PLDs. FPGAs are the newest member of the ASIC family and ats rapidly growing in importance, replacing TTL in microelectronic systems. Even though an FPGA is a type of gate array, we do not consider the term gate-array-based ASICs to include FPGAs, This may change as FPGAs and MGAs start to look more alike, Figure 1.9 illustrates the essential characteristics of an FPGA: + None of the mask layers are customized. + A method for programming the basic logic cells and the i rammable basic logic cells that can imple- interconnect. + The core is a regular array of progi ment combinational as well as sequential logic (fip-flops). «A matrix of programmable interconnect surrounds the basic logic cells. + Programmable 1/O cells surround the core. + Design turnaround is a few hours. We shall examine these features in detail in Chapters 4-8. (afoKsfelels\al=[sleTelslelelelelsleleNs) rogrammable~ [9 | asic logic : cell iB Ooo yoyo! |g IGURE 1.9 A field-programmable gate array | S| (FPGA) GA FPGAs contain a regular structure ie eee g programmable basic logic cells surrounded by | Pogrammabie interconnect. The exact ype, iz, ) MCMC IC | number of the programmable basic logic cells. Cl | varies tremendously. 7 5 CII Bl S| (Oloyoloyoyory || a MOO OOo |S programmable~|a| SI interconnect |SGuSboo0R000oqq000009 1.2 Design Flow Aaa ee coe steps to design an ASIC; we call this a design Figure 1.10) with a trict deasipon of the finenon stein Cone tone eee a " fardoare daeripon hagaege HDL he ee eT1.2 DESIGNFLOW 17. start 1 design entry logical panonaa. relayout ] c pon Simulation eo design ee VHDUVerilog logic synthesis system partioning @ panaqeo. floorplanning ystlayout pl Simulation (5) chi faune el p Vt circuit routing 3 ‘ placement block I ‘com physical I design @ nil CI logic cells T extraction @ backannotated Ti netlist finish 2 3: 4, 5. 6. 7. 8. FIGURE 1.10 ASIC design flow. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a netlist—a description of the logic cells and their connections, System partitioning. Divide a large system into ASIC-sized pieces. Prelayout simulation. Check to see if the design functions correctly. Floorplanning. Arrange the blocks of the netlist on the chip. Placement. Decide the locations of cells in a block. Routing. Make the connections between cells and blocks. Extraction. Determine the-resistance and capacitance of the interconnect,18 CHAPTER1 INTRODUCTION TO ASICS ks with the added loads 9. Postlayout simulation. Check to see the design still wor of the interconnect. Steps 1-4 are part of logical design, and SiCPt 5-9 are part of physical design. ‘There ie some overlap. For example, system partion might be considered as either logical or physical design. To put jit another Way when we are performing sys- tem partitioning we have to consider both logical and physical factors. Chapters Sg ar this book is largely about Fogieal design ‘and Chapters 15-17 largely about physical design. 1.3. Case Study Sun Microsystems released the ‘SPARCstatio design but a very important example because make extensive use of ASICs to achieve the foll Better performance at lo 989. It is now an old vin April 1 the first workstations to it was one of # lowing: wer cost ‘ower, and quiet operation + Reduced numbe! 1 assembly, and impro" ‘The SPARCstation contains about 50 ICs on the excluding the DRAM used for the system memory (standard parts). The SPARCstation I designers partitioned “ne system into the nine ASICS shove in Table 1.1 and wrote specifications for ane ASIC —this took about three months LSI Logic and Fujitsu designed the ‘SPARC integer unit (IU) and floating-point ard design unit (FPU) to these specifications, ‘The clock ASIC is a fairly straightforw. g ASICs, the video controller/data buffer, the RAM control- Seese (DMA) controller are defined by the 32-bit her ASICs that they connect to, The rest of the system Cs: the cache controller, memory-management ‘These three ASICs, with the 1U,and FPU. have the aths and determine the system partitioning. The design of 1 took five Sun engineers six months after the specifications the Sun engineers simulated the entire erating system (SunOS)- wed reliability Compact size, reduced P system motherboard — + of parts, easie ler, and system bus ( is partitioned unit (MMU), and th most critical timing P: ASICs 3-8 in Table 1. ‘vere complete. During the design proces® SPARCstation 1—including execution of the Sun o (SBus) and the ot! into three more AS! data buffer. the SPARCstation 10 ty brochures (known 8 ms Created! = im Section 1.3 and Section 15.3 is from "2 and pp. 27-28 and from two pul “Concept to System: How Sun Microsys [ASIC System Technology.” A- Bechtolsheim, T- rons: J-H, Huang and D. Boyle of LSU: ion 1: Beyond the 3M Hi not include these as references dit to Andy Bechtolsheim "Some informat “Architecture Guide—May 1992, P- “sparkle sheets"). ‘The first is ‘SPARCstation 1 Using LSI Logic’s. Insley, and J. Ludemann of Sun Microsyst LSI Logic publication. The second paper raeirg and E. Frank, a Sun Microsystems publication. I did a y are impossible to obtain now. ‘but I would like to give cre jun Microsystems and LSI Logic engineers.