1530 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO.

6, JUNE 2013

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V

Supply, 52.5-nW, 0.55-V Subbandgap Reference
Circuits for Nanowatt CMOS LSIs
Yuji Osaki, Member, IEEE, Tetsuya Hirose, Member, IEEE, Nobutaka Kuroki, and Masahiro Numa, Member, IEEE

Abstract—This paper presents bandgap reference (BGR) and significantly reduced. One reason for this is the use of resistors.
sub-BGR circuits for nanowatt LSIs. The circuits consist of a The resistors in most reference circuits are used to generate cur-
nano-ampere current reference circuit, a bipolar transistor, and
rent or voltage to control the temperature characteristics of the
proportional-to-absolute-temperature (PTAT) voltage generators.
The proposed circuits avoid the use of resistors and contain only output reference voltage [3]–[9]. When we use a moderate value
MOSFETs and one bipolar transistor. Because the sub-BGR for resistance, sufficient current for the resistors is required and
circuit divides the output voltage of the bipolar transistor without power dissipation therefore cannot be reduced. Although it can
resistors, it can operate at a sub-1-V supply. The experimental
be reduced if we accept using a large value for resistance, the
results obtained in the 0.18- m CMOS process demonstrated that
the BGR circuit could generate a reference voltage of 1.09 V and resistors will occupy a large area of the silicon.
the sub-BGR circuit could generate one of 0.548 V. The power Resistor-less voltage reference circuits that operate at
dissipations of the BGR and sub-BGR circuits corresponded to nanowatt power have been reported [10]–[12]. However, be-
100 and 52.5 nW.
cause the output reference voltages of these circuits are based
Index Terms—Bandgap reference (BGR) circuits, CMOS analog on the threshold voltage of MOSFETs, the voltages will change
integrated circuits, low voltage, nanowatt, reference circuits.
with process variations [10]–[12]. Therefore, they are not
suitable for use as voltage reference circuits.
This paper presents a nanowatt BGR circuit that does not use
resistors [13]. In contrast to Hirose et al. [13], we use a different
I. INTRODUCTION 0.18- m CMOS process to demonstrate the robustness of our
BGR circuit architecture. The proposed BGR consists of a
T HE development of nanowatt LSIs is expected to lead to
the expansion of next-generation power-aware applica-
tions such as life-log and life-assist medical devices, environ-
nano-ampere current reference circuit, a bipolar transistor, and
proportional-to-absolute-temperature (PTAT) voltage gener-
ators. Because the circuit only consists of MOSFETs except
mental sensors, and wireless sensor networks [1], [2]. Because
for the bipolar transistor, it can generate a bandgap voltage
they must operate for a long time with less-than-ideal energy
without resistors. In addition, a sub-BGR circuit that generates
supply from microbatteries or from surrounding natural energy,
voltage lower than 1.2 V is also presented. The proposed
we need to design LSIs that operate with extremely low power
sub-BGR uses a voltage divider. The voltage divider accepts
dissipation. To develop such LSIs, we must first develop voltage
the base-emitter voltage of the bipolar transistor and generates
reference circuits because they are one of the most fundamental
a sub-1-V reference voltage in combination with the PTAT
analog building circuits. Here, we describe process, voltage, and
voltage generators. Therefore, the proposed sub-BGR is useful
temperature (PVT) variation-tolerant voltage reference circuits
as a reference circuit in sub-1-V LSIs.
that can operate at several tens of nanowatts or less.
This paper is organized as follows. Section II presents the op-
Bandgap reference (BGR) circuits are widely used in modern
erating principles behind our proposed circuits. Section III de-
LSIs to generate a reference voltage on chips. The generated
scribes the implementation of the circuits using 0.18- m CMOS
voltage is used for various analog signal processes. Although
process technology with deep N-well option and presents the
several BGRs have been developed, the power dissipations of
experimental results with a fabricated proof-of-concept chip.
most of them exceed nanowatt power [3]–[7] and have not been
Extremely low power dissipation of 100 nW for the BGR and
52.5 nW for the sub-BGR were achieved. Section IV concludes
Manuscript received September 04, 2012; revised December 12, 2012;
the paper.
accepted March 02, 2013. Date of publication April 03, 2013; date of current
version May 22, 2013. This work was supported in part by VLSI Design and
Education Center (VDEC), The University of Tokyo with the collaboration with
Cadence Design Systems, Inc. and Mentor Graphics, Inc., STARC, KAKENHI, II. ARCHITECTURE
and the New Energy and Industrial Technology Development Organization
(NEDO). This paper was approved by Associate Editor Boris Murmann. A. Characteristics of Subthreshold Current
Y. Osaki is with Panasonic Corporation, 571-8501 Osaka, Japan.
T. Hirose, N. Kuroki, and M. Numa are with the Department of Electrical
Subthreshold operation achieves ultralow-power operation
and Electronics Engineering, Kobe University, 657-8501 Kobe, Japan (e-mail:
[email protected]). because the subthreshold current is of the order of nano-am-
Digital Object Identifier 10.1109/JSSC.2013.2252523 peres. When a drain–source voltage of a MOSFET is

0018-9200/$31.00 © 2013 IEEE

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 OSAKI et al.: 1.2-V SUPPLY, 100-NW, 1.09-V BANDGAP AND 0.7-V SUPPLY, 52.5-NW, 0.55-V SUB-BGR CIRCUITS FOR NANOWATT CMOS LSIs 1531

Fig. 1. Architecture of proposed BGR circuit.

Fig. 2. PTAT voltage generator consisting of differential pair circuit.

higher than roughly 0.1 V, subthreshold current is expressed

as

(1)

where is the aspect ratio of the transistor,

is a process-dependent parameter, is the car-
rier mobility, is the gate–oxide capacitance,
is the oxide permittivity, is the oxide thickness, is the
subthreshold slope factor, is a gate–source voltage,
is the thermal voltage, is the Boltzmann constant,
is the absolute temperature, is the elementary charge, and
is the threshold voltage of the MOSFET [14]. We will use
(1) to analyze the characteristics of a subthreshold MOSFET. Fig. 3. Schematic of nano-ampere current reference circuit [15].
Note that, in this work, we assumed that is a constant param-
eter (in the process used, 1.14 and 1.40 for nMOSFETs and
pMOSFETs, respectively). However, is not constant in actual the pMOS-current mirror. Therefore, PTAT voltage can be gen-
devices and depends on gate-oxide and depletion-layer capac- erated by making .
itances [14]. This must be taken into account in high-accuracy The nano-ampere current reference circuit generates a 10-nA
applications. current [15] and supplies it to the others. Fig. 3 is a schematic
of a nano-ampere a current reference circuit (no start-up circuit
B. BGR is shown) we used [15]. The circuit consists of a bias voltage
Fig. 1 shows the architecture of the proposed BGR circuit. circuit, the PTAT voltage generator, and a current source cir-
It consists of a nano-ampere current reference circuit, a bipolar cuit. All MOSFETs operate in the subthreshold region except
transistor, and a PTAT voltage generator. The operating princi- for the MOS resistor that operates in the strong-inver-
ples of the circuits are as follows. sion and deep triode regions. The gate length and the gate
PTAT voltage in conventional BGR circuits is generated width of and are the same, and they are biased at
by using bipolar transistors and resistors. However, as we the same current. The PTAT voltage generator adds a voltage to
explained in the previous section, it is not advantageous to use the gate–source voltage of in order to increase that of .
resistors at nano-ampere current levels. Fig. 2 shows the PTAT The difference in their gate–source voltages forced across MOS
voltage generator we used [8], [13]. It consists of a differential resistor , which is operating in the strong-inversion and deep
pair with a current mirror. When the MOSFETs operate in the triode regions. The value of the MOS resistor is defined by
subthreshold region, gate-to-gate voltage in this circuit
can be expressed from (1) as (3)

Equally sized MOSFETs and make their threshold volt-

ages similar, so the value of the generated current is robust to
process variations [15]. In [15], the generated current in 15 sam-
ples from one wafer exhibited a variance of 14.1%.
The bipolar transistor accepts the current through a current
(2) mirror and generates a base-emitter voltage , which is ex-
pressed as
where and correspond to aspect ratios in the differ-
(4)
ential pair, and and correspond to aspect ratios in
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 1532 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 6, JUNE 2013

Fig. 4. Architecture of proposed sub-BGR circuit.

where is the saturation current of the bipolar transistor [14]. Output reference voltage in the bandgap voltage ref-
Because decreases linearly with temperature, (4) can be erence circuit can be expressed from (5) and (6) as
simplified as

(5)

where is the bandgap voltage of the silicon (i.e., 1.2 V)

and is the temperature coefficient of . Because has
a negative dependence on temperature, the PTAT voltage gen-
erator is used to cancel out this dependence. As (5) is approxi- (7)
mated by the first order, has higher order dependencies on Therefore, the condition can be obtained by
temperature. Therefore, there will be nonlinearities in the output appropriate choice of the aspect ratios of the transistors in the
voltage even though we cancel out the negative dependence of differential pairs and current mirrors, and of .
on temperature. However, the nonlinearities can be com-
pensated for if we use a technique of curvature compensation C. Sub-BGR
such as that reported by Ge et al. [5]. The bias current of the Because the bandgap voltage of silicon is larger than 1.2 V,
bipolar transistor also determines the accuracy of . Because BGR circuits require more than 1.2 V of supply voltage. Here,
bias current is generated from the current reference circuit and we present a voltage reference circuit that operates at sub-1-V
the generated current is tolerant to threshold voltage variations, power supply.
the current variations can be minimized [15]. Therefore, the ef- Fig. 4 shows a block diagram of the proposed sub-BGR cir-
fect of bias current variations can also be minimized. cuit. The circuit uses a voltage divider circuit. The voltage di-
The PTAT voltage generator in Fig. 2 supplies voltage vider circuit divides the base-emitter voltage . The output
which has a positive dependence on temperature as discussed voltage of the voltage divider can be expressed as
previously. However, because in (2)
is included in a logarithmic function, it must have a large (8)
value ( 40 M) in order for the positive temperature coefficient
of to cancel out the negative temperature dependence where is the division ratio of the divider. Then, the PTAT
( 2 mV/ C) of base-emitter voltage . Moreover, making voltage generator is also used to cancel the negative dependence
much larger than requires a large area on temperature of . The reference output voltage
and this cannot be made use of. We use a number of differential of this circuit is expressed as
pairs and cascade them to obtain sufficient PTAT voltage.
When the differential pairs are connected in a cascade, total
gate-to-gate voltage can be expressed as

(9)

where is the number of differential pairs. Note that because

base-emitter voltage is divided by , the negative temper-
(6) ature coefficient is also divided by . Therefore, the required
PTAT voltage decreases and the number of differential pairs can
be reduced. As a result, both the area and the current dissipation
where is the number of differential pairs. Because the ra- in the sub-BGR circuit are less than those in the BGR circuit.
tios of are multiplied, large PTAT A zero temperature coefficient voltage is obtained in a similar
voltage can be efficiently obtained from (6). way to that of the BGR circuit by designing the aspect ratios so
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 OSAKI et al.: 1.2-V SUPPLY, 100-NW, 1.09-V BANDGAP AND 0.7-V SUPPLY, 52.5-NW, 0.55-V SUB-BGR CIRCUITS FOR NANOWATT CMOS LSIs 1533

Fig. 5. Schematic of proposed BGR circuit.

that the second term in (9) becomes zero, and the voltage can be sizes based on the results of Monte Carlo simulations assuming
rewritten as both die-to-die (D2D) and within-die (WID) variations in
transistor parameters [16]–[18].
(10) Five differential pairs were used in the BGR in this design.
The reference output voltage of this circuit can be ex-
Note that, if is divided by after it is generated, the pressed as
supply voltage of the circuit requires more than 1.2 V. This
is because the circuit has to generate in advance. How-
ever, because the proposed sub-BGR circuit divides the base-
emitter voltage and output reference voltage is lower (11)
than 1.2 V, the sub-BGR circuit can operate at sub-1-V power
supply.
A zero temperature coefficient voltage can be obtained by de-
III. EXPERIMENTAL RESULTS signing the aspect ratios in the differential pairs and the current
mirrors so that the second term in (11) becomes zero.
A. Circuit Implementation We used a source-follower circuit as a voltage divider circuit
We fabricated a proof-of-concept chip using a 0.18- m, in the sub-BGR. The voltage divider circuit divided the base-
1-poly, 6-metal CMOS process with deep N-well option. emitter voltage in half. Each body terminal of the nMOS-
Figs. 5 and 6 show the schematics for the proposed BGR and FETs in the source-follower circuit was connected with their
sub-BGR circuits. A cascode configuration was used in the source terminal to avoid the body effect of the transistor. We
circuits to reduce dependence on supply voltage. All transistor ignored the gate and substrate leakage currents because these
sizes are provided in Figs. 5 and 6. We determined the transistor leakage currents were smaller than the subthreshold current in
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 1534 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 6, JUNE 2013

Fig. 6. Schematic of proposed sub-BGR circuit.

that we used two pMOS differential pairs as first PTAT voltage

generators because would have been too low to apply an
nMOS PTAT generator. The reference output voltage of
this circuit can be expressed as

(13)

Fig. 7. Chip micrograph and layout. Therefore, a zero temperature coefficient voltage can be ob-
tained by designing the aspect ratios in the differential pairs and
the current mirrors so that the second term in (13) becomes zero,
the process we used. The output voltage of the source-fol- and the voltage can be rewritten as
lower circuit can be expressed as

(12) (14)

Then, three differential pairs were used in the sub-BGR to Fig. 7 shows a micrograph of the chip and the layout for each
cancel the negative dependence on temperature of . Note circuit. The areas that the current reference (CUR including the
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 OSAKI et al.: 1.2-V SUPPLY, 100-NW, 1.09-V BANDGAP AND 0.7-V SUPPLY, 52.5-NW, 0.55-V SUB-BGR CIRCUITS FOR NANOWATT CMOS LSIs 1535

Fig. 8. (a) Measured operating current and (b) measured voltages of and as a function of .

Fig. 9. (a) Measured voltage of and (b) measured voltage of as a function of temperature at three supply voltages.

bipolar transistor), the BGR, and the sub-BGR circuits occupy

correspond to 0.0144 mm , 0.0150 mm , and 0.0102 mm . We
measured nine sample chips.

B. Results

Fig. 8(a) plots the measured operating current in the cur-

rent reference circuit as a function of . The circuit oper-
ated at more than 0.7-V power supply and the current was about
6 nA. The line regulation of the current was 6.47%/V. Fig. 8(b) Fig. 10. Measured operating current as a function of temperature in nine
plots the measured voltages of and as a function samples.
of . The BGR circuit generated as 1.08 V at more
than 1.2-V power supply. The sub-BGR circuit could operate at room temperature were 100 and 52.5 nW, respectively. The av-
sub-1-V power supply (i.e., 0.7 V) and was 0.549 V. erage TCs of the BGR and the sub-BGR circuits corresponded
Fig. 9(a) and (b) plots the measured voltages of and to 147 and 114 ppm/ C, respectively. The output voltages ex-
as a function of temperature from 40 C to 120 C at hibited a nonlinear dependence on temperature as was explained
three different supply voltages. The temperature coefficients in the previous section. We can reduce the dependence on tem-
(TCs) have similar characteristics across different supply perature by using a technique of curvature compensation.
voltages. Fig. 12(a) and (b) shows the distributions of and
Fig. 10 plots measured operating current as a function of in nine samples at 20 C with 1.5-V power supply. The
temperature from 40 C to 120 C in nine samples. The cur- output voltages were not trimmed. The coefficients of variation
rent reference circuit generated a nano-ampere current over a ( , where and are the mean value and the standard
wide range of temperatures. The current increased with different deviation) for and were 0.737% and 1.05%,
dependencies on temperature at higher temperatures. We as- respectively. The coefficients of variation were very small
sumed that the reason for this was leakage current. However, because the nine samples were removed from the same wafer.
it did not have much influence on the operation of our circuit Fig. 13 plots the measured PSRRs of and . The
because the increase in current was small. Fig. 11(a) and (b) PSRR of at 100 Hz and 1 MHz corresponded to 62 and
plots the measured voltages of and as a function 14 dB, respectively. The PSRR of at 100 Hz and 1 MHz
of temperature from 40 C to 120 C. The average power dis- corresponded to 56 and 8.7 dB, respectively. The PSRR of
sipations of the BGR and sub-BGR circuits in nine samples at was better than that of because the voltage divider
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 1536 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 6, JUNE 2013

Fig. 11. (a) Measured voltage of and (b) measured voltage of as a function of temperature in nine samples.

Fig. 12. Distributions of (a) and (b) for nine samples.

loads and/or large capacitive loads. However, the increase in

bias current leads to high power dissipation. We have to design
bias current in accordance with applications.
Table I summarizes the performance of the proposed BGR
and sub-BGR circuits and compares them with other reported
reference voltage circuits [3]–[13]. The proposed circuits op-
erate with ultralow power dissipation. The minimum supply
voltage of the sub-BGR is especially low at 0.7 V.

C. Discussion
The coefficients of variation in the experimental results were
very small because the nine samples were obtained from the
Fig. 13. Measured PSRRs of and . same wafer. In order to evaluate robustness to process varia-
tions, we performed Monte Carlo SPICE simulations. The re-
sults for 500 runs are depicted in Fig. 14. The coefficients of
in the sub-BGR circuit was affected by the change in the supply variation for and were 0.351% and 1.61%, re-
voltage and it degraded the PSRR of . spectively. It was reported to be 7% in [11]. Thus, our pro-
Because our BGR and sub-BGR dissipated quite a low posed circuit is superior in process variations. The improvement
amount of power, they will suffer from poor noise perfor- comes from the fact that our proposed circuit is based on not the
mance, poor driving capabilities, and a slow start-up time. threshold voltage of MOSFETs, but the bandgap voltage of the
Note that, the simulated noise densities of and silicon.
with 4.43-pF on-chip capacitors at 100 Hz were 1.72 and Output voltage , 1.09 V, in the experimental results
1.90 V/ , respectively, and the simulated start-up time was lower than the material bandgap voltage, around 1.2 V.
was 6 ms in our circuit. An on-chip decoupling capacitor will This was because the operating current increases with tempera-
reduce noise. However, it may degrade start-up time. There- ture. Fig. 15 plots the simulated base-emitter voltages s as
fore, the decoupling capacitor should be designed to satisfy a function of temperature from 40 C to 120 C. The s
the required noise accuracy and start-up time depending on were biased with constant bias currents of 10 nA and 1 A. The
applications. The circuits for driving capabilities should not measured biased with the current and their linear fitting
be directly connected to resistive loads because of their poor curves were also shown in the figure. When the bipolar transistor
driving current. Bias current in the last stage of the PTAT accepts the constant currents, s at absolute zero temperature
generators should be increased if we have to drive resistive were almost equal to the material bandgap voltage ( 1.2 V). On
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 OSAKI et al.: 1.2-V SUPPLY, 100-NW, 1.09-V BANDGAP AND 0.7-V SUPPLY, 52.5-NW, 0.55-V SUB-BGR CIRCUITS FOR NANOWATT CMOS LSIs 1537

TABLE I
PERFORMANCE SUMMARY AND COMPARISON

Fig. 14. Distributions of output voltages, as obtained from Monte Carlo simulation of 500 runs.

could generate a reference voltage of 1.09 V and the sub-BGR

circuit could generate one of 0.548 V. The power dissipation of
the BGR circuit was 100 nW and that of the sub-BGR circuit
was 52.5 nW.

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 1538 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 6, JUNE 2013

[11] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 15 Tetsuya Hirose (M’05) received the B.S., M.S., and
ppm/ C, 20 ppm/V CMOS voltage reference circuit consisting of Ph.D. degrees from Osaka University, Osaka, Japan,
suthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 44, no. 7, in 2000, 2002, and 2005, respectively.
pp. 2047–2054, Jul. 2009. From 2005 to 2008, he was a Research Associate
[12] M. Soek, G. Kim, D. Blaauw, and D. Sylvester, “A portable 2-transistor with the Department of Electrical Engineering,
picowatt temperature-compensated voltage reference operating at 0.5 Hokkaido University. He is currently an Associate
V,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2534–2545, Jul. Professor with the Department of Electrical and
2012. Electronics Engineering, Kobe University, Kobe,
[13] T. Hirose, K. Ueno, N. Kuroki, and M. Numa, “A CMOS bandgap and Japan. His current research interests are in the field
sub-bandgap voltage reference circuits for nanowatt power LSIs,” in of nanowatt-power analog/digital mixed-signal inte-
Proc. IEEE Asian Solid-State Circuits Conf., 2010, pp. 77–80. grated circuits design and human-centric intelligent
[14] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. electronic systems.
Cambridge, U.K.: Cambridge Univ., 2002. Dr. Hirose is a member of the Institute of Electronics, Information and Com-
[15] T. Hirose, Y. Osaki, N. Kuroki, and M. Numa, “A nano-ampere current munication Engineers and the Japan Society of Applied Physics.
reference circuit and its temperature dependence control by using tem-
perature characteristics of carrier mobilities,” in Proc. Eur. Solid-State
Circuits Conf., 2010, pp. 114–117.
[16] K. A. Bowman, S. G. Duvall, and J. D. Meindl, “Impact of die-to-die Nobutaka Kuroki received the B.E., M.E., and
and within-die parameter fluctuations on the maximum clock frequency Dr.Eng. degrees in electronic engineering from
distribution for gigascale integration,” IEEE J. Solid-State Circuits, Kobe University, Japan, in 1990, 1992, and 1995,
vol. 37, no. 2, pp. 183–190, Feb. 2002. respectively.
[17] H. Onodera, “Variability: Modeling and its impact on design,” IEICE From 1995 to 2005, he was a Research Associate
Trans. Electron., vol. 89-C, pp. 342–348, 2006. with the Department of Electrical and Electronic En-
[18] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, gineering, Kobe University, where he has been an As-
“Matching properties of MOS transistors,” IEEE J. Solid-State Cir- sociate Professor since 2006. His research interests
cuits, vol. 24, no. 5, pp. 1433–1439, May 1989. include digital signal processing and digital image
processing.
Dr. Kuroki is a member of the IEEJ, Institute of
Electronics, Information and Communication Engineers, and ITE.

Masahiro Numa (M’96) received the B.E., M.E.,

and Dr.Eng. degrees in precision engineering from
the University of Tokyo, Tokyo, Japan, in 1983,
1985, and 1988, respectively.
From 1986 to 1989, he was a Research Associate
with the Department of Precision Engineering, Uni-
versity of Tokyo, Tokyo, Japan, where he became
a Lecturer in 1989. After joining Kobe University,
Kobe, Japan, in 1990, he joined the Department of
Electrical and Electronic Engineering as an Asso-
Yuji Osaki (S’09–M’12) received the B.E., M.E., ciate Professor in 1995 and has been a Professor
and Ph.D. degrees in electrical and electronic engi- since 2004. In 1996, he was a Visiting Scholar with the University of California,
neering from Kobe University, Kobe, Japan, in 2008, Santa Barbara, CA, USA. as a Visiting Scholar. His research interests include
2010, and 2012, respectively. CAD and low-power design methodologies for VLSI, and image processing.
In 2012, he joined Panasonic Corporation, Prof. Numa is a member of the Association for Computing Machinery, IPSJ,
Kadoma, Japan. His current research interests are and Institute of Electronics, Information and Communication Engineers. He
in ultralow-power CMOS circuits and smart sensor served as the Technical Program Committee Chair of the 17th Workshop on
networks. Synthesis and System Integration of Mixed Information technologies (SASIMI
2012). He is currently serving as the General Chair of SASIMI 2013 and the
Chair of the IEEE Circuits and Systems Society, Kansai Chapter.

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