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FPGA implementation of single bit error correction using CRC

Article in International Journal of Computer Applications · August 2012

DOI: 10.5120/8238-1471

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 International Journal of Computer Applications (0975 – 8887)
Volume 52– No.10, August 2012

FPGA Implementation of Single Bit Error Correction

using CRC
Pramod S P Rajagopal A Akshay S Kotain
Department of ECE, Department of E&C, DSCE, Department of E&C, DSCE,
DSCE,VTU,Bangalore,India VTU,Bangalore, INDIA VTU,Bangalore, INDIA

ABSTRACT 2. PRINCIPLE
Transferring data between two points is very essential, also CRC is one of the most famous and robust error control
the accuracy of the transferred data is vital for some critical methods. Its computation resembles a long division operation
applications, but an error during the transmission of data is in which the quotient is discarded and the remainder becomes
very common. The Cyclic Redundancy Check (CRC) method the result, with the important distinction that the arithmetic
is generally used for error detection and correction. In this used is the carry-less arithmetic of a finite field or Modulo-2
paper, we have proposed a new technique for error detection addition. The length of the remainder is always less than or
and correction in case of CRC-16, which is hardware equal to the length of the divisor, which therefore determines
optimized and works at relatively higher frequency and speed. how long the result can be.
In the proposed method, it is possible to detect the exact place
of single bit error and correct them using minimum hardware. In this method, the receiver divides the data by generator
This method involves no look tables and hence is memory polynomial and then gets the remainder. The receiver then
efficient. This paper focuses on effective implementation of uses parallelism technique to correct single bit error by a
this method on FPGA. shifter circuit which will be explained in the following
sections. This improvised proposed method requires zero
Keywords memory and minimum hardware.
CRC, Field Programmable Gate Array, Single bit error Before transmission, the frame produced by CRC encoder
correction, Parallelism, non-lookup technique. consists of check bits cascaded with data bits. These check
bits which are redundant are used for error detection and
1. INTRODUCTION correction at the receiver. For the calculation of checksum
The Internet is growing rapidly in terms of number of users bits, a fixed generator polynomial is chosen. The data bits are
and amount of bandwidth used. Besides the transmission and then divided with the generator polynomial and the resultant
switching speeds, the per-packet operations necessary for remainder is the checksum bits. The division of the data by
internet Protocol (IP) packet forwarding are the current the generator polynomial is performed using the circuit which
limiting factors. As transmission speeds are continually is shown in Figure 1.
increasing, IP packet processing overheads have become the
main bottleneck [5]. The received data may not be same as the
transmitted data because of noise and interference, which
leads to errors during the process of data transmission and
storage. Hence, to achieve better quality data transmission,
coding and detection methods are employed. CRC is very
simple and efficient method to detect and correct the errors. A
Cyclic Redundancy Check (CRC) is a type of function that
takes an input data stream of any length, and produces an
output value of 32-bit or 24 bit integer. Single bit error
correction using look up table technique was presented in [3]
and [4]. A CRC can be used as a checksum to detect
accidental alteration of data during transmission or storage. A
CRC theoretically can correct all single, double and odd bits
in error [6]. The process of encoding and decoding are Fig 1: Polynomial divider.
discussed in the following sections. Initially, all the remainder registers are initialized to zero.
In this paper, we have introduced a new approach for the error Then the data bits are shifted into the circuit with the order
detection and correction using non-look up table technique such that the LSB of data is entered into the circuit first. Now
based on FPGA, in case of CRC. This approach is memory depending upon the generator polynomial, the data is just
efficient and operates at high frequency. Since most of the shifted right or it is added with the feed- back value. Modulo-
methods currently employed are based on look up table 2 addition is performed. Once all the data bits are shifted into
technique, they consume more space and also there will be a the registers, the remainder registers indicates the checksum
reduction in speed because of the overhead required in bits. These checksum bits are cascaded with the data bits
accessing the ROM which stores the look up table. We will before the data is transmitted.
then review the Sunil Shukla [1] method that corrects single The codeword C(x) can be calculated using Equation 1.
bit error and also other look up table optimization techniques
presented in [2]. We have also discussed a method which
( )
makes the algorithm hardware implementable and the results ( ) ( )
( ) (1)
obtained are tabulated.

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 International Journal of Computer Applications (0975 – 8887)
Volume 52– No.10, August 2012

The first part of right hand side of Equation 1 represents the Dre represents received data.
checksum bits. Here ‘n’ represents the frame width and ‘k’
represents the data width. As an example taking n= 24 and Receiver again calculates CRC on the received data. Let Ccal
indicates the CRC calculated over Dre at the receiver side. If
k=8 the calculation of checksum bits is shown below.
no error has occurred during transmission then Cre and Ccal
are equal. But if some bit(s) are in error, then Cre and Ccal
x5+x4+x2+x will be in mismatch. In such cases the error needs to be
detected and corrected .Hence we need to calculate the
21 20 18 16
x16+x12 +x5+1 x +x +x +x syndrome which is given by:
x +x +x +x5
21 17 10
Syn=Cre XOR Ccal (4)

x20+x18+x17+x16+x10+x5 If the syndrome is calculated as proposed in [9] which uses a

circuit similar to the circuit as shown in Figure 1, only with
x20+x16+x9+x4 more number of registers, then it requires as many clock
cycles as the number of bits in the codeword. But by using
x18+x17+x10+x9+x5+x4 equation 4, the syndrome can be calculated in minimum
number of clock cycles .This method of syndrome calculation
x18+x14+x7+x2 was proposed in [1] and is an efficient one, hence we have
adopted it.
x17+x14+x10+x9+x7+x5+x4+x2 Table 1. Possible number of error patterns
x17+x13+x6+x
Standard Single Bit Error
x14+x13+x10+x9+x7+x6+x5+x4+x2+x CRC-8 24
CRC-16 32
Here:
Data, D(x):00010011 This paper uses two standards CRC-16 and CRC-8 for
Check bits:00110011011110110 correcting single bit errors. Here we have designed the
Codeword, C(x):00110011011110110__00010011 algorithm to detect more than one error and we will raise a
flag indicating retransmission of the frame if there were more
Similarly the codeword for CRC-16 can be calculated. The than one error.
CRC Encoder is designed to generate the codeword in a single There are 2 cases in which the single bit error can occur. In
clock cycle with high speed and efficiency. the first case, one bit error can occur in the data bits. In the
second case, one bit error can be in checksum bits. Hence the
Frame Structure of CRC-16: total number of possible single bit errors in data for both the
Check bits (32 down to 17) Data bits(16 down to 1) standards is shown in Table 1.
For CRC-16 if ‘i’ is the position of the error then for case 1)
1≤ i ≤16 and for case 2) 17≤ i ≤32 . Similarly for CRC-8 only
Frame Structure of CRC-8: the limits will change.
Check bits (24 down to 9) Data bits(8 down to 1)
In our proposed method we have used a new technique for
detecting errors in both the cases (described in previous
3. PROPOSED METHOD FOR ERROR paragraph). This method is an outcome of the fact that if an
DETECTION AND CORRECTION error occurs as in case 2 then the syndrome pattern will have
In this paper, we will be presenting a unique way of 1’s equal to no. of bits in error. As we know, we only have to
implementing multiple bit error detection and single bit error correct the error in the data bits, there is no need to correct the
correction using CRC for a frame width of 24 bits and 32 bits. error which has occurred in the checksum bits. But we need to
Let Ftr be the frame transmitted in which the checksum is detect the errors in the checksum bits. This method of analysis
appended after 16 or 8 bits of data. We can express Ftr as is advantages since it reduces memory requirements by 76%
shown in Equation 2. and also we need to worry only about the errors in data, this
reduces the load on the computational block of the receiver.
Ftr = Dtr & Ctr (2)
The analysis of the two cases mentioned above is explained in
detail by using tables. The syndrome pattern for Case 2 for
Where, CRC-16 is shown in Table 2. This pattern is similar even for
& - concatenation operator. CRC-8. As we can see the pattern consists of only bit with
Dtr- transmitted 16 or 8 bit data. logical level 1. Similarly Table 3 represents the syndrome
Ctr - transmitted 16 bit checksum. patterns of the Case 1 for CRC-16 and CRC-8 standards.

At the receiver side, let Fre be the received frame as shown in In [1] only lower 8 bits are used for addressing leading to 256
Equation 3. memory locations. Also, the no. of patterns to be checked in
[1] is only 32. Hence the above type of addressing is not
Fre = Dre & Cre (3) applicable. Here we require the entire 16 bits of the syndrome
for locating and correcting the data. This results in 65536
Where,
memory locations. Considering a ROM with 65536 or 256
Cre indicates received checksum. memory locations is not so efficient when compared to our

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 International Journal of Computer Applications (0975 – 8887)
Volume 52– No.10, August 2012

method of not using any memory block at all. We can analyze Table 3.
the syndrome more effectively without using any memory. Syndrome patterns of single bit error in data bits
The use of ROM [8] also introduces complexity into the
design, since we need to constantly read error patterns from it The bit in The bit in
and to take care of correct timing. Syndrome pattern error for error for
CRC-8 CRC-16
Table 2.
1000010000001000 8 16
Syndrome patterns of single bit error in check bits
0100001000000100 7 15
Location of the bit in 0010000100000010 6 14
Syndrome pattern
error (i) 0001000010000001 5 13
0000000000000001 17 1000110001001000 4 12
0000000000000010 18 0100011000100100 3 11
0000000000000100 19 0010001100010010 2 10
0000000000001000 20 0001000110001001 1 9
0000000000010000 21 1000110011001100 - 8
0000000000100000 22 0100011001100110 - 7
0000000001000000 23 0010001100110011 - 6
0000000010000000 24 1001010110010001 - 5
0000000100000000 25 1100111011000000 - 4
0000001000000000 26 0110011101100000 - 3
0000010000000000 27
0011001110110000 - 2
0000100000000000 28
0001100111011000 - 1
0001000000000000 29
0010000000000000 30
0100000000000000 31 But, in the proposed method the same circuit in Figure 2 is
1000000000000000 32 used but more number of clock cycles are required. That is
when all the 7 received bits are entered into the syndrome
calculator, ‘0’s are now fed into it, from 8th shift onwards as
To explain the method of correcting single bit error that we shown Table 4. Each time a ‘0’ is fed into the circuit, the shift
have proposed let us consider an example of (7,4) CRC register contents are tabulated. This process of feeding ‘0’s
code as in [9]. The syndrome generator circuit for this continues till the shift register contents read S0 S1 S2 =100. In
codeword is shown Figure. 2. This circuit of shift registers general for (n-k) shift register, the contents should read S0,
is similar to the circuit shown in Figure 1 except that it has S1……. Sn-k-1 = 1 0 0………….0. i.e., 1 followed by (n-k-1)
only three shift registers corresponding to three check bits in number of 0s. In Table (4), we find that at the 12th shift we
the codeword. get shift register contents as 100. The error is then located and
corrected as given below.
Table 4.
Contents of shift register in the syndrome calculator

No. of Input Shift Register Contents

shifts Z(x) S0 S1 S2
Initialization and Shift register contents are
LSB of Z(x) enter cleared
first 0 0 0
1 1 1 0 0
2 0 0 1 0
3 1 1 0 1
Fig 2: syndrome circuit for (7,4)
4 0 1 0 0
Here the generator polynomial used is g(x)=1+x+x3. The 5 1 1 1 0
received vector Z=1110101 with three check bits and a 6 1 1 1 1
nibble of data. In this codeword first three MSB bits are 7 1 0 0 1
check bits which is concatenated with a nibble of data. Here 8 0 1 1 0
the 3rd MSB or 3rd Check bit is in error. So we need to 9 0 0 1 1
detect it and correct it. In conventional method the output of 10 0 1 1 1
the circuit in Figure 2 which is syndrome is used to address 11 0 1 0 1
a look up table which actually stores the error pattern. This 12 0 1 0 0
error pattern is then XORed with the CRC frame to get the
correct data.

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 International Journal of Computer Applications (0975 – 8887)
Volume 52– No.10, August 2012

As we can see from Table (4) after 7th shift we get the with the error pattern register content. If not then the
syndrome from the circuit in “fig 2”. Since this syndrome is procedure is continued and error pattern register content is
not equal to “000” it indicates an error. Then the procedure shifted towards left by 1 bit. The initial content of error
pattern register is “0000000000000001”.
is continued as explained earlier until 12th shift when shift
register content is “100”. This shift number indicates the The Timing and Control Unit is designed using a state
position of the error as shown below. diagram as shown in “fig 4”. It consists of four states, initially
in S0 we need to compute the syndrome. Hence we need a
delay of 32 clock cycles and received bits must be routed to
syndrome calculator circuit. This is achieved by setting the
mode pin to high and Sel1 pin to low which in-turn connects
clk input to the 5 bit counter and the CRC frame to the
syndrome circuit respectively. So when the Top signal of the
counter becomes 1, it indicates the completion of the delay
required. Then the state transition to S1 occurs where mode
pin turned low so that the counter can count the number of
1’s in the syndrome vector. The counter content C is sent back
The 5th bit counting from right is in error. to the control unit. Concurrently the vector syndrome is
Therefore Error pattern is E=0010000 checked whether or not it is equal to 0 using generic NOR
gate. If true NbE signal goes high. State jumps to S2 if C=1 or
Corrected vector V= Z XOR E NbE=1and the select pin Sel2 is made low which makes the
= 1110101 XOR 0010000 mux connect received data to corrected data. If C≠1 and
V = 1100101 NbE=0 then the control jumps from S1 to S3 which indicates
that a single bit error is present in data bits. In S3 the control
This is the same method employed in correcting single bit unit sets the Sel1 to high which inputs 0’s into the syndrome
error in CRC-8 and CRC-16. calculator. After each clock cycle syndrome is XORed with
“10000…..0” and checked if zero using the same Generic
NOR gate. If true SbE goes high indicating the completion of
4. IMPLEMENTATION ON FPGA the process, if false then error pattern register is shifted
A parallel VLSI architecture of the decoder circuitry is as towards left as explained in previous section. The control unit
shown in “Fig.3”. The syndrome calculator generates the stays in S3 until SbE is 0 . Once SbE is 1 then Sel2 is set as 0
vector syndrome from the received frame based on the circuit to connect the output corrected data to a pattern obtained by
similar to “fig 1”. This operation requires 32 clock cycles and XORing received data with content of error pattern register.
hence this timing is kept track by a Timing and Control Unit
with the help of a 5 bit counter. Then if the syndrome is all The architecture for CRC-8 is similar to Figure 3” but it
zero, it means that the corrected data is same as received data requires a extra comparator circuit after 5 bit counter since
or else if the number of 1’s in the syndrome pattern is equal to initially we need a delay of 24 clock cycles and hence Top
1, it indicates an error in the check bits. Finally, if single bit signal cannot be used. So we use a comparator to check if
error is present in data bits which is indicated by the above counter has reached 24 or not.
equations not being satisfied then 0’s are input into the
syndrome calculator circuit and after each 0 input the vector
syndrome is XORed with the pattern “0000000000000001”
and checked whether the result is zero or not. If it is zero then
the corrected data is obtained by XORing the received data

Fig 3: VLSI Architecture

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 International Journal of Computer Applications (0975 – 8887)
Volume 52– No.10, August 2012

CRC has been introduced for single bit error correction. We

have implemented on FPGA, for two different standards
CRC-8 and CRC-16. We have shown that hardware
implementation on FPGA can be effectively used to improve
the performance of CRC calculations.

Usually components, like shift registers, XOR and NOR gates

are used, so the entire circuit can be easily designed. This
approach is efficient both in terms of hardware and speed. The
additional hardware required is very simple. This technique
works efficiently in case of ASIC design also.

The hardware requirements are tabulated and the algorithm is

Fig 4: state diagram of the control unit tested for all possible inputs using a test bench and the
algorithm performs as designed.
The algorithm has been implemented and verified on Xilinx
Virtex-5 FPGA device. The code was written in VHDL and 6. REFERENCES
[1] Shukla S, Bergmann N W. “Single bit error correction
synthesized using XST (Xilinx synthesis tool). The device
implementation in CRC-16 on FPGA” In: IEEE
used for implementation is xc5vlx30 with speed grade 3. The International Conference on Field-programmable
results obtained are summarized in Table 5. Simulation is Technology. Brisbane,Australia, 2004: 319-322.
carried out using MODELSIM SE 6.5 and the simulation
[2] PAN Yun, GE Ning, DONG Zaiwang. “CRC Look-up
results are shown in Figure 5.
Table Optimization for Single-Bit Error Correction”. In:
TSINGHUA SCIENCE AND TECHNOLOGY ISSN
Table 5. Device utilization of FPGA 1007-0214 18/19 pp620-623 Volume 12, Number 5,
October 2007.
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Max Freq. 10.1109/JRPROC.1961.287814, January 1961.
792.14 274.45 792.14 250.156
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[5] W.W Peterson, E. J. Weldon. “Cyclic Codes for Error
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[6] Norman Matloff. “Cyclic Redundancy Checking”.
[7] “Double Bits Error Correction Using CRC Method” by
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[8] “FPGA implementation of one and two bit error

correction using CRC” by Pramod S P, Akshay S kotain,
Rajagopal A in International conference on recent trends
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[9] Digital and analog communication systems, K. Sam
Shanmugam, John Wiley, 1996.
[10] Giureppe Campobello, Giuseppe Patane. Marco Russo,
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Fig 5: Modelsim Simulation
[12] T. B. Pei and C. Zukowski “High-speed Parallel CRC
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