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sg)
Nanyang Technological University, Singapore.

A dual‑path subsampling PLL with ring VCO phase

noise suppression

Dong, Yangtao; Boon, Chirn Chye; Liu, Zhe; Yang, Kaituo

2023

Dong, Y., Boon, C. C., Liu, Z. & Yang, K. (2023). A dual‑path subsampling PLL with ring VCO
phase noise suppression. IEEE Transactions On Microwave Theory and Techniques.
https://dx.doi.org/10.1109/TMTT.2023.3284279

https://hdl.handle.net/10356/170916

https://doi.org/10.1109/TMTT.2023.3284279

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A Dual-Path Sub-Sampling PLL With Ring

VCO Phase Noise Suppression
Yangtao Dong, Graduate Student Member, IEEE, Chirn Chye Boon, Member, IEEE
Zhe Liu, Graduate Student Member, IEEE, Kaituo Yang, Member, IEEE

Abstract—This paper presents a 2-GHz dual-path sub- and feedback phase noise suppression (FBPNS) [19], are
sampling phase-locked loop (SSPLL) with ring voltage-controlled widely researched recently. ILCM suppresses the ring
oscillator (VCO) phase noise suppression. In addition to the oscillator’s phase noise by injecting a clean reference into the
conventional sub-sampling charge pump (SSCP), a high-pass path oscillator, so the output phase noise is decided by the
from the sub-sampling phase detector (SSPD) to the low-pass filter
multiplication factor and reference noise. Usually, an additional
(LPF) is implemented in the proposed SSPLL. Due to this dual-
path architecture, a new in-band zero and pole are introduced into
frequency tracking loop [9]-[10] is required to detect and adjust
the open-loop transfer function (zero frequency is smaller than the the ring oscillator’s frequency accurately across PVT
pole frequency), which extends the open-loop unit-gain bandwidth variations. In PNFs [11]-[12], voltage-controlled delay lines
without sacrificing the phase margin. Consequently, the phase (VCDLs) are used for the error information extraction and the
noise contribution of the ring VCO is suppressed while the loop output phase noise suppression. Although they achieve an
stability is ensured. Meanwhile, the phase noise contribution of the effective noise transfer function for noise reduction, the usage
high-pass path is negligible compared to the reference and ring of long VCDLs leads to a large power and chip area
VCO’s contribution. Measurement results show that the SSPLL’s consumption. Fig. 1(a) shows a delay discriminator-based
closed-loop bandwidth is extended to around 6 MHz with a
FFPNS technique [13]-[14]. Through using the delay
reference of 20 MHz and the jitter is reduced by 1.34× (from 3.52
ps to 2.63 ps) with a maximum noise suppression of 6.5 dB at the
discriminator, which is composed of a phase shifter, a mixer, a
1.1-MHz offset. The phase noise suppression (PNS) path consumes bandpass filter (BPF) and a variable gain amplifier (VGA), the
0.16 mW and no delay line or calibration are needed, which results VCO’s instantaneous phase noise in a selected bandwidth is
in a relatively high FoMPNC value of 40.5 dB. extracted. Then an inverter-based delay cell is controlled by the
Index Terms—CMOS phase-locked loop, dual-path delay discriminator and conducts the phase noise cancellation.
architecture, high-pass filter, phase margin, phase noise Since the implementation of the delay discriminator is so
cancellation, ring voltage-controlled oscillator, sub-sampling complex, the power consumption and area to realize phase
phase detector. noise suppression (PNS) is significantly large. In addition,
delay time of the inverter-based delay cell limits the phase noise
I. INTRODUCTION
performance of the overall PLL. Fig. 1(b) depicts another

H
IGH-PERFORMANCE ring oscillator based phase- FFPNS technique [15] for a conventional charge-pump PLL
locked loops (PLLs) are required in various (CPPLL). By cascading a clock-skew sub-sampling delay-
applications, such as low-power system-on-chip (SoC) locked loop (SSDLL) to the CPPLL, a high-pass phase-noise
systems, digital microprocessors, data converters and specified rejection path from the output of the CPPLL to the output of the
wireless or wireline communication systems. Compared to LC SSDLL is constructed. However, a low-noise performance and
oscillator, ring oscillators [1]-[20] have the advantages like a large area occupied by the VCDL and low-pass filter (LPF)
more compact chip area, wider frequency tuning range and are required for the SSDLL. Meanwhile, although the cascade
intrinsic multi-phase output signals. However, the inferior structure relaxes the trade-off between the loop bandwidth and
jitter/phase noise performance of the ring oscillator is always the number of integrators, it folds the VCDL noise for a large
the bottleneck of the overall PLL jitter/phase noise noise multiplication factor. Fig. 1(c) shows a SSPLL utilizing a
performance. FFPNS technique [16]-[18]. In this approach, the intrinsic
In order to reduce ring oscillator’s phase noise contribution phase noise extraction function of the sub-sampling phase
to the overall PLL, several techniques like injection locked detectot (SSPD) is discovered. The output of the SSPD is fed to
clock multiplier (ILCM) [9]-[10], phase noise filter (PNF) [11]- a VCDL at the PLL output directly to perform the FFPNS
[12], feedforward phase noise suppression (FFPNS) [13-18] operation. However, to accurately cancel the phase noise of the

Manuscript received Mar 3, 2023; revised May 2, 2023; accepted May 30, Y. Dong, C. C. Boon, Z. Liu, and K. Yang are with VIRTUS, School of
2023. Date of publication xxxxxx xx, xxxx; date of current version xxxxxx xx, Electrical and Electronic Engineering, Nanyang Technological University,
xxxx. This research/project is supported by the National Research Foundation, Singapore 639798. (e-mail: [email protected];
Singapore and Infocomm Media Development Authority under its Future [email protected]; [email protected]; [email protected].)
Communications Research & Development Programme. (Corresponding Digital Objective Identifier XXXXXXXXX.
author: Chirn Chye Boon, Zhe Liu.) Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org
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REF LPF
Phase PFD CP VCO OUT1
BPF
Shifter

Mixer VGA
DIV

Voltage-Controlled Delay Line

OUT2
REF CP LPF VCO NCB OUT
PFD
Re-timer

Clock-Skew LPF
DIV CP
REF Sub-Sampling

(a) (b)

CLK1 SSPD1
SSPD

SSPD Gm + LPF VCO NCB OUT CLK2 SSCP

REF Tunable SSPD2
Delay MUX
Buffer CLK3 SSPD3
Decision
PFD CP REF
PFD CP + LPF VCO OUT
Calibration
DIV SSPD

DIV

(c) (d)
Fig. 1. State-of-the-art phase noise cancelling techniques: (a) Delay discriminator-based FFPNS technique; (b) SSDLL based
FFPNS technique; (c) Sub-sampling phase detection based FFPNS technique; (d) Frequency-shaping sub-sampling loop based
FBPNS technique.

VCO, additional calibration is needed to optimize the gain of and reduces the SSPD/SSCP noise by nature. Therefore, the
the voltage-controlled delay line in the noise cancellation block phase noise performance is mainly decided by the
(NCB). reference/reference buffer and ring VCO. The reference
To avoid complex phase noise extraction circuits and the frequency is set as 20 MHz and the output frequency is set as 2
usage of long delay line in afore-mentioned phase noise GHz in this PLL design. Usually, the phase noise of
cancelling techniques, a feedback phase noise suppression reference/reference buffer at the 100-kHz to 10-MHz offset is
(FBPNS) technique is proposed in [19] as shown in Fig. 1(d). about -150 dBc/Hz while the phase noise of the ring VCO is
It consists of a conventional type-II CPPLL and a sub-sampling around -90 dBc/Hz at the 1-MHz offset and -115 dBc/Hz at the
loop with a frequency-shaping SSPD. The SSPD directly 10-MHz offset. Then if the bandwidth of the overall PLL is set
samples the output of the PLL and converts the phase/timing at 1 MHz, the phase noise contributed by the
error to a voltage error. By comparing the voltage difference reference/reference buffer is around -110 dBc/Hz while the one
between the current period and the previous period, the error contributed by the ring VCO is around -90 dBc/Hz at the 1-
information is extracted and a current proportional to the error
MHz offset. It is obvious that the ring VCO dominates the
information is fed into the LPF by the sub-sampling charge
PLL’s in-band phase noise. A straight way to reduce the in-band
pump (SSCP). Consequently, the equivalent (1-z-1) operation is
phase noise is improving the PLL bandwidth to suppress the
formed and an additional zero is introduced into the open-loop
gain expression. The PLL bandwidth is extended and the loop ring VCO’s phase noise contribution. However, Gardener’s
stability is maintained by the introduced zero (a phase margin limit theory [28]-[30] demonstrates that the ratio between the
of 60° is ensured). The VCO’s phase noise is suppressed due to type-II PLL open-loop bandwidth and the reference frequency
the wider loop bandwidth. However, in this FBPNC technique, is theoretically limited by the phase margin. In other words, the
additional clock generation is needed for three additional phase margin should be increased to achieve a higher
SSPDs and a tunable delay is required to synchronize the bandwidth, such as 60º phase margin at an open-loop bandwidth
charge-pump based loop and the sub-sampling loop. of ¼ reference frequency [30]. Thus, a large enough phase
In order to suppress the phase noise of the ring voltage- margin should be ensured when the bandwidth is increased. On
controlled oscillator (VCO) with minimum area and power the other hand, as demonstrated in [17], for a PLL with a
consumption, this paper proposes a dual-path sub-sampling ring reference frequency at several tens MHz, the frequency band
VCO based PLL with FBPNS technique. Different from [19], from several hundred kHz to several MHz always dominates
the main structure of this design is based on the conventional the PLL’s phase noise performance. As a result, the noise
sub-sampling PLL [21]-[27], which eliminates divider noise attenuation in this frequency band is the most important for the
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ISOBUF

Output
Pulser
Ring VCO Buffer

REF SSPD SSCP1 OUT

R1
C2
HPF SSCP2 C1

Dual-Path Structure for

Ring VCO Phase Noise Suppression

Tri-state Dead Charge

PFD Zone Pump

Divider /100

Fig. 2. Architecture of the proposed dual-path sub-sampling PLL.

jitter reduction. The goal of this paper is to suppress the ring pass frequency corner and SSCPs’ transconductances, a new in-
VCO’s output phase noise from several hundred kHz to several band zero and pole are generated to enlarge the PLL bandwidth.
MHz by extending the bandwidth while maintaining a Moreover, since the frequency of the introduced zero is smaller
sufficient phase margin. than the pole, the phase margin of the PLL is compensated. As
This paper is organized as follows. Section II describes the a consequence, the phase noise of the ring VCO is suppressed
implementation and operation principle of the proposed dual- while the loop stability is still ensured.
path sub-sampling PLL (SSPLL) and compares it with the The circuit implementation of core blocks for FBPNC is
conventional SSPLL. Section III analyzes the noise depicted in Fig. 3(a) and the transient waveforms of critical
contributions of the critical blocks in the proposed SSPLL. signals in the locking process are shown in Fig. 3(b). The SSPD
Measurement results are shown in Section V. Finally, samples the ring VCO’s output at 2 GHz with a reference
conclusions are drawn in Section VI. frequency of 20 MHz. Then the sampled output voltage is
converted to an output current by the SSCP1 in path I. In path
II. IMPLEMENTATION AND OPERATION PRINCIPLE OF THE II, the sampled output is firstly high pass filtered. Next, the
PROPOSED DUAL-PATH SUB-SAMPLING PLL filtered signal is also converted to a current signal and flows
The architecture of the proposed dual-path SSPLL is shown into the LPF. In the SSPD and HPF design, CS is 100 fF, CH is
in Fig. 2. It consists of a frequency-locked loop (FLL) and a 3 pF and RH is 50 kΩ. When the SSPD is operating in the
sub-sampling loop (SSL). Similar to [21], the FLL is composed sampling process, the equivalent load to the isolation buffer
of a divider, a three-state phase-frequency detector (PFD) and a (ISOBUF) is CS in parallel to the CH and RH. By properly setting
charge pump (CP). When the frequency of the ring VCO is the driving current of the ISOBUF, the amplitude of the signals
largely deviated from N×Fref, FLL starts to operate and tune the on CS is kept at about 0.5 Vpp. When the SSPD is at the hold
VCO frequency close to the N×Fref. Then the FLL is disabled status, the charge on CS is shared by CH and RH with a time-
and the SSL begins to work and accurately locks the ring constant of RH(CS//CH), which is around 5 ns. Since the pulse
VCO’s output to N×Fref. Compared to the conventional SSPLL width of the SSCPs’ control signal PUL is less than 1ns and set
[21], the main difference is the dual-path structure from the at the beginning of a hold stage, the sampled signal on CS almost
output of the SSPD to the low-pass filter (LPF) in the SSL. has no attenuation when two SSCPs are enabled.
As for the conventional structure, there is only one SSCP According to the dual-path structure, the transfer function of
existing between the SSPD and the LPF, which converts the SSPD and SSCPs becomes
output voltage signal of the SSPD to a current signal and injects HPD&CP (s) ≌ 2AISOBUF ×
into the LPF. In contrast, for the proposed dual-path SSPL, one
path from the SSPD to the LPF is through SSCP1, the other path R H CH s τPUL
(g m,SSCP1 + × g m,SSCP2 ) × (1)
is composed of the high-pass filter (HPF) and SSCP2. These 1 + R H CH s TREF
two paths are operating simultaneously to control the current where AISOBUF is the amplitude of the ISOBUF output signals,
injecting to the LPF. Through properly setting the HPF’s high-
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Path I

M15
M5 M4 M11
REF PUL M16 M17 PUL
CS CDUM VCTRL
IN+
ISOBUF M2 M3
OUT IN- PUL M18 M19 PUL R1
C2
CS M1 M12 M20 C1
SSPD SSCP1
IREF
VB1 LPF

M27

M21
VCM M13
M10 M9
PUL M22 M23 PUL
CH RH CDUM
IN+
M7 M8
IN- PUL M24 M25 PUL
CH
RH M6 M14 M26
HPF VCM
SSCP2

Path II

(a)

VCTRL

SSCP1_IN+
SSCP1_IN-

SSCP2_IN+
SSCP2_IN-

PUL

REF

(b)

Fig. 3. Core blocks: (a) Circuit implementation; (b) Waveforms of critical signals in the locking process.

gm,SSCP1, gm,SSCP2 is the transconductance of SSCP1, SSCP2, Furthermore, the overall open-loop gain for the SSPLL can
τPUL is the pulse width of the signal PUL, and fREF is the be expressed as
reference frequency. As a result, a new zero is generated at the K VCO
HOPEN−LOOP (s) = HPD&CP (s) ∗ HLPF (s) ∗ (4)
frequency of s
1+sR1 C1
g m,SSCP1 where HLPF (s) is . Meanwhile, R1 is 8 kΩ, C1 is 50
s(C1 +C2 +sR1 C1 )
fZF = . (2)
2π(g m,SSCP1 + g m,SSCP2 )R H CH pF and C2 is 3.3 pF in the LPF design.
According to the expression (4), Fig. 4 illustrates the
And a new pole is generated at another frequency of
conceptual open-loop characteristics of the proposed and
1 conventional type-II SSPLL. For the conventional type-II
fPF = . (3)
2πR H CH SSPLL, the slope of the open-loop gain is changed from -40
1
Obviously, the zero frequency is smaller than the pole dB/dec to -20 dB/dec at the zero fZ1 = (0.4 MHz in this
2πR1 C1
frequency, and the ratio of them is decided by two SSCPs’ design), and then from -20 dB/dec to -40 dB/dec at the pole
transconductances. C +C
fP1 = 1 2 (6.4 MHz in this design). The open-loop gain of
2πR1 C1 C2
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|HOPEN-LOOP(s)| |HOPEN-LOOP(s)|
SSPLL w/o PNS SSPLL w/i PNS
-40dB/dec
-40dB/dec -20dB/dec
-20dB/dec
-20dB/dec

fZ1 fPF
fZ1
Frequency fZF Frequency
fP1 fP1 -40dB/dec
-40dB/dec

0dB/dec

(a) (b)

Fig. 4. Conceptual open-loop gain: (a) Conventional SSPLL; (b) Proposed dual-path SSPLL.

80
-100
[email protected] ≈ 60o
Open-loop Gain (dB)

60

Open-Loop Phase (o)

40
-120

20 UBW = 4.2MHz

0 -140
[email protected] ≈ 60o
-20 UBW = 2.2MHz
-160
-40
SSPLL w/o PNS SSPLL w/o PNS
SSPLL w/i PNS SSPLL w/i PNS
-60
-180
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
Frequency(Hz) Frequency(Hz)

(a) (b)
Fig. 5. Simulated open-loop characteristics of the conventional SSPLL and proposed dual-path SSPLL: (a) Open-loop gain; (b)
Open-loop phase.

the proposed structure has different characteristics. The slope is 55º in simulation.
firstly changed from -40 dB/dec to -20 dB/dec at fZ1 and then As a result, the proposed dual-path architecture realizes the
to 0 dB/dec at the new zero fZF (0.48 MHz in this design). After goal of increasing the open-loop bandwidth without sacrificing
that, the slope begins to reduce to -20 dB/dec when it encounters the phase margin. Then, a noise analysis needs to be conducted
the additional pole fPF (1.06 MHz in this design) and finally for the critical blocks to further explore the phase noise
reduces to -40 dB/dec due to the pole fP1 . From the conceptual suppression effect.
open-loop gain, it can be seen that the open-loop bandwidth is
obviously extended and the expansion effect is decided by fZF III. NOISE ANALYSIS OF CRITICAL BLOCKS
and fPF . Since the main structure of this design is based on the
To achieve a trade-off between the bandwidth expansion and conventional SSPLL [20]-[22], the divider noise is eliminated
the phase margin compensation, gm,SSCP1 is set as 1.25 mS, and by nature. To analyze the phase noise of the overall PLL, the
gm,SSCP2 is set as 1.2 gm,SSCP1 in this design. Fig. 5 shows the phase noise contribution from each part is analyzed respectively
simulated results of the open-loop characteristics. Compared to with the phase-domain noise model as shown in Fig. 6.
the conventional transfer function, the proposed transfer
function improves the open-loop bandwidth from 2.2 MHz to A. Phase Noise Contribution of the Reference
4.2 MHz. Moreover, since the phase margin is compensated by For the phase noise contribution of the reference, it could be
the introduced zero fZF , it is kept the same with the conventional calculated based on the following transfer function as
one, which is 60° in simulation. In fact, as long as the ratio ℒin−band,REF,n 1 N × HOPEN−LOOP (s) 2
between gm,SSCP1 and gm,SSCP2 is well kept, the open-loop = ( ) (5)
SϕREF,n 2 1 + HOPEN−LOOP (s)
bandwidth will be extend to 4.1 MHz to 4.3 MHz with a 50%
variation of the fZF and fPF, and the phase margin is from 63º to
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ΦVCO,n
HPD&CP(s)

+ +
ΦREF ×N KD1 HLPF(s) KVCO/s + ΦOUT
- +

HHPF(s) KD2

Fig. 6. Phase-domain model of the proposed dual-path SSPLL.

Proposed SSPD & HPF & SSCPs

VN1 VN2
CH SSCP1
ISOBUF
OUT SSCP2 IN,SSPD&HPF
CS RH ISOBUF VN1 CH VN2
OUT
CS RH R1
C2
C1
In,RON
CH
Track mode
RON Conventional SSPD & SSCP
RON << RH CS RH In,RH

SSCP
IN,SSPD
In,RON ISOBUF VN
CH OUT
Hold mode CS R1
RON In,RH C2
CS RH C1

Fig. 7. Noise analysis of the SSPD and HPF in the proposed Fig. 8. Comparison of the SSPD and HPF’s noise in the
SSPLL. proposed SSPLL with the conventional one.

where the absolute value of HOPEN−LOOP (s) is much larger than signal (only the first and third order harmonic considered here,
the division ratio N (set as 100 in this design) within the higher order harmonic is negligible), its one-sided noise can be
bandwidth. calculated as the following expression
Since the crystal or the reference buffer can reach a phase
2kT 1 1
noise lower than -150 dBc/Hz at several MHz offset, the in- SVN1_T ≌ 4 × (2kTR ON + × R ON 2 ) × ( 2 + ). (6)
RH π 9π2
band phase noise contributed by the reference will be less than
-110 dBc/Hz through calculation. As for hold mode, the noise spectrum is composed of two
parts of noise. The first part is equivalent to sample the noise of
B. Phase Noise Contribution of the SSPD and HPF
RON with a train of impulses and convolve the result with a
The noise equivalent models of the SSPD and HPF for the square pulse. The second part is generated by RH, which will be
sampling process are shown in Fig. 7. VN1 and VN2 represents modulated by the reference signal. Therefore, the one-sided
the noise generated at the two nodes connected to the following hold mode noise can be calculated as the following expression
SSCPs, which will be further transferred to the PLL outputs.
1 RON
Similar to the analysis in [31], in order to calculate the noise SVN1_H ≌ 2 × kT × ( − )+
4CEQfREF 2
spectrum of VN1, we firstly separate it into track mode noise,
1 1
hold mode noise and related noise. For track mode noise, the 4 × 2kTR H × (0.25 + + ) (7)
π2 9π2
noise mainly comes from RH and RON (RON’s low-frequency
noise is related noise here, so it is not included in the track mode where CEQ represents the equivalent capacitance
sRH CH CS +CH +CS
noise). Since this thermal noise is modulated by the reference and its value is between Cs and CS+CH.
1+sRH CH
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In addition, when we calculate track mode and hold mode + - + - + -

noise, their related noise is not calculated in. The one-sided - + - + - +
related noise between track mode and hold mode is VCTRL
SVN1_R ≌ 4kTR ON . (8)
As a result, the total one-sided noise of the VN1 could be
obtained as below (RON is much less than RH)
SVN1 = SVN1_T + SVN1_H + SVN1_R . (9)
The noise spectrum of VN2 can also be analyzed in the same
manner. At the track mode, the noise is mainly generated by VOUT- VOUT+
VIN+ VIN-
RON and RH. However, RON and RH’s low-frequency noise are
related noise here, so it is not calculated in the track mode noise Bn Bn

and there is no higher-order RH noise because of the bandwidth 5-bit 5-bit

Cap Bank Cap Bank
limitation. Therefore, the one-sided track mode noise of VN2 is VCTRL
expressed as
1 1
SVN2_T ≌ 4 × 2kTR ON × ( 2+ ). (10) Fig. 9. Circuit implementation of the ring VCO.
π 9π2

As for the hold mode noise of VN2, the calculation of first part
is same as the VN1 and the second part is deduced by convolving ℒin−band,VN2,n , will not be higher than -130 dBc/Hz in
RH’s high order noise with the square wave, whose fundamental simulation.
frequency is the reference frequency. As a result, the one-sided In addition, for the conventional SSPD [21] and the proposed
hold mode noise can be written as SSPD and HPF, the noise current generated at the output of the
corresponding SSCPs can be calculated according to Fig. 8.
1 RON
SVN2_H ≌ 2 × kT × ( − )+ Assuming the reference frequency and the transconductances of
4CEQfREF 2
these SSCPs are the same, then the noise current generated from
1 1
4 × 2kTR H × ( 2+ ). (11) the proposed one is increased by no more than 12 dB compared
π 9π2
to the conventional one with a sampling capacitance of CS.
The one-sided related noise of VN2 is composed of RON and
RH’s thermal noise as C. Phase Noise Contribution of SSCPs
For the SSCPs, they are equivalent to a V-to-I converter. The
SVN2_R ≌ 4kT(R ON + R H ). (12)
generated current noise is decided by the transconductance of
By adding these noises with the related noise, we can obtain them. And the spectrum of the (thermal) noise current can be
the total one-sided VN2 noise expressed as
𝜏𝑃𝑈𝐿
SVN2 = SVN2_T + SVN2_H + SVN2_R . (13) 𝑆𝐼𝑆𝑆𝐶𝑃,𝑛 = 4𝑘𝑇ϒ (𝑔𝑚,𝑆𝑆𝐶𝑃1 + 𝑔𝑚,𝑆𝑆𝐶𝑃2 ). (16)
𝑇𝑅𝐸𝐹
Furthermore, according to the phase-domain model in Fig. 6, Meanwhile, the transfer function of the noise of SSCPs to the
the output phase noise due to the SSPD and HPF can be PLL output is
calculated as shown in equation (14) and (15). According to the
above deductions, SVN1 and SVN2 can be approximated to K
ℒin−band,SSCP,n 1 HLPF (s) × VCO
kT kT
= ×( s )2 . (17)
+ 3.9 kTR ON + 2.9kTR H and + 3.9 kTR ON + SISSCP,n 2 1 + HOPEN_LOOP (s)
2CEQ fref 2CEQfref
4.9kTR H , respectively. With fREF = 20 MHz, CH = 3 pF, RH =
Since there is no division ratio N existing in the transfer
50 kΩ, CS = 100 fF and RON is negligible compared to RH, then function and the pulse width for the SSCPs can be controlled to
the in-band phase noise ℒin−band,SSPD&HPF,n contributed by the a small proportion of TREF, the in-band (thermal) noise of the
SSPD and HPF, which includes ℒin−band,VN1,n and SSCPs becomes less than -135 dBc/Hz in simulation.

τ K
ℒ in−band,VN1,n 1 g m,SSCP1 × PUL × HLPF (s) × VCO 1 g m,SSCP1
TREF s 2
= ×( ) ≌ ×( )2 (14)
SVN1 2 1 + HOPENLOOP (s) 2 R H CH s
2A ISOBUF × (g m,SSCP1 + 1 + R C s × g m,SSCP2 )
H H

R H CH s τ K R H CH s
ℒ in−band,VN2,n 1 g × PUL × HLPF (s) × VCO × g m,SSCP2
1 + R H CH s m,SSCP2 TREF s 2 1 1 + R H CH s
= ×( ) ≌ ×( )2 (15)
SVN2 2 1 + HOPENLOOP (s) 2 R H CH s
2A ISOBUF × (g m,SSCP1 + × g m,SSCP2 )
1 + R H CH s
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-90

-40
Phase Noise (dBc/Hz)

Phase Noise (dBc/Hz)

-100
-60
Max ∆ = 6.5dB
-80 -110

-100
-120

Free-running ring VCO's phase noise

VCO's output phase noise w/o PNS
-120
VCO's output phase noise w/i PNS
-130
10k 100k 1M 10M 10K 100K 1M 10M
Frequency(Hz) Frequency(Hz)

(a) (b)
Fig. 10. Simulation results: (a) Simulated phase noise of free-running ring VCO; (b) Simulated phase noise contribution of ring
VCO in the conventional SSPLL and proposed SSPLL.

Fig. 11. Die photograph of the proposed dual-path SSPLL.

(a)
D. Phase Noise Contribution of the Ring VCO
Fig. 9 shows the implementation of the ring VCO used in this
SSPLL and the simulated phase noise of the free-running ring
VCO is shown in Fig. 10(a). According to the phase domain
model in Fig. 6, the phase noise transfer function of the ring
VCO can be deduced as:
ℒin−band,VCO,n 1 1
= ×( )2 . (18)
SϕVCO,n 2 1 + HOPEN−LOOP (s)
It can be observed that the phase noise contribution of the ring
VCO is in an inverse relationship to the PLL’s open-loop gain.
Due to the novel open-loop transfer function of the proposed
SSPLL, the simulated output phase noise contributed by the
ring VCO is reduced compared to the conventional SSPLL as
shown in Fig. 10(b). The ring VCO’s output phase noise is
suppressed to be less than -100 dBc/Hz from 200 kHz to 4 MHz,
and the suppression is around 6.5 dB from 1 to 2 MHz in (b)
simulation. Meanwhile, with the analysis in Section III.A, III.B
and III.C (LPF noise is negligible), it is known that the phase Fig. 12. Measured phase noise performance: (a) SSPLL with
noise performance of this SSPLL is dominated by the ring FBPNS disabled; (b) SSPLL with FBPNS enabled.
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TABLE I
PERFORMANCE COMPARISON WITH OTHER STATE-OF-THE-ART DESIGNS

JSSC’13 JSSC’17 ISSCC’16 JSSC’18 ISSCC’20

This work
[13] [11] [15] [17] [19]
Technology 90nm CMOS 65nm CMOS 65nm CMOS 65nm CMOS 40nm CMOS 28nm CMOS

Oscillator Type Ring Ring Ring Ring Ring Ring

Cancellation
FFPNC PNF FFPNC FFPNC FBPNC FBPNC
Technique
Supply Voltage 1.2 V 0.85 V 1.2 V 0.935 V 0.9 V 0.8 V

Output Freq. 5 GHz 1.2 GHz 2.1 GHz 2.36 GHz 5.25 GHz 2 GHz

Reference Freq. 10 MHz 24 MHz 67.74 MHz 49.15 MHz 21 MHz 20 MHz

Division Ratio 500 50 31 48 250 100

Power 29.64 mW 19.8 mW 3.84 mW 5.86 mW 9.01 mW 2.96 mW

Active Area 0.122 mm2 0.6 mm2 0.043 mm2 0.022 mm2 0.161 mm2 0.037 mm2
3.8 ps 1.48 ps 1.05 ps 0.63 ps 1.95 ps 2.63 ps
Integrated Jitter
10 kHz-10 MHz 100kHz-100 MHz 1 kHz-50 MHz 1 kHz-100 MHz 30 kHz-100 MHz 1kHz-100 MHz
FoM1 a -213.7 dB -223.6 dB -233.7 dB -236.3 dB -224.6 dB -226.9 dB

FoM2 b -240.7 dB -240.6 dB -248.6 dB -253.1 dB -248.6 dB -246.9 dB

PNC/PNS
4.44 mW 15.85 mW 0.96 mW 0.5 mW 4.05 mW 0.16 mW
Power
Jitter Reduction 1.37× 2.41× 3.49× 1.40× 1.6× 1.34×

FoMPNS c 26.3 dB 25.6 dB 41.0 dB 35.9 dB 28.0 dB 40.5 dB

Jitterrms 2 Power 1 Jitterrms 2 Power (Jitter Reduction)2

a FoM1 = 10log10 [( ) ( )] b FoM
2 = 10log10 [ ( ) ( )] c FoM
PNS = 10log10 [ ]
1s 1mW N 1s 1mW PNS Power (W)

Fig. 13. Comparison of measured phase noise performance. Fig. 14. Measured SSPLL output spectrum.

VCO. As a result, the reduction of the ring VCO’s output phase standard 28-nm CMOS technology for verification. It occupies
noise leads to the improvement of the overall SSPLL’s phase an active area of 0.037 mm2 and consumes 2.96 mW under a
noise performance. supply voltage of 0.8 V. The frequency characteristics are
measured with the spectrum analyzer (R&S FSUP50).
IV. MEASUREMENT RESULTS Fig. 12 and Fig. 13 shows the measured phase noise of the
As shown in Fig. 11, the proposed SSPLL is fabricated in a proposed SSPLL with the PNS path enabled and disabled. It
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shows that the proposed SSPLL can achieve a phase noise of - 5. K. Sogo, A. Toya and T. Kikkawa, "A ring-VCO-based sub-sampling PLL
CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter," in Proc.
102 dBc/Hz at the 1-MHz offset with the PNS path enabled IEEE Eur. Conf. on Solid-State Circuits (ESSCIRC), Bordeaux, France,
while the one with the PNS path disabled only reaches -95 Sep. 2012, pp. 253-256.
dBc/Hz at the 1-MHz offset. Compared to the one without 6. C. -W. Hsu, K. Tripurari, S. -A. Yu and P. R. Kinget, "A Sub-Sampling-
Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust
FBPNS, the phase noise of the proposed SSPLL is suppressed
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jitter integrated from 1 kHz to 100 MHz is improved from 3.52 Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL
With Loop Bandwidth-Tracking Technique," IEEE Trans. on Very Large
ps to 2.63 ps. Meanwhile, the closed-loop bandwidth of the Scale Integr. (VLSI) Syst., vol. 26, no. 5, pp. 933-944, May 2018.
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In addition, the measured spectrum is shown in Fig. 14, which 1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic
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Table I summarizes and compares the performance of the VCO-Based Injection-Locked Clock Multiplier With a Continuous
Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge
proposed PLL with other state-of-the-art works. Since division Phase Detector," IEEE J. of Solid-State Circuits, vol. 51, no. 8, pp. 1878-
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Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-
PLL, it is also taken into consideration in FoM2 as in [19]. Due Time PVT Calibrator With Replica-Delay Cells," IEEE J. of Solid-State
to the proposed FBPNS technique, the FoM2 value achieves - Circuits, vol. 51, no. 2, pp. 401-411, Feb. 2016.
246.9 dB. Moreover, compared to other state-of-the-art works, 11. A. Li, Y. Chao, X. Chen, L. Wu and H. C. Luong, "A Spur-and-Phase-
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the implementation in this work is simplest and does not require
Locked PLLs," IEEE J. of Solid-State Circuits, vol. 52, no. 8, pp. 2128-
any additional delay line, clock generation or calibration 2140, Aug. 2017.
circuits for the PNS path. Furthermore, the cancellation path 12. S. Hao, T. Hu and Q. J. Gu, "A CMOS Phase Noise Filter With Passive
only consumes 0.16 mW and achieves a FoMPNS of 40.5 dB. Delay Line and PD/CP-Based Frequency Discriminator," IEEE Trans. on
Microw. Theory Techn., vol. 65, no. 11, pp. 4154-4164, Nov. 2017.
13. S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, "A 90-nm CMOS 5-GHz
V. CONCLUSION Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise
Cancellation," IEEE J. of Solid-State Circuits, vol. 48, no. 5, pp. 1151-
A ring-VCO based SSPLL with FBPNC technique is 1160, May 2013.
implemented, analyzed and demonstrated in this paper. The 14. S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, "A 90nm CMOS 5GHz ring
proposed dual-path architecture improves the open-loop unit- oscillator PLL with delay-discriminator based active phase noise
cancellation," in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC),
gain bandwidth and maintains a sufficient phase margin Montreal, QC, Canada, Jul. 2012, pp. 173-176.
simultaneously. Consequently, the phase noise contribution of 15. Z. Huang, B. Jiang, L. Li and H. C. Luong, "2.3 A 4.2µs-settling-time 3rd-
the ring VCO is suppressed while the loop stability is ensured. order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified
Furthermore, the phase noise contribution of the introduced clock-skew sub-sampling DLL," in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2016, pp. 40-
PNC path is negligible in the overall PLL’s phase noise. In 41.
addition, the PNC path is area-power efficient and no delay line 16. S. S. Nagam and P. R. Kinget, "A −236.3dB FoM sub-sampling low-jitter
or calibration is required, which leads to a relatively high supply-robust ring-oscillator PLL for clocking applications with feed-
FoMPNC value. forward noise-cancellation," in Proc. IEEE Custom Integr. Circuits Conf.
(CICC), San Diego, CA, USA, May 2018, pp. 1-4.
17. S. S. Nagam and P. R. Kinget, "A Low-Jitter Ring-Oscillator Phase-Locked
ACKNOWLEDGMENT Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase
Detector," IEEE J. of Solid-State Circuits, vol. 53, no. 3, pp. 703-714, Mar.
The authors would like to thank Dr. Liang Zhipeng and Dr. 2018.
Ding Xin for their useful technical discussion, and thank Ms. 18. S. S. Nagam, Y. Fan and P. R. Kinget, "Auxiliary Feed-Forward Noise
Lim-Tan Gek Eng for her great help in chip testing. Cancellation Techniques for a Generic Type-II Ring Oscillator Phase
Locked Loop," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 5, pp.
1670-1674, May 2021.
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23. X. Gao, E. Klumperink and B. Nauta, "Sub-sampling PLL techniques," Next Generation Wireless Communication Systems (World
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Digital Sub-Sampling Architecture," IEEE J. of Solid-State Circuits, vol.
51, no. 6, pp. 1385-1397, Jun. 2016. Programme Director for RF and MM-wave research in the S$50
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Zhe Liu (S’19) received the B.S. and M.S.

Yangtao Dong (S'19) received the B.E. and
degrees from the College of Information
M.E. degrees from Zhejiang University
Science & Electronic Engineering, Zhejiang
(ZJU), Hangzhou, China, in 2015 and 2018,
University, Hangzhou, China, in 2014 and
respectively. He is currently pursuing the
2017, and the Ph.D. degree from Nanyang
Ph.D. degree at Nanyang Technological
Technological University, Singapore, in
University (NTU), Singapore. His research
2022. Her research interests include the
interests are on analog and radio-frequency
design of RF integrated circuits such as PLL,
integrated circuits and systems, including
DLL and receiver for wireless
wideband analog baseband design,
communications.
frequency synthesizers, millimeter-wave receiver front-end and
biomedical front-end circuits.

Kaituo Yang (S'15–M’19) received the B.S.

Chirn Chye Boon (M’09-SM’10) and M.S. degrees in School of Information
received B.E. (Hons.) (Elect.) in 2000 and Science and Technology from University of
Ph.D. (Elect. Eng.) in 2004 from Nanyang Science and Technology of China (USTC),
Technological University (NTU), in 2011 and 2014, and the Ph.D. degree from
Singapore. Since 2005, Chirn Chye has Nanyang Technological University,
been with NTU where he is currently an Singapore, in 2021. He is also a researcher
Associate Professor. Before that, he was in VIRTUS Laboratory, NTU, Singapore
with Advanced RFIC, where he worked as since 2014. His research interests include
a Senior Engineer. analog and RF integrated circuits and systems for wireless
He specializes in the areas of radio frequency (RF) & MM- communications, especially focusing on low NF and high
wave circuits design for Communications applications. He has linearity receiver design. He holds several patents in the field of
conceptualized, designed and silicon-verified many RF-CMOS design.
circuits/chips resulting in over 150 refereed publications and 15
patents in the fields of RF and MM-wave. He is a coauthor of
the book “Design of CMOS RF Integrated Circuits and
Systems” and “CMOS Millimeter-Wave Integrated Circuits for