Overview of

Electrostatic Recommendations in
Updated E78, E129, and ITRS 2005

Arnold Steinman M.S.E.E.

Chief Applied Technologist
MKS, Ion Systems
Leader – SEMI ESD Task Force
ESDA Certified ESD Program Manager
Ion Systems
NARTE Certified ESD Engineer
[email protected]
© MKS Instruments, Ion Systems 2006
 Outline
z Problems caused by static charge
z Static Control Basics – Grounding and Ionization
z Static control requirements – Semiconductor
Industry Standards
ΠSEMI E78 РStatic control in Production Equipment
ΠSEMI E129 РControlling Static Charge in the Factory
ΠInternational Technology Roadmap for Semiconductors
ΠANSI ESD S20.20 РStatic Control Program
z Conclusions

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 Static Charge Problems
Contamination and ESD
Static Charge
+
Static Charge +
--- ---
--

--- + +
+
--- +
--- ---

Yield Throughput
MR Heads
Disk Media Wafers Equipment
FPD Screens
Reticles
Integrated
Circuits

Contamination ESD Damage Process Interruptions

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 Contamination Study
200 mm wafer in a Class 1 Mini-Environment

Wafer at 0 V Wafer at 2000 V

class 1 mini environment for 6 class 1 mini environment for 6 weeks
weeks

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 Electrostatic Discharge (ESD)
Responsible For Many Unidentified Failures

z Quality Issues – Catastrophic ESD

failures occur at the wafer level, the
device level, the board level and the
equipment level. ESD also damages
film, medical devices, and optics.

z Reliability Issues - ESD can cause

latent defects that may develop into
failures at a future date.

z The cost of an ESD failure increases

as a device evolves from a die on a
wafer into a component within a
system.

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 Damage Caused by
Electrostatic Discharge (ESD)

1.5 μm

6
ESD Generates Radio Waves
That Affect Microprocessors
Equipment structures and control
cables make excellent antennas

z Scrambled Program
Instructions and Data
z Microprocessor Lockup
z “Software Errors”

7
 The Basics
z Static Charge Generation
– Triboelectric Charging
– Induction Charging

z Static Charge Control

– Personnel Grounding
– Worksurface Grounding
– Static Dissipative Materials

z Insulators

8
 Insulators vs. Conductors
z The generation and storage of electrostatic charge occurs
primarily on insulators and isolated conductors. These
materials are used throughout the work environment.

z Conventional grounding techniques cannot remove

charges from insulators.

z There are two passive methods for removing charges from

insulators:
1) Surface treatments to attract moisture to the
surface.
2) Relative Humidity in excess of 40%.

z The third option is to make the air more conductive by

ionizing it.
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 Neutralizing Static Charge
with Bipolar Air Ionization
Charged Air Molecules
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+ + ---
+
---
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+ + +
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+ ---
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--- + ---
--- +
+ +
+ --- +
--- ---
+ --- --- ---
+
--- --- --- --- --- --- --- --- + + + + + + + +
+ + + + + + + + Insulator - - - - - - - -

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 International Technology
Roadmap for Semiconductors
(ITRS) 2005

Factory Integration Chapter

Static Control – pg 35
download - www.sematech.org
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 Technical Requirements - Electrostatics
2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Year Technology Node
90nm 80nm 70nm 65nm 57nm 50nm 45nm 40nm 35nm 32nm 28nm 25nm 22nm 20nm 18nm 16nm 14nm

Maximum allowable electrostatic field on facility

100 V/cm 90 V/cm 80 V/cm 70 V/cm 63 V/cm 55 V/cm 50 V/cm 44 V/cm 38 V/cm 35 V/cm 31 V/cm 28 V/cm 25 V/cm 22 V/cm 20 V/cm 18 V/cm 15 V/cm
surfaces

1.0 nC 0.8 nC 0.60 nC 0.5 nC 0.40 nC 0.30 nC 0.25 nC 0.20 nC 0.15 nC 0.125 nC 0.10 nC 0.08 nC 0.06 nC 0.05 nC 0.04 nC 0.03 nC 0.025 nC
Maximum allowable static charge on devices
(100V) (80V) (60V) (50V) (40V) (30V) (25V) (20V) (15V) (12.5V) (10V) (8V) (6V) (5V) (4V) (3V) (2.5V)

Maximum allowable electrostatic field on wafer

100 V/cm 90 V/cm 80 V/cm 70 V/cm 63 V/cm 55 V/cm 50 V/cm 44 V/cm 38 V/cm 35 V/cm 31 V/cm 28 V/cm 25 V/cm 22 V/cm 20 V/cm 18 V/cm 15 V/cm
and photomask surfaces

Notes for Tables - Static Charge Limits

1. Facility surface electric field limits apply on all components of the factory, including construction
materials, furniture, people, equipment, and carriers.
2. Wafer and photomask surface electric fields measured when they are removed from their carriers.
3. Static charge on devices measured when they are removed from their carriers.
4. For measurement techniques, refer to SEMI E78 or SEMI E43.
5. Measurements in V/cm are made with an electrostatic fieldmeter at 2.5cm (one inch).
6. Measurements in nC are made using a Faraday Cup or coulombmeter.
7. Preventing ESD damage requires an understanding of individual device and process sensitivities
to ESD. These will need to be established by appropriate testing. Specific devices may require
lower limits than those contained in the table.
8. Levels in volts (V) are equivalent device voltages assuming a 10pF device capacitance.
For 2005 – 90 volts/cm and 0.8 nanocoulombs
For 2020 – 15 volts/cm and 0.024 nanocoulombs
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 SEMI E78-0706

SEMI E78-0706
Guide to Assess and Control
Electrostatic Discharge
(ESD) and Electrostatic
Attraction (ESA) for
Equipment

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 SEMI E129-0706

Guide to Assess and Control

Electrostatic Charge in a
Semiconductor
Manufacturing Facility

Why? – Static charge continues to

be a problem throughout silicon,
reticle, and device manufacturing
facilities, not just in the equipment.

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 SEMI E78 and E129
Recommended Electrostatic Limits
Year Electrostatic Discharge, Electrostatic Field,
Node nC V/cm V/inch
2000 2.5–10 200 500
180 nm
2002 2.0 150 375
130 nm
2003 1.5 125 300
100 nm
2004 1.0 100 250
90 nm (100 volts on a 10 pf device)
2006 0.6 80 200
70 nm
2007 0.5 70 175
65 nm
2009 0.3 55 140
50 nm
2010 0.25 50 125
45 nm
2013 0.125 35 88
32 nm
2015 0.08 28 70
25 nm
2018 0.04 20 50
18 nm

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 ESD Task Force
Issues for Future Discussion
z Relationship to the ITRS
– Technology Node designations
– DRAM vs. Microprocessor table values
– Random faults per mask level vs. PWP used in allowable electric field calculations
– DRAM ½ pitch vs. MPU/ASIC ½ pitch vs. MPU/ASIC Metal 1 ½ pitch
z Different charge levels for devices, wafers, and reticles (10pf for devices, 220pf
for wafers, 70-100pf for photomasks
z Scale electric field limits for particle deposition based on killer particle size. Now
they are mostly based on protecting reticles.
z E78 - Review and/or remove the “background information” in many of the
sections and include in an Appendix/Related Information section.
z E78 - Write clear instructions on the use of Table 1 in Section 12. (see 4 step
process in Comment KT-3)
z E78 - Rewrite Section 9 to include details on type(s) of tests, number and
type(s) of samples, etc. to avoid supplier/user negotiations over test
methodology
z E129 – Differentiate between requirements for areas where devices and reticles
are handled, and those areas where they are not present. In/outside FOUPs
and reticle carriers, minienvironments, equipment, etc.
z Reticle electrostatic field issues.

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 ANSI ESD S20.20
Standard for the Development
International Standard
of an Electrostatic Control
Program for the Protection of
ANSI ESD S20.20 Electrical and Electronic Parts,
Standard
For the Development of an
Assemblies and Equipment
Electrostatic Control Program (for 100 volt HBM sensitive
EOS/ESD association standard

for the Protection of Electrical

and Electronic Parts, devices)
Assemblies and Equipment

Electrical Overstress/Electrostatic Discharge Association

ESD 7900 Turin Road

Free Download
Rome, NY 13440

from ESD Association

www.esda.org
Available in Chinese and Spanish
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 S20.20 Program Requirement for
100 volt Human Body Model Devices
z Ground everything that is conductive or
static dissipative.
z Keep charged insulators and isolated
conductors 30 cm away from sensitive
product at all times
z Use ionization whenever there are
process essential insulators in the
product or process
z Establish facility audit and training
programs
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 Cost of “Discovery”
Activity Associated Cost

Problem Occurs Product Losses

Investigation of Cause Engineering Time
Analysis Costs
Product Losses
Development and Testing Engineering Time
of Trial Solutions Trial Solution Cost
Product Losses
Installation of Chosen Solution Cost
Solution Product Losses
The cost of discovery is 10-100 times the cost of the solution!
Prevent static problems – It’s too costly to solve them 19
 Semiconductor Issue
Field-Induced CDM

z Any charged object is a potential hazard

z Static fields cause ESD damage when a
conductor is grounded in the field - devices
z Changing electric fields from a discharge or
movement can cause ESD damage without
grounding - reticles
z Isolate by distance (field drops as 1/distance2)
z Neutralize the charge

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Field Induced CDM Without Grounding
Reticle Damage Caused By ESD

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New Customer Requirements
z Documented Static Control Program
z Maintain Static Levels in the whole factory less
than 100 volts
– ANSI ESD S20.20 – 100 volts HBM

– SEMI E129 – 100 volts CDM for a 10 pf IC (1 nC)

– ITRS for 2004 – 100 volts CDM for a 10 pf IC (1 nC)

z Required for New Business

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 Achieving the 100 volt
Customer Requirement
z Ground all conductors - 0 volts

z Reduce the charge on insulators and isolated

conductors with ionizers – less than 100 volts/inch

z Educate the customer – 100 volts/inch on a

Fieldmeter has nothing to do with a 100 volt device

ESD sensitivity

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 Conclusions
z Static charge issues will not go away. Solving them
becomes more important with technology change.
z A complete static control program requires grounding,
proper material selection, and ionization to control charge on
insulators. Use ANSI ESD S20.20.
z SEMI E78 and E129 address static control requirements for
the semiconductor factory of the future, synchronizing with
ITRS 2005. These documents will be harmonized and
updated every 2 years
z The discussion of the many issues concerning static charge
control in semiconductors is continuing. Please join the ESD
Task Force to be part of that discussion.
z Next meeting Tuesday October 17 1:30-4:30PM

Static control is not an option!

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