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2. P-N Junction Diode

2.1 Semiconductor Diode
In an n-type material the electron is called the majority carrier and the hole the minority
carrier. In an p-type material the holes are the majority carrier and the electrons are
minority carrier.
If the two materials are “joined” the electrons and holes in the region of the junction will
combine resulting in a lack of carriers in the region near the junction. This region of
uncovered positive and negative ions is called the depletion region due to the depletion of

ks
mobile carriers in this region.
Since the diode is two terminal devices, the application of a voltage across its terminals
leaves three possibilities: no bias VD  0 V  , forward bias VD  0 V  and reverse

bias VD  0V  . Each is a condition that will result in a response that one must clearly

understand if the device is to be applied effectively.

2.1.1 No Applied Bias VD  0 V  Depletion region

           
   
          
zi
            
    
          
           
   







   

p n

I D  0 mA I D  0 mA
 V D  0V 
no bias 
fi
Figure 2.1: p-n junction with no applied bias.
Under no bias condition, any minority carriers (holes) in the n-type material that find
themselves within the depletion region will pass directly into the p-type material. The
closer the minority carrier is to the junction, the greater the attraction for the layer of
negative ions and the less the opposition of the positive ions in the depletion region of the
n-type material. For further discussions we shall assume that all the minority carriers in

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the n-type material that find themselves in the depletion region due to their random
motion will pass directly into the p-type material. Similar discussion can be applied to the
minority carriers (electrons) of the p-type material.
The majority carriers (electrons) of the n-type material must overcome the attractive
forces of the layer of positive ions in the n-type material and the shield of negative ions in
the p-type material in order to migrate into the area beyond the depletion region of the
p-type material. Again the same type of discussion can be applied to the majority carriers
(holes) of the p-type material.

ks
In the absence of an applied bias voltage, the net flow of charge in any one direction for
a semiconductor diode is zero.
2.1.2 Reverse Bias Condition VD  0V 

I s Minority-carrier flow
I majority  0

           
         
           
     
      
           
zi
p n
Depletion region

Is Is

 
VD
Figure 2.2: Reversed biased p-n junction.
fi
If an external potential of V volts is applied across the p-n junction such that the positive
terminal is connected to the n-type material and the negative terminal is connected to the
p-type material, the number of uncovered positive ions in the depletion region of the
n-type material will increase due to the large number of “free” electrons drawn to the
positive potential of the applied voltage.

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For similar reasons, the number of uncovered negative ions will increase in the p-type
material. The net effect, therefore, is a widening of the depletion region. This widening of
the depletion region will establish too great a barrier for the majority carriers to
overcome, effectively reducing the majority carrier flow to zero.
The number of minority carriers, however, that find themselves entering the depletion
region will not change, resulting in minority-carrier flow. The current that exists under
reverse bias conditions is called the reverse saturation current and is represented by
I s or I 0 .

ks
2.1.3 Forward Bias Condition VD  0 V 
Is 
I majority  I D  I majority  I s

          
     
            

           
p n
Depletion region
zi
ID ID

 
VD
Figure 2.3: Forward biased p-n junction.

A forward-bias or “on” condition is established by applying the positive potential to the

p-type material and the negative potential to the n-type material as shown in figure 2.3.
Thus a semiconductor diode is forward-biased when the association p-type positive and
fi
n-type negative has been established.
The application of a forward-bias potential VD will “pressure” electrons in the n-type

material and holes in the p-type material to recombine with the ions near the boundary
and reduce the width of the depletion region. The resulting minority-carrier flow of
electrons from the p-type material to the n-type material (and of holes from the n-type
material to the p-type material) has not changed in magnitude (since the conduction level

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is controlled primarily by the limited number of impurities in the material), but the
reduction in the width of the depletion region has resulted in a heavy majority flow across
the junction. An electron in the n-type material now “sees” a reduced barrier at the
junction due to the reduced depletion region and a strong attraction for the positive
potential applied to the p-type material. As the applied bias increases in magnitude the
depletion region will continue to decrease in width until a flood of electrons can pass
through the junction, resulting in an exponential rise in current as shown in the forward-
bias region of the characteristics.

ks
2.1.4 Ideal Diode
Before examining the construction and characteristics of an actual device, we first
consider the ideal device, to provide a basis for comparison. The ideal diode is a two-
terminal device having the symbol and characteristics shown in figure 2.4(a) and 2.4(b),
respectively.
Ideally, a diode will conduct current in the direction defined by the arrow in the symbol
and act like an open circuit to any attempt to establish current in the opposite direction. In
essence: The characteristics of an ideal diode are those of a switch that can conduct
zi
current in only one direction. VD
 

ID
(a)

 ID
VD
 
fi
ID
 
0 VD
 VD


ID

(b)
Figure 2.4: Ideal Diode: (a) Symbol; (b) Characteristics.

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The ideal diode, therefore, is a short circuit in the region of conduction and is an open
circuit in the region of non conduction.
Short circuit
VD
 
 
ID
I D (limited by circuit)
(a)

0 VD
Open circuit
VD

ks
 
 

ID  0
(b)
Figure 2.5: (a) Conduction and (b) non-conduction states of the ideal diode as determined by
the applied bias.

2.1.5 Diode Characteristics ( V  0.7V for Si and V  0.3V for Ge)

I D m 
zi
Ge Si

VD V 
Si V  0.3V V  0.7V
fi
Ge

Figure 2.6: Comparison of Si and Ge semiconductor diodes.

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It is clear from the characteristics of figure 2.6 that to forward bias the diode minimum
voltage of V is required. This voltage V is called cut-in voltage of the diode. The closer

the upward swing is to the vertical axis, the more “ideal” the device. However, the other
characteristics of silicon as compared to germanium still make it the choice in the
majority of commercially available units.
2.1.6 Diode Equation
 VD VT 
ID  Is  e  1 where I s = reverse saturation current,

ks
 
kT
VT  is volt equivalent of temperature and   1 for Ge and   2 for Si devices.
e
Note: The reverse saturation current in a germanium diode is normally larger by a factor
of about 1000 than the reverse saturation current in a silicon diode of comparable ratings.
I s is in the range of A for a Ge diode and nA for a silicon diode at room temperature.

2.1.7 Breakdown Diodes

zi
Diodes which are designed with adequate power-dissipation capabilities to operate in the
breakdown region may be employed as voltage-reference or constant-voltage devices.
Such diodes are known as avalanche, breakdown or Zener diodes. They are used
characteristically in the manner indicated in the figure 2.7.
I
R


IZ
VZ
 RL VZ V
fi
V  I ZK


 I ZM
(a ) (b )
Figure 2.7: (a) Zener diode as voltage regulator (b) Zener charachteristics.

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The source V and resistor R are selected so that initially, the diode is operating in the
breakdown region. Here the diode voltage, which is also the voltage across the load RL, is
VZ, and the diode current is IZ. The diode will now regulate the load voltage against
variations in load current and against variations in supply V, because in the break-down
region only small changes in diode voltage produce large changes in diode current.
Moreover, as load current or supply voltage changes, the diode current will accommodate
itself to these changes to maintain a nearly constant load voltage. The diode will continue
to regulate until the circuit operation requires the diode current to fall to IZK, in the

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neighborhood of the knee of the diode volt-ampere curve. The upper limit on diode
current is determined by the power dissipation rating of the diode.

2.1.8 The Temperature Dependence of the V-I Characteristics

The volt-ampere relationship contains the temperature implicitly in the two symbols VT
and I s . If the temperature is increased at a fixed voltage, the current increases. However if

we now reduce V, then I may be brought back to its previous value. It is found that for
dV
zi
either silicon or germanium (at room temperature)  2.5 mV 0 in order to
dT C
dV
maintain a constant value of I. It should be noted that decreases with increasing T.
dT
fi

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2.2 Diode Resistances

2.2.1 DC or Static Resistance
The application of a dc voltage to a circuit containing a semiconductor diode will result
in an operating point on the characteristic curve that will not change with time. The
resistance of the diode at the operating point can be found simply by finding the
corresponding levels of VD and ID as shown in figure 2.8 and applying the following
VD
equation: RD 
ID

ks
The dc resistance levels at the knee and below will be greater than the resistance levels
obtained for the vertical rise section of the characteristics. The resistance levels in the
reverse-bias region will naturally be quite high. Since ohmmeters typically employ a
relatively constant current source, the resistance determined will be at a preset current
level (typically, a few milliamperes).
I D mA 

ID 
zi
VD
0 V D V 

Figure 2.8: Determining the dc resistance of a diode at a particular operating point.

2.2.2 AC or Dynamic Resistance
The dc resistance of a diode is independent of the shape of the characteristic in the region
fi
surrounding the point of interest. If a sinusoidal rather than dc input is applied, the
situation will change completely. The varying input will move the instantaneous
operating point up and down a region of the characteristics and thus defines a specific
change in current and voltage as shown in figure 2.9(a). With no applied varying signal,
the point of operation would be the Q-point appearing on figure determined by the
applied dc levels. The designation Q-point is derived from the word quiescent which
means “still or unvarying.”

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Diode characteristic

tangnet line

I d  Q - point
dc operation 
Q - point  I d


ks
V d
Vd
Figure 2.9: (a) Defining ac Resistance. (b) Determining the ac Resistance at a Q-point.
A straight line drawn tangent to the curve through the Q-point as shown in figure 2.9(b)
will define a particular change in voltage and current that can be used to determine the ac
or dynamic resistance for this region of the diode characteristics. An effort should be
made to keep the change in voltage and current as small as possible and equidistant to
Vd
either side of the Q-point. In equation form rd  where ∆ signifies a finite change
I d
zi
in the quantity.
For small-signal operation the dynamic resistance r is an important parameter and is
dV
defined as the reciprocal of the slope of the volt ampere characteristic r  .
dI
The dynamic resistance is not a constant, but depends upon the operating voltage.
1
For a semiconductor diode, the dynamic conductance g 
r
fi
dI I s eV /VT I  I s V  V  V
g    r  T  I  I s  e VT  1 and  1 , I  I S .
dV VT VT I   VT
26
At room temperature, for  = 1, r  , where I is in mA and r is in . For a forward
I
current of 26 mA the dynamic resistance is 1.

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2.3 Diode Capacitances

2.3.1 Space-Charge or Transition Capacitance
A reverse bias causes majority carriers to move away from the junction, thereby
uncovering more immobile charges. Hence the thickness of the space charge layer at the
junction increases with reverse voltage. The increased in uncovered charge with applied
voltage may be considered a capacitive effect. We may define an incremental capacitance
dQ
CT by: CT  where dQ is the increase in charge caused by a change dV in voltage.
dV

ks
It follows from this definition that a change in voltage dV in a time dt will result in a
dQ dV
current i  given by i  CT where CT is not a constant, but depends upon the
dt dt
magnitude of the reverse voltage.
2.3.2 Diffusion Capacitance
For a forward bias a capacitance which is much larger than the transition capacitance lies
in the injected charge stored near the junction outside the transition region. It is
convenient to introduce an incremental capacitance, defined as the rate of change of
zi
injected charge with voltage, called the diffusion or storage, capacitance CD.
Charge control description of a diode
If the bias is in the forward direction, the potential barrier at the junction is lowered and
holes from the p-side enter the n- side. Similarly electrons from the n-side move into the
p-side. This process of minority-carrier injection has been discussed earlier. The excess
hole density falls off exponentially with distance.
fi
Assume that one side of the diode, say the p material, is so heavily doped in comparison
with the n side that the current I is carried across the junction entirely by holes moving
from the p to the n side or I  I pn  0  . The excess minority charge Q will then exist only

on the n side.
Q
Now I  , where    p  mean life for holes.


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The above equation states that the diode current (which consists of holes crossing the
junction from the p to the n side) is proportional to the stored charge Q of excess minority
carriers. The factor of proportionality is the reciprocal of the decay time constant (the
mean lifetime) of the minority carriers. Thus in the steady state, the current I supplies
minority carriers at the rate at which these carriers are disappearing because of the
process of recombination.
Static Derivation of CD
Q dQ dI 

ks
Since, I  and CD   g 
 dV dV r
dI 1
where g  is the diode incremental conductance and r  is the diode incremental
dV g
resistance.
Thus I .
CD 
VT
We see that the diffusion capacitance is proportional to the current I. In the above
derivation we have assumed that the diode current I is due to holes only. If this
zi
assumption is not satisfied then above equation gives the diffusion capacitance C DP due

holes only and a similar expression can be obtained for the diffusion capacitance CDn due

to electrons. The total diffusion capacitance can then be obtained as the sum of C DP

and CDn .

Note: For a reverse bias, g is very small and CD may be neglected compared with CT.
fi
For a forward current, on the other hand, CD is usually much larger than CT.
Despite the large value of CD, the time constant rCD may not be excessive because the
1
dynamic forward resistance r  is small. Thus rC D   . Hence, the diode time constant
g
equals the mean lifetime of minority carriers, which lies in the range of nanoseconds (ns)
to hundreds of microseconds(s).

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2.4 Load Line Analysis

The applied load will normally have an important impact on the point or region of
operation of a device. If the analysis is performed in a graphical manner, a line can be
drawn on the characteristics of the device that represents the applied load. The
intersection of the load line with the characteristics will determine the point of operation
of the system. Such an analysis is, for obvious reasons, called load-line analysis.
Consider the network of figure 2.10(a) employing a diode having the characteristics of
figure 2.10(b). Note in figure 2.10(a) that the “pressure” established by the battery is to

ks
establish a current through the series circuit in the clockwise direction. The fact that this
current and the defined direction of conduction of the diode are a “match” reveals that the
diode is in the “on” state and conduction has been established. The resulting polarity
across the diode will be as shown in figure 2.10(a) and the first quadrant (VD and ID
positive) of figure 2.10 (b) will be the region of interest – the forward-bias region.

ID
I D  mA 
 
VD
zi
 
E R VR
 

VD V 
0

Figure 2.10: (a) Series diode configuration circuit; (b) Characteristics.

fi
Applying Kirchhoff’s voltage law to the series circuit of figure 2.10 (a) will result in
 E  VD  VR  0  E  VD  VR
 E  VD  I D R
The two variables of above equation (VD and ID) are the same as the diode axis variables
of figure 2.10(a). This similarity permits a plotting of the equation on the same
characteristics of figure 2.10 (b).

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The intersections of the load line on the characteristics can easily be determined if one
simply employs the fact that anywhere on the horizontal axis ID = 0A and anywhere on
the vertical axis VD = 0 V.
ID

E Characteri stics (device)

R 
 Q  point
I DQ Load line network 

ks

0 VDQ E VD

Figure 2.11: Drawing the load line and finding the point of operation.

If we set VD  0 V in equation E  VD  I D R and solve for I D , we have the magnitude of

E
I D on the vertical axis. Thus E  VD  I D R  0 V  I D R and I D  .
R VD  0V
zi
If we set I D  0 A in equation E  VD  I D R and solve for VD , we have the magnitude of

VD on the horizontal axis. Thus E  VD   0 A  R and VD  E I .

D 0 A

A straight line drawn between the two points will define the load line as depicted in
figure 2.11. Change the level of R (the load) and the intersection on the vertical axis will
change. The result will be a change in the slope of the load line and a different point of
fi
intersection between the load line and the device characteristics.
We now have a load line defined by the network and a characteristics curve defined by
the device. The point of intersection between the two is the point of operation for this
circuit. By simply drawing a line down to the horizontal axis the diode voltage VDQ can be

determined, whereas a horizontal line from the point of intersection to the vertical axis
will provide the level of I DQ . The current ID is actually the current through the entire

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series configuration of figure 2.10(a). The point of operation is usually called the
quiescent point (abbreviated “Q-point”) to reflect its “still, unmoving” qualities as
defined by a dc network.
The solution obtained at the intersection of the two curves is the same that would be
obtained by a simultaneous mathematical solution of equations E  VD  I D R

 
and I D  I s e VD / VT  1 .

2.5 Series Diode Configurations with DC Inputs

ks
In this section the approximate model is utilized to investigate a number of series diode
configurations with dc inputs. The procedure described can, in fact, be applied to
networks with any number of diodes in a variety of configurations.
For each configuration the state of each diode must first be determined. Which diodes are
“on” and which are “off”? Once determined, the appropriate equivalent can be substituted
and the remaining parameters of the network determined.
In general, a diode is in the “on” state if the current established by the applied sources is
such that its direction matches that of the arrow in the diode symbol, and VD  0.7 V for
zi
silicon and VD  0.3 V for germanium.
For each configuration, mentally replace the diodes with resistive elements and note the
resulting direction as established by the applied voltages (“pressure”). If the resulting
direction is a “match” with the arrow in the diode symbol, conduction above is, of course,
contingent on the supply having a voltage greater than the “turn-on” voltage ( V ) of each

diode.
If a diode is in the “on” state, one can either place a 0.7 V drop across the element, or the
fi
network can be redrawn with the V equivalent circuit. In time the preference will

probably simply be to include the 0.7 V drop across each “on” diode and draw a line
through each diode in the “off” or open state. Initially, however, the substitution method
will be utilized to ensure that the proper voltage and current levels are determined.

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The series circuit of figure 2.12(a) will be used to demonstrate the approach described in
the paragraphs above. The state of the diode is first determined by mentally replacing the
diode with a resistive element as shown in figure 2.12(b). The resulting direction of I is a
match with the arrow in the diode symbol and since E  V the diode is in the “on” state.

The network is then redrawn as shown in figure 2.12(c) with the appropriate equivalent
model for the forward-biased silicon diode. Note for future reference that the polarity of
VD is the same as would result if in fact the diode were a resistive element.

ks
Si  I 
 
R VR E R VR
E
 
 

 
Figure 2.12: (a) Series diode configuration. (b) Determining the state of the diode of figure (a).
 VD 
IR
ID 0 . 7V


zi
E R VR



Figure 2.12: (c) Substituting the equivalent model for the “on” diode of figure (a).

The resulting voltage and current levels are the following.

VR
fi
V D  V , V R  E  V and I D  I R  .
R
In figure 2.13(a) the diode of figure 2.12(a) has been reversed. Mentally replacing the
diode with a resistive element as shown in figure 2.13(b) will reveal that the resulting
current direction does not match the arrow in the diode symbol. The diode is in the “off”
state, resulting in the equivalent circuit of figure 2.13(c). Due to the open circuit, the
diode current is 0 A and the voltage across the resistor R is the following:

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VR  I R R  I D R  0V

Si I 
 

E R VR
E R VR

 


 

Figure 2.13: (a) Reversing the diode of (b) Determining the state of diode

ks
figure 2.12(a). of figure (a).
 VD  E 
0 . 7V IR
 ID  0 A 

E R VR



Figure 2.13(c): Substituting the equivalent model for the “off” diode of figure (a).

The fact that VR  0V will establish E volts across the open circuit as defined by
zi
Kirchhoff’s voltage law. Always keep in mind that under any circumstances–dc, ac
instantaneous values, pulses, and so on – Kirchhoff’s voltage law must be satisfied!

Example: For the series diode configuration of figure shown below, determine VD, VR,
and ID.
 VD 
Solution: Since the applied voltage establishes
fi
Si IR
a current in the clockwise direction to match the 

arrow of the symbol and the diode is in the “on” state. 8V R 2 .2 k  VR
E
VD = 0.7 V, VR = E – VD = 8 V – 0.7 V = 7.3 V  

VR 7.3V 
ID  IR    3.32 mA
R 2.2k

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Example: Repeat above example with the diode reversed.

Solution: Removing the diode, we find that the direction of I is opposite to the arrow in
the diode symbol and the diode equivalent is the open
 VD 
circuit no matter which model is employed. The result is
IR
the network of figure shown below, where ID = 0 A due ID 

to the open circuit. Since VR = IRR, VR = (0) R = 0 V. E R VR
8V 2 .2 k  
Applying Kirchhoff’s voltage law around the closed loop 

yields -E +VD + VR = 0 

ks
and VD = E – VR = E – 0 = E = 8 V
Example: For the series diode configuration of figure shown below, determine VD, VR,
and ID.
 VD 
Solution: Although the “pressure” establishes a current
ID Si
with the same direction as the arrow symbol the level of 
applied voltage is insufficient to turn the silicon diode R 1 . 2 k  VR
E 0 .5 V

“on”. The resulting voltage and current levels are therefore
the following: 
zi
ID = 0 A, VR = IRR = IDR = (0 A) 1.2 k = 0 V and VD = E = 0.5 V
Example: Determine V0 and ID for the series circuit of Si Ge IR
figure shown below.  12 V  Vo
Solution: The resulting current has the same direction ID 5 .6 k 
as the arrowheads of the symbols of both diodes, and
the network of figure shown below results because
VT VT
fi
E  12 V   0.7 V  0.3 V   1 V .Note the redrawn  1   2

0 .7 V 0 .3 V
IR 
supply of 12 V and the polarity of V0 across the 5 . 6 k  Vo
E 12 V

5.6 k resistor. The resulting voltage
V0  E  V 1  V 2  12V  0.7V  0.3V  11V

V R V0 11V
and I D  I R     1.96mA
R R 5.6k

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Example: Determine I, V1, V2 and V0 for the series dc configuration of figure shown
below.  V1 
R1
E1  V0
10V 4.7 k Si I 
R2 2 .2 k V 2


E 2  5V
Solution: The sources are drawn and the current direction indicated as shown in figure
below. Note that the “on” state is noted simply by the additional VD= 0.7 V on the figure.

ks
This eliminates the need to redraw the network and avoids any confusion that may result
from the appearance of another source.

 Vo 

4.7 k I 4.7 k 
2.2 k 2.2 k R 2 V 2 KVL Vo
E1 10 V I E1 10 V 
 
E2 5V 5V E2

The resulting current through the circuit is,
E1  E 2  VD 10V  5V  0.7V 14.3V
zi
I    2.07 mA
R1  R2 4.74k  2.2k 6.9k
and the voltages are V1 = IR1 = (2.07 mA) (4.7 k ) = 9.73 V
V2 = IR2 = (2.07 mA) (2.2 k ) = 4.55 V
Applying Kirchhoff’s voltage law to the output section in the clockwise direction will
result in
+E2 -V2 +V0 = 0 and V0 = V2 – E2 = 4.55 V – 5 V = - 0.45 V.
fi
The minus sign indicates that V0 has a polarity opposite to that appearing in figure.

2.6 Parallel and Series–Parallel Configurations

The methods applied in series configurations can be extended to the analysis of parallel
and series-parallel configurations. For each area of application, simply match the
sequential series of steps applied to series diode configurations.

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Example: Determine V0, I1, I D1 and I D2 for the parallel diode configuration as shown in
I1 0.33 k 
figure.   
R I D1 I D2

E 10 V D1 Si D2 Si Vo

   

Solution: For the applied voltage the

 VR 
I1
“pressure” of the source is to establish a 0.33 k 
  
R I D1 I D2

ks
current through each diode in the same  
E 10V 0.7V 0.7V Vo
direction as shown in figure below. Since the  
resulting current direction matches that of the    

arrow in each diode symbol and the applied voltage is greater than 0.7 V, both diodes are
in the “on” state. The voltage across parallel elements is always the same and V0 = 0.7 V.
VR E  VD 10V  0.7V
The current I1     28.18 mA
R R 0.33k
I1 28.18 mA
Assuming diodes of similar characteristics, I D1  I D2    14.09 mA
2 2
zi
Example: Determine the current I for the network shown in figure below.
Si

I R D1 E2  4 V
 
E1  20V 2.2 k  D2

Si

Solution: 0.7V
 
fi
Redrawing the network as shown in figure  VR  I I
reveals that the resulting current direction is such I R  2.2k
 
as to turn on diode D1 and turn off diode D2. The E1 20V E2 4V
 
resulting current I is then I

E1  E2  VD 20V  4V  0.7V
I   6.95 mA
R 2.2k

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2.7 Rectifiers
2.7.1 Half-Wave Rectification
This circuit will generate a waveform vo that will have an average value of particular use
in the ac-to-dc conversion process.
vi

    
Vm  

ks
0 vi R vo
T T t
2
1 cycle
 
v i  V m sin t

Figure 2.14: Half-Wave Rectification.

During the interval t  0  T the polarity of the applied voltage is such as to establish
2
“pressure” in the direction indicated and turn on the diode with the polarity appearing
zi
above the diode. Substituting the short-circuit equivalence for the ideal diode will result
in the equivalent circuit shown in figure 2.15, where it is fairly obvious that the output
signal is an exact replica of the applied signal. The two terminals defining the output
voltage are connected directly to the applied signal via the short-circuit equivalence of
the diode.
       
    vo
fi
vi R vo vi R vo  vi Vm

T t
   
2

Figure 2.15: Conduction region (0  T/2).

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For the period t  T , the polarity of input vi is shown in figure 2.16 and the
2 T
resulting polarity across the ideal diode produces an “off” state with an open circuit
equivalent. The result is the absence of a path for charge to flow and v0  0V for the

period T .
2 T
  
 

  
 vo

Vm vo  0 V
vi R vo vi R vo  0V

ks
T T t
   
2
Figure 2.16: Nonconduction region (T/2  T).
The process of removing one-half the input signal to establish a dc level is aptly called
half-wave rectification.
The input vi and the output v0 were sketched together in figure 2.17 for comparison

purposes. The output signal v0 now has a net positive area above the axis over a full
zi
Vm
period and an average value determined by Vdc   0.318Vm

vi

Vm

V dc  0 V
0 t

vo
fi
Vm

V dc  0 .318 V m

0 t
T

Figure 2.17: Half-wave rectified signal.

The process of removing one-half the input signal to establish a dc level is aptly called
half-wave rectification.

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NOTE: The effect of using a silicon diode with V  0.7V is demonstrated in figure 2.18

for the forward-bias region. The applied signal must now be at least 0.7V before the diode
can turn “on.” For levels of vi less than 0.7V the diode is still in an open-circuit state and

vo  0V . When conducting, the difference between vo and vi is a fixed level of

V  0.7V and v0  vi V . The net effect is a reduction in area above the axis, which

naturally reduces the resulting dc voltage level. For situations where Vm V equation

ks
given below can be applied to determine the average value with a relatively high level of
accuracy. Vdc  0.318(Vm  V )
vi vo
 VT 
  
Vm   Vm  VT
0.7V
VT  0.7V
R
0 T T t vi vo 0 T
T
t
2 2

  Offset due to VT
zi
Figure 2.18: Effect of V on half-wave rectified signal.
Peak Inverse Voltage (PIV) or Peak Reverse Voltage (PRV)
It is the voltage rating that must not be exceeded in the reverse-bias region. The required
PIV rating for the half-wave rectifier can be determined from figure 2.19, which displays
the reverse-biased diode with maximum applied voltage. Applying Kirchhoff’s voltage
law, it is fairly obvious that the PIV rating of the diode must equal or exceed the peak
value of the applied voltage. Therefore, PIV rating ≥ Vm
fi
 V PIV  

 
I 0

Vm Vo  IR  0R  0V
R
 


Figure 2.19: Determining the required PIV rating for the half-wave rectifier.

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2.7.2 Full Wave Rectification

(i) Bridge Network
The dc level obtained from a sinusoidal input can be improved 100% using a process
called full-wave rectification. The most familiar network for performing such function
appears in figure 2.20 with its four diodes in a bridge configuration.
vi
 
Vm  D2
D1
vi  vo 

ks
0 T T t R
2 D3
 D4


Figure 2.20: Full-wave bridge rectifier.

During period t  0  T the polarity of the input is shown in figure 2.21. The resulting
2
polarities across the ideal diodes are shown to reveal that D2 and D3 are conducting

while D1 and D4 are in the “off” state.

  
 
" off " " on"
zi
  v  
o
vi
 R 
" on"   " off "
 

Figure 2.21: FWR for the period 0 → T/2 of the input voltage vi.
The net result is the configuration of figure 2.22, with its indicated current and polarity
across R. Since the diodes are ideal the load voltage v0  vi .
vi vo
fi
Vm 
Vm
R
t vi t
0 T  vo  0 T
2 2


Figure 2.22: Conduction path for the positive region of vi .

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For the negative region of the input the conducting diodes are D1 and D4 , resulting in the

configuration of figure 2.23. The important result is that the polarity across the load
resistor R is the same as during positive half cycle. vo
vi

 Vm

 vo 
vi   t
t R 0 T T
0 T T
2
2 Vm 

ks

Figure 2.23: Conduction path for the negative region of vi .
Over one full cycle the input and output voltages will appear as shown in figure 2.24.
vi vo

Vm Vm
Vdc  0.636Vm
t t
0 T T 0 T T
2 2
zi
Figure 2.24: Input and output waveforms for a full-wave rectifier.
Since the area above the axis for one full cycle is now twice that obtained for half-wave
2Vm
system, the dc level has also been doubled and Vdc   0.636Vm .

NOTE: If silicon rather than ideal diodes are employed as shown in figure 2.25, an
application of Kirchhoff’s voltage law around the conduction path would result in
 vi  V  vo  V  0 And vo  vi  2V
fi
The peak value of the output voltage v0 is therefore V0max  Vm  2V
 vo
 V  0.7 V

R Vm  2V
vi
 vo 
 V  0.7 V

t
 T 0
T

2
Figure 2.25: Determining Vomax for silicon diodes in the bridge configuration.

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For situations where Vm  2V equation given below can be applied to determine the

average value with a relatively high level of accuracy.

Vdc  0.636(Vm  2V )

PIV
The required PIV of each diode (ideal) can be determined from figure 2.26 obtained at
the peak of the positive region of the input signal. For the indicated loop the maximum
voltage across R is Vm and the PIV rating is defined by PIV ≥ Vm

ks

PIV

 Vm 

Figure 2.26: Determining the required PIV rating for the bridge configurations.

(ii) Center-Tapped transformer

A second popular full-wave rectifier appears in figure 2.27 with only two diodes but
zi
requiring a center-tapped (CT) transformer to establish the input signals across each
D1
section of the secondary of the transformer.
vi


Vm  vi
R
vi 
0 T t CT  vo 


vi

fi
D2
Figure 2.27: Centre-tapped transformer full-wave rectifier.
During the positive portion of vi applied to the primary of the transformer, the network

will appear as shown in figure 2.28. D1 assumes the short-circuit equivalent and D2 the

open circuit equivalent as detrmined by the secondary voltages and the resulting current
directions.The output voltage v0 appears as shown in figure 2.28.

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vi vo

Vm
Vm Vm

 vo 
vi 

0 t CT 0 T t
T R
 Vm 2
2 

  

Figure 2.28: Network conditions for the positive region of vi .

During the negative portion of the input the network appears as shown in figure 2.29,

ks
reversing the roles of the diodes but maintaining the same polarity for the voltage across
the load resistor R. The net effect is the same output as that appearing in positive half
cycle with the same dc levels.
vo
vi   

 Vm
Vm
 R
vi 
CT 0 t
 vo  T T
0 T T t 
2
2 
Vm Vm
zi


Figure 2.29: Network conditions for the negative region of vi .

PIV: The network of figure 2.30 will help us determine the net PIV for each diode for
this full-wave rectifier. Inserting the maximum voltage for the secondary voltage and Vm
as established by the adjoining loop will result in
PIV = Vsecondary + VR = Vm + Vm and PIV ≥ 2Vm .
fi
 PIV 


Vm

 R
 
 Vm 

Figure 2.30: Determining the PIV level for the diodes.

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2.8 Clippers
There are a variety of diode networks called clippers that have the ability to “clip” off a
portion of the input signal without distorting the remaining part of the alternating
waveform. The half-wave rectifier is an example of the simplest form of diode clipper–
one resistor and diode. Depending on the orientation of the diode, the positive or negative
region of the input signal is “clipped” off.
2.8.1 Series Clippers (Positive and Negative)
The response of the series configuration of figure 2.31(a) to a variety of alternating

ks
waveforms is provided in figure 2.31(b). Although first introduced as a half-wave
rectifier (for sinusoidal waveforms), there are no boundaries on the type of signals that
can be applied to a clipper.


 

vi R vo

 


Figure 2.31(a): Series clipper.

zi
vi vO vi vi

V V V V

0 t t 0 t t

V V
fi
Figure 2.31(b): Input and output waveforms.

The addition of dc supply such as shown in figure 2.32 can have a pronounced effect on
the output of a clipper. Our initial discussion will be limited to ideal diodes and the effect
of V will be discussed later.

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vi
V

Vm  

vi vo
t R
0 T T
2  
 Vm

Figure 2.32: Series clipper with a dc supply.
There is no general procedure for analyzing above networks, but there are a few thoughts
to keep in mind before analyzing these circuits.

ks
1. Make a mental sketch of the response of the network based on the direction of the
diode and the applied voltage levels.
The direction of the diode suggests that the signal vi must be positive to turn it on. The dc

supply further requires that the voltage vi be greater than V volts to turn the diode on.

The negative region of the input signal is “pressuring” the diode into the “off” state,
supported further by the dc supply. In general, therefore, we can be quite sure that the
diode is an open circuit (“off” state) for the negative region of the input signal.
zi
2. Determine the applied voltage (transition voltage) that will cause change in state
for the diode.
For the ideal diode the transition between states will occur at the point on the
characteristic where vd  0V and id  0 A . Applying the condition id  0 A at vd  0 will

result in the configuration of figure 2.33, where it is recognized that the level of vi that

will cause a transition in state is: vi  V .

fi
V vd  0V
  id  0 

 

vi R v o  i R R  i d R  (0 ) R  0 V

 


Figure 2.33: Determining the transition level.

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For an input voltage greater than V volts the diode is in the short-circuit state, while for
input voltage less than V volts it is in the open-circuit or “off” state.
3. Be continually aware of the defined terminals and polarity of vo .

When the diode is in the short-circuit state such as shown in figure 2.34, the output
voltage vo can be determined by applying Kirchhoff’s voltage law in the clockwise

direction. vi  V  vo  0 and vo  vi  V .

V
  

ks
 

vi R vo
KVL
 

Figure 2.34: Determining vo .

4. It can be helpful to sketch the input signal above the output and determine the
output at instantaneous values of the input.
vi
zi
It is then possible that the output voltage can be Vm

sketched from the resulting data points of vo as

0 T T t
demonstrated in figure 2.35. 2
Keep in mind that at an instantaneous value of vi
the input can be treated as a dc supply of that value vo

and the corresponding dc value (the instantaneous

fi
value) of the output determined. For instance, at (Vm  V )

vi  Vm the network to be analyzed appears in

0 T T t
figure 2.36. 2
Figure 2.35: Determining levels of vo .

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For Vm  V the diode is in the short-circuit state and vo  Vm  V . At vi  V the diodes

change state and at vi  Vm , vo  0V and the complete curve for vo can be sketched as

shown in figure 2.37.

V vi vo
 

 Vm
Vm  V

vi  Vm R vo V
 0 T T t 0 T T t
2 2

ks


vi  V diodes change state

Figure 2.36: Determining vo when vi  Vm . Figure 2.37: Sketching vo .

Example: Determine the output waveform for the network shown in figure below.
vi
V  5V

20V    

vi R vo
0 T T t
2
zi
 


Solution: The diode will be in “on” state for the positive region of vi , especially when we

note the aiding effect of V= 5V. The network will then appear as shown in figure (a)
and v0  vi  5V . Substituting id  0 at v d  0 for the transition levels, we obtain the

network of figure (b) and vi  5V .

vd  0 V
fi
 
       id  0 A 
5V 5V
vi R vo vi R vo  0V

   
 

Figure (a): v0 with diode in the “on” state. Figure (b): Determining the transition level.

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For vi more negative than  5V the diode will enter its open-circuit state, while for

voltages more positive than  5V the diode is in the short-circuit state. The input and
output voltage appear in figure shown below.
vi vi

20 vi  5V  20V  5V  25V

5V vo  0V  5V  5V
 5V T T t 0 T T t
2 2 vo  5V  5V  0V

ks
Figure: Sketching v0 .

Example: Repeat above example for the square-wave input shown in figure below.
vi V  5V

   
20
vi vo
R

0 T T t  

2  10
zi
Solution: For vi  20V ( 0  T 2 ) the network of figure (a) will result. The diode is in

the short-circuit state and vo  20V  5V  25V . For vi  10V the network of figure (b)

will result, placing the diode in the “off” state and vo  i R R  0  R  0V . The resulting
output voltage appears in figure (c).
vo
fi
 
     
5V  5V 25 V

20V R vo 10V R vo  0V 0V
  0 T T t
    2

Figure (a): vo at vi  20V Figure (b): vo at vi  10V Figure(c): sketching vo

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2.8.2 Parallel Clippers (Positive and Negative)

The network of figure 2.38 is the simplest of parallel diode configurations with the output
for the same inputs. The analysis of parallel configurations is very similar to that applied
to series configurations, as demonstrated in the next example.

 R 

vi vo

 

ks

vi vo vi vo

V V

0 t 0 t 0 t 0 t
V V V V
Figure 2.38: Response to a parallel clipper.

Example: Determine v0 for the network of figure shown below.

vi

zi
 R 
16
vi vo
0 t V 4V
 
 16 

Solution: The polarity of the dc supply and the direction of the diode strongly suggest
that the diode will be in the “on” state for the negative region of the input signal. For this
fi
region the network will appear as shown in figure below where the defined terminals for
v0 require that v0  V  4V . 
 R 

vi vo  V  4V
V 4V
 


Figure: v0 for the negative region of vi.

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The transition state can be determined from figure shown

below, where the condition id  0 A at vd  0V has been v R  0V

 
imposed. The result is vi (transition)  V  4 V . id  0 vd  0 V
vi vo
Since the dc supply is obviously “pressuring” the diode to 
V 4V
stay in the short-circuit state, the input voltage must be  

greater than 4 V for the diode to be in the “off” state. Any Figure: Determining the
input voltage less than 4V will result in a short-circuited transition level.

ks
diode.
For the open-circuit state the network will appear as shown in figure below,
where v0  vi .Completing the sketch of v0 results in the waveform of figure shown below.
vi
16
v R  0V
 4 V transition level
 R  0 T t
iR  0 T
vi vo vo 2
V 4V
zi
  16
 4V
Figure: Determining v0 for the
0 T T t
open state of the diode
2
Figure: Sketching v0 .

To examine the effect of V on the output voltage, the next example will specify a silicon

diode rather than an ideal diode equivalent.

fi

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Example: Repeat above example using a silicon diode with V = 0.7 V.

Solution: The transition voltage can first be determined by applying the condition
id  0 A at v d  0.7V and obtaining the network of figure shown below. Applying

Kirchhoff’s voltage law around the output loop in the clockwise direction, we find that
R
 v i  V  V  0 
 id  0  
and vi  V  V  4  0.7  3.3V 
V 0.7 V
vi  vo
v R  id R  0  R  0V 

ks
V
 4 V 


Figure: Determining the transition level.

For input voltages greater than 3.3V, the diode will be an open circuit and v0  vi . For

input voltages of less than 3.3 V, the diode will be in the “on” state and the network of
figure shown below results, where v0  3.3V .

Note that the only effect of V was to drop the transition level to 3.3 V from 4 V.

There is no question that including the effects of V was to drop the transition level to
zi
3.3 V from 4V.

id vo

 R 
 16
0.7 V
vi  vo 3.3V
 0 T T t
4V
  
 2
fi
Figure: Determining vo for the diode Figure: Sketching v0 .
of figure 2.83 in the “on” state.

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Summary Clippers Networks

A variety of series and parallel clippers with the resulting output for the sinusoidal input
are provided in figures shown below. In particular, note the response of the last
configuration, with its ability to clip off a positive and a negative section as determined
by the magnitude of the dc supplies.

Simple Series Clippers (Ideal Diodes)

Positive:

ks
vi vo


Vm  

vi R vo 0
t ETH

Vm  
  Vm

Negative:
vi vo
zi
Vm 

 Vm

vi R vo
t t
 
Vm 
fi

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Biased Series Clippers (Ideal Diodes)

Positive:
vi vo


Vm  
V
vi R vo 0
t t
V
Vm  

 V m  V 

ks
vo
vi


Vm  
V V
vi R vo 0
t t
   V m  V 
Vm 

Negative
vi vo
zi
Vm 
  V m V 
V
vi R vo 0
t t
V
Vm  


vo
vi
fi
V m V 
Vm 
 
V V
vi R vo 0 t
t
Vm  


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Simple Parallel Clippers (Ideal Diodes)

Positive:

vi vo


Vm  R 

vi vo 0
t t
Vm   Vm


ks
Negative:

vi vo

Vm  Vm
 R 

vi vo t
t
Vm  

zi
Biased Parallel Clippers (Ideal Diodes)
vi vo

Vm  R 
V
vi vo 0
t t
 V
Vm   Vm
fi


vi
vo

Vm  R 

vi vo 0 t
t
V V
Vm  
  Vm

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Negative:

vi vo

Vm  R  Vm

vi vo 0
t t
V V
Vm  


vi

ks
vo
 Vm
Vm  R 
V
vi vo 0 t
t
 V
Vm 


Miscellaneous
zi
vi vo

 
Vm  R 
V1 V1  V 2
vi vo 0
t
t  V2
Vm  V1 V2
 

fi

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2.9 Clampers
The clamping network is one that will “clamp” a signal to a different dc level. The
network must have a capacitor, a diode, and a resistive element, but it can also employ an
independent dc supply to introduce an additional shift. The magnitude of R and C must be
chosen such that the time constant τ = RC is large enough to ensure that the voltage
across the capacitor does not discharge significantly during the interval the diode is
non-conducting. Throughout the analysis we will assume that for all practical purposes
the capacitor will fully charge or discharge in five time constants.

ks
The network of figure 2.39 will clamp the input signal to the zero level (for ideal diodes).
vi
C
 
V  

vi R vo
0 T T t
2
V  
 
Figure 2.39: Clamper.

During the interval 0→T/2 the network will appear as C

zi
  
shown in figure 2.40, with the diode in the “on” state  
V
effectively “shorting out” the effect of resistor R. The 
V R vo
resulting RC time constant is so small (R is 
determined by the inherent resistance of the network) 
 
Figure 2.40: Diode “on” and the
that the capacitor will charge to V volts very quickly. capacitor charging to V volts.
During this interval the output voltage is directly across C
fi
 
the short circuit and vo = 0 V.   
V
When the input switches to –V state, the network will 
 vo
V vo R
appear as shown in figure 2.41, with the open-circuit  
equivalent for the diode determined by the applied 


signal and stored voltage across the capacitor-both Figure 2.41: Determining vo with
the diode “off”.
“pressuring” current through the diode from cathode to
anode.

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Now that R is back in the network the time constant determined by the RC product is
sufficiently large to establish a discharge period 5τ much greater than the period T/2→T
and it can be assumed on an approximate basis that the capacitor holds onto all its charge
and therefore voltage (since V = Q/C) during this period. vi
Applying Kirchhoff’s voltage law around the input loop will
result in V

+ V+ V+ vo = 0 and vo = – 2V.
0 T T t
The negative sign resulting from the fact that the polarity of 2

ks
V
2V is opposite to the polarity defined for vo. The resulting vo
output waveform appears in figure 2.42 with the input signal.
0 T T t
The output signal is clamped to 0 V for the interval 0 to T/2
2
but maintains the same total swing (2V) as the input.
 2V
For a clamping network:
The total swing of the output is equal to the total swing of the
Figure 2.42: Sketching vo.
input signal.
This fact is an excellent checking tool for the result obtained.
zi
In general, the following steps may be helpful when analyzing clamping networks:
1. Start the analysis of clamping networks by considering that part of the input signal that
will forward bias the diode.
2. During the period that the diode is in the “on” state, assume that the capacitor will
charge up instantaneously to a voltage level determined by the network.
3. Assume that during the period when the diode is in the “off” state the capacitor will
fi
hold on to its established voltage level.
4. Throughout the analysis maintain a continual awareness of the location and reference
polarity for vo to ensure that the proper levels for vo are obtained.
5. Keep in mind the general rule that the total swing of the total output must match the
swing of the input signal.

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Example: Determine vo for the network of figure (a) for the input indicated.

vi f  1000 z C  1F
10  
 

0 t1 t2 t3 t4 t vi R 100 k vo
30V
V 5V
 
 20  
T
Figure (a): Applied signal and network.

ks
Solution: Note that the frequency is 1000 Hz, resulting in a period of 1 ms and an interval
of 0.5 ms between levels. The analysis will begin with the period t1→ t2 of the input
signal since the diode is in it short-circuit state as recommended by comment 1.
For this interval the network will appear as shown in C
 
figure (b). The output is across R, but it is also    
VC
directly across the 5V battery if you follow the direct R 100 k vo
20V 
connection between the defined terminals for vo and V 5V
 
the battery terminals. The result is vo = 5V for this   
zi
interval. Figure (b): Determining vo and VC
with the diode in the “on” state.
Applying Kirchhoff’s voltage law around the input
loop will result in
+20V-VC +5V = 0 and VC = 25 V. C
 
   
The capacitor will therefore, charge up to 25V, as 25
stated in comment 2. In this case the resistor R is not 10 V R 100 k vo

V 5V
fi
shorted out by the diode but a Thevenin’s equivalent 
 
circuit of that portion of the network which includes  

the battery and the resistor will result in RTh  0  with

Figure (c): Determining vo with the
ETh = V = 5 V. diode in the “off” state.

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For the period t2 → t3 the network will appear as shown in figure (c). The open-circuit
equivalent for the diode will remove the 5V battery from having any effect on vo, and
applying Kirchhoff’s voltage law around the outside loop of the network will result in
-10 V - 25 V – vo = 0 and vo = 35 V.
The time constant of the discharging network of figure (c) is determined by the product
RC and has the magnitude: τ = RC = (100 kΩ) (0.1 μF) = 0.01 s = 10 ms

vi vo

ks
35
10

0 t1 t2 t3 t4 t 30V
30V
5
 20
0 t1 t2 t3 t4 t

Figure (d): vi and vo for the clamper.

zi
The total discharge time is therefore 5τ = 5 (10 ms) = 50 ms.
Since the interval t2 → t3 will only last for 0.5 ms, it certainly a good approximation that
the capacitor will hold its voltage during the discharge period between pulses of the input
signals. The resulting output appears in figure (d) with the input signal. Note that the
output swing of 30 V matches the input swing as noted in step 5.
fi

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Example: Repeat above example using a silicon diode with V = 0.7 V.

Solution: For the short-circuit state the network now

 
   
takes form of figure (a) and vo can be determined by VC  0.7V
Kirchhoff’s voltage law in the output section. 20 V  R vo
-5V+0.7 V+ vo = 0 5V
 
and vo = 5V – 0.7 V = 4.3 V  

Figure (a): Determining vo and VC

with the diode in the “on” state

ks
For the input section Kirchhoff’s voltage law will
result in  
   
+20V-VC –0.7V+5V = 0 24.3V
10 V R vo
and VC = 25 V – 0.7 V = 24.3 V. 
5V
For the period t2 → t3 the network will now appear as  
  
in figure (b) with the only change being the voltage
across the capacitor. Applying Kirchhoff’s voltage law Figure (b): Determining vo with the
yields diode in the open state.
zi
-10V-24.3 V+ vo = 0 and vo = 34.3 V.
The resulting output appears in figure (c) verifying the statements that the input and
output swings are the same.
vo
34.3V

30V
fi
4.3V

0 t1 t2 t3 t4 t

Figure (c): Sketching vo.

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Summary Clamping Networks

vi
  vo
V  
C
T
0 t vi R vo 0 t
V   2V
 
 2V
vi vo
 
V  
C

ks
T 2V
0 t vi R vo
V  
0 t
 
vi
vo
 
V  
C
T V1
0 t vi R vo 0 t
V1 2V
V  
 

vo
zi
vi
 
V  
C
T 2V
0 t vi R vo
V1
V 
V1 0 t
 

vi
vo
 
V  
C
fi
T 0
0 t vi R vo t
V1
V  V1

 2V


vi vo
 
V  
C
T
0 t vi R vo
2V
V V1
 
  t
 V1

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2.10 Zener Diode

The analysis of networks employing Zener diodes is quite similar to that applied to the
analysis of semiconductor diodes. First the state of the diode must be determined
followed by a substitution of the appropriate model and a determination of the other
unknown quantities of the network. The Zener model to be employed for the “on” state
and for the “off” state as defined by a voltage less than VZ but greater than 0V with the

polarity indicated as shown in figure 2.43.

ks
  
Vz Vz V
  

‘’on’’ ‘’off’’ ( VZ  V  0V )
(a)
(b)
Figure 2.43: Zener diode equivalents for the (a) “on” and (b) “off” states.
2.10 .1 Case-I Vi and RL fixed 
zi
R

The simplest of Zener diode networks appears as IZ

shown in figure 2.44. Vi VZ RL
 P
The applied dc voltage is fixed, as is the load ZM

resistor. The analysis can fundamentally be  

broken down into two steps. Figure 2.44: Basic Zener regulator.
1. Determine the state of the Zener diode by R
fi

removing it from the network and calculating
 
the voltage across the resulting open circuit. Vi V VL RL
RLVi  
Open circuit voltage V  VL  .
R  RL  

If V  VZ , the Zener is “on” and if V  VZ , the Figure 2.45: Determining the state of the
Zener diode.
Zener is “off.”

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2. Substitute the appropriate equivalent circuit and solve for the desired unknowns.
IR
R

IL
IZ
 
Vi VZ R V
L L
PZM  
 

Figure 2.46: Substituting the Zener equivalent for the “on” situation.

ks
When the Zener is “on” then VL  VZ and I R  I Z  I L  I Z  I R  I L

VL V V V
where I L  and I R  R  i L .
RL R R

Power dissipated by the Zener diode PZ  VZ I Z  PZM .

Note: If the Zener diode is in the “on” state, the voltage across the diode is not V volts.
When the system is turned on the Zener diode will turn “on” as soon as the voltage across
zi
the Zener diode is VZ volts . It will then “lock in” at this level and never reach the higher
level of V volts.
Zener diodes are most frequently used in regulator network or a reference voltage.
A simple regulator designed to maintain a fixed voltage across the load RL . For values of
applied voltage greater than required to turn the Zener diode “on,” the voltage across the
load will be maintained at VZ volts . If the Zener diode is employed as a reference voltage,
fi
it will provide a level for comparison against other voltages.

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Example: (a) For the Zener diode network of figure (a), determine VL , VR , I Z and PZ .

(b) Repeat part (a) with RL  3 k  .  VR 

R
Solution: (a) Following the suggested procedure 
IZ
the network is redrawn as shown in figure (b). 
Open circuit voltage Vi 16 V VZ  10V RL 1.2k VL
PZM  30 mW 
RLVi 1.2k  16 V 
V   8.73 V  
R  RL 1 k   1.2 k 
Figure (a)

ks
Since V  8.73 V is less than VZ  10 V the diode

is in the “off” state. Substituting the open-circuit

R IR
equivalent we will find that  IL
1k IZ
VL  V  8.73 V 

Vi 16 V V RL 1k VL
VR  Vi  VL  16 V  8.73 V  7.27 V  
I Z  0 A and PZ  VZ I Z  0 W .  

(b) Open circuit voltage

Figure (b): Determining V for the
3 k  16 V  regulator of figure (a).
zi
RLVi
V   12 V
R  RL 1 k   3 k 
 VR 
Since V  12 V is greater than VZ  10 V , the R

diode is in the “on” state and the network of 1k IZ

figure (c) will result. Vi 16 V VZ RL 3k VL
VL  VZ  10 V and VR  Vi  VL  6 V 
 
V 10V
fi
with I L  L   3.33 mA
RL 3k  Figure (c): Network of figure (a) in
the “on” state.
VR 6V
and I R    6 mA .
R 1 k

I Z  I R  I L  6 mA  3.33 mA  2.67 mA . The power dissipated, PZ  VZ I Z  26.7 mW

which is less than the specified PZM  30 mW .

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2.10.2 Case-II  fixed Vi and variable RL 

Due to the offset voltage VZ , there is a specific range of resistor values (and therefore

load current) which will ensure that the Zener is in the “on” state. Too small a load
resistance RL will result in a voltage VL across the load resistor less than VZ and the

Zener device will be in the “off” state.

To determine the minimum load resistance that will turn the Zener diode on, simply
calculate the value of RL that will result in a load voltage VL  VZ .

ks
RLVi RVZ
That is, VL  VZ  . Solving for RL we have RLmin  .
RL  R Vi  VZ

Any load resistance value greater than the RL obtained from above equation will ensure

that the Zener diode is in the “on” sate and the diode can be replaced by its VZ source

equivalent.
This condition establishes the minimum RL , but in turn specifies the maximum I L as

VL V
I Lmax   Z .
zi
RL R Lmin

Once the diode is in the “on” state, the voltage across R remains fixed at
VR  Vi  VZ

VR
and I R remains fixed at IR 
R
The Zener current I Z  I R  I L resulting in a minimum I Z when I L is a maximum and a
fi
maximum I Z when I L is a minimum value since I R is constant.

Since I Z is limited to I ZM as provided on the data sheet, it does affect the range of RL

and therefore I L . Substituting I ZM for I Z establishes the minimum I L as

I Lmin  I R  I ZM

VZ
and the maximum load resistance as R Lmax  .
I Lmin

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IR
Example: (a) For the network of figure shown 1k
 IL
determines the range of RL and I L that will result in  R IZ

V RL being maintained at 10 V. Vi  50 V VZ  10V RL

I ZM  32 m
(b) Determine the maximum voltage rating of the  
diode.
Solution:
(a) To determine the value of RL that will turn the Zener diode on, apply equation

ks
RLmin 
RVZ

1 k 10V   10 k  250 
Vi  VZ 50V  10 V 40
The voltage across the resistor R is then determined by equation
VR 40 V
VR  Vi  VZ  50 V  10 V  40 V and IR    40 mA .
R 1 k

The minimum level of I L is then determined by equation

I Lmin  I R  I ZM  40 m  32 m  8 mA

VZ 10 V
zi
with R Lmax    1.25 k .
I Lmin 8 mA

(b) Pmax  VZ I ZM  10 V  32 mA   320 mW .

2.10.3 Case-III  fixed RL and variable Vi 

For fixed values of RL , the voltage Vi must be sufficiently large to turn the Zener diode

on. The minimum turn-on voltage Vi  Vimin is determined by

fi
VL  VZ 
RLVi R  R VZ .
and Vimin  L
RL  R RL

The maximum value of Vi is limited by the maximum Zener current I ZM .

Since I ZM  I R  I L , I Rmax  I ZM  I L

Since I L is fixed at VZ / RL and I ZM is the maximum value of I Z , the maximum Vi is

defined by Vimax  V Rmax  VZ  I Rmax R  VZ .

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Example: Determine the range of values of Vi that will maintain the Zener diode in the

“on” state. IR
R
 IL
 220 IZ

VZ  20V RL 1.2k VL
Vi
I ZM  60 m 
 
Solution:
RL  R VZ 1200   220  20 V   23.67 V

ks
Vimin  
RL 1200 
VL VZ 20 V
IL     16.67 mA
RL RL 1.2 k 

I Rmax  I ZM  I L  60 m  16.67 m  76.67 mA

Vimax  I Rmax R  VZ  (76.67 mA) (0.22 k ) + 20 V =16.87 V + 20 V = 36.87 V

2.10.4 Zener as a Reference Levels

zi
Two or more reference levels can be established by placing Zener diodes in series as
shown in figure 2.47. As long as Vi is greater than the sum of V Z1 and V Z 2 , both diodes

will be in the “on” state and the three reference voltages will be available.

 20 V 

5k  
10 V (VZ1 )

fi

Vi 50V  30 V
 
20 V (VZ 2 )
 
 

Figure 2.47: Establishing three reference voltage levels.

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Two back-to-back Zener can also be used as an ac regulator as shown in figure 2.48. For
the sinusoidal signal vi the circuit will appear as shown in figure 2.49 at the

instant vi  10 V .
vi vo

 5k 

22V Z1

20V 20V
vi vo
0 t Zeners  0 20V t
 22V Z2

ks

 


Figure 2.48: 40-V peak-to-peak sinusoidal ac regulator.

I

5k 
Z1 
 20V
Vi  10V 
 0 V
Z2

zi
 

Figure 2.49: circuit operation at vi  10 V .

The region of operation for each diode is indicated in the adjoining figure. Note that Z1 is
in a low-impedance region, while the impedance of Z2 is quite large, corresponding with
the open-circuit representation. The result is that vo  vi when vi  10 V . The input and

output will continue to duplicate each other until vi reaches 20 V. Z2 will then “turn on”
fi
(as a Zener diode) while Z1 will be in a region of conduction with a resistance level
sufficiently small compared to the series 5 kΩ resistor to be considered a short circuit.
The resulting output for the full range of vi is provided in figure 2.48. Note that the

waveform is not purely sinusoidal, but its rms value is lower than that associated with a
full 22 V peak signal.

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