Attitude Stabilization of Marine Satellite Tracking Antenna Using Model Predictive Control
Attitude Stabilization of Marine Satellite Tracking Antenna Using Model Predictive Control
Attitude stabilization of Marine Satellite Tracking Antenna using Model Predictive Control
Published in:
IFAC Journal of Systems and Control
DOI:
10.1016/j.ifacsc.2021.100173
Publication date:
2021
Document version:
Accepted manuscript
Document license:
CC BY-NC-ND
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Acronyms 1. Introduction
ARM Advanced RISC Machines. 6 Marine Satellite Tracking Antenna (MSTA) is an im-
portant shipboard equipment for establishing communica-
AXI Advanced Extensible Interface. 6 tion between ships and geostationary satellites. Due to the
ship motion caused by the ocean wave, an attitude stabiliza-
DSP Digital Signal Processing. 1 tion system is necessary for MSTA to keep the antenna dish
pointed toward the geostationary satellite with high preci-
FPGA Field Programmable Gate Array. 1, 2 sion.The Ka-band MSTA is the latest generation of MSTA
and is also the one used in our research. The Root Mean
FTC Fault Tolerant Control. 1 Square (RMS) value of allowable tracking error is only 0.2 𝑑𝑒𝑔.
Moreover, the actuators in our MSTA are stepper motors,
HIL Hardware-in-the-loop. 1, 2 whose velocity changing rate cannot be higher than a cer-
tain threshold. Otherwise, step missing will occur.
HLS High Level Synthesis. 6
Many research works have been done about the attitude
stabilization system of MSTA. In Wang et al. (2011), a per-
MPC Model Predictive Control. 1, 2 manent magnet synchronous motor servo system based on
MSTA Marine Satellite Tracking Antenna. 1 Digital Signal Processing (DSP) chip and vector control is
designed. The DSP and complex programmable logic device
are the main control chips. The software and hardware are
RMS Root Mean Square. 1
designed and completed to realize the digital control of the
satellite tracking antenna. In Tseng and Teo (1998), fuzzy
SOC System On Chip. 1, 2 logic is used to cope with the uncertainty and non-linearity
⋆
This document is the results of the research project funded by the In- of the attitude control of shipboard tracking antenna. The
novation Fund Denmark. simulations demonstrated the effectiveness of the design, which
∗ Corresponding author
has been implemented on some antennas. A Fault Tolerant
[email protected] (Y. Wang)
ORCID (s): 0000-0002-9451-1746 (Y. Wang)
Control (FTC) system is proposed in Soltani et al. (2011)
to deal with certain faults from communication system mal-
function or signal blocking. The FTC system maintains the
tracking functionality by employing a proper control strat-
egy. A robust fault diagnosis system is designed to super-
vise the FTC system. The employed fault diagnosis solution
is able to estimate the faults for a class of nonlinear systems
acting under external disturbances. In Ming et al. (2005),
a method for constructing the model of MSTA is proposed cross-elevation part and the azimuth part. The attitude stabi-
and the model is established by experiments. According to lization design of each part is independent and the controller
the model, an H-infinity controller is designed and imple- design method of each part is the same. Therefore, only the
mented in the antenna system. These research works have elevation part is used to show the design process of the atti-
contributed a lot to the design of the attitude control system tude stabilization system.
of MSTA, but none of them has considered the constraints
in the system. In the attitude stabilization system of MSTA, 2.1. Diagram of the attitude stabilization system
the actuators are stepper motors, whose angular accelera- The diagram of the attitude stabilization system of the
tion has to be limited to avoid missing steps. Previously, elevation part is shown in Fig. 1.
research works focused on the design of velocity profiles to
avoid missing steps, but to the best of our knowledge, no one
has tried to apply Model Predictive Control (MPC) to solve
this problem.
Recently, there is an increasing interest in the applica-
tion of Field Programmable Gate Array (FPGA) on compu-
tational acceleration (Tu et al. (2019); Zhang et al. (2019); Figure 1: Diagram of the attitude stabilization system of the
Kosan et al. (2018); Lucia et al. (2018)). This is mainly due elevation part
to its special hardware architecture, which is completely dif-
ferent from CPU. The development of FPGA chips is very
fast in the past five years, which is mainly pushed by the In Fig. 1, the reference angle is determined by the po-
strong need from deep learning and machine vision (Rah- sition of the geostationary satellite that the MSTA needs to
man et al. (2016); Dundar et al. (2017)). A lot of research track. This reference angle can be considered as a constant
work on the application of FPGA to accelerate the calcu- value in our research. There are two closed loops in this atti-
lation of MPC can be found (Gulbudak and Santi (2016); tude stabilization system, the inner loop and the outer loop.
Darba et al. (2016); Ramrez et al. (2014); Damiano et al. The inner loop is the velocity loop, which is responsible for
(2014); Ma et al. (2014); Jerez et al. (2014)). The compre- controlling the angular velocity of the elevation part. And
hensive reviews of FPGA applications in the industrial con- the outer loop is the position loop, which is responsible for
trol system can be found in (Monmasson and Cirstea (2007); controlling the rotation angle of the elevation part. The ro-
Monmasson et al. (2011)). These researches have laid a solid tation angle and velocity can be obtained from an attitude
foundation in the application of FPGA on MPC. However, sensor. The disturbance in Fig. 1 is from the rotation move-
there are still some areas that must be improved. ments of ships caused by ocean waves.
In this paper, the MPC algorithm based on the active set The position controller is a proportional–integral con-
method is designed and implemented in FPGA for the atti- troller. In this paper, only the design of the velocity con-
tude stabilization of MSTA. The contribution of the current troller will be explained in detail. The velocity controller is
work has four aspects: (1) The MPC algorithm is applied responsible for compensating most part of the disturbance
to handle the velocity change of stepper motors in MSTA. from the ship.
(2) Half-precision floating-point data type is proposed for
MPC implementation. (3) The Hardware-in-the-loop (HIL) 2.2. State space model for MPC
simulation is achieved in a low-cost System On Chip (SOC) In the attitude stabilization system of the elevation part,
FPGA chip, which demonstrates an inexpensive method for the stepper motor is the actuator and the elevation part is the
HIL simulation. (4) Three parallel fixed-point MPC con- load. For MPC design, the model of stepper motor has to be
trollers are implemented in the low-cost SOC FPGA chip obtained first.
and are executed simultaneously. In the previous formulation of predictive model control,
The remainder of this paper is organized as follows: In finite impulse response models, step response models, and
Section 2, the attitude stabilization system of MSTA is in- transfer function models were favored. In recent years, there
troduced and the model for MPC design is presented. The is a growing popularity of designing MPC based on state-
design procedure of MPC algorithm is stated in Section 3. space models (Wang (2009)). The main theoretical results
Then, the designed MPC is implemented in FPGA in Section of MPC related to stability come from state-space models.
4 and a HIL simulation is made in Section 5 to verify the per- The state-space model can be used for both mono-variable
formance of the proposed control scheme. Lastly, Section 6 and multi-variable processes, and can even be extended to
gives the conclusion and discusses future works. nonlinear processes (Camacho and Alba (2007)). Therefore,
the state-space model is applied in the paper.
2. Introduction and modeling of control The stepper motor is used in the close-loop control sys-
tem and its angular velocity is obtained from a high-precision
system
gyroscope mounted on the elevation part. By conducting ex-
The MSTA under development is a commercial product, perimental analysis, it is found that the velocity model of the
which has three rotating parts, namely the elevation part, the stepper motor can be approximated as a second-order linear
3. MPC algorithm where the elements of 𝑌 are the predicted outputs based on
The pseudo-code of the MPC algorithm for velocity con- current state 𝑥(𝑘). Thus they are also the predicted angular
trol loop in Fig. 1, is stated in Algorithm 1. The detailed velocities of the elevation part of the MSTA. The elements of
explanation of each line is given next. It should be noted Δ𝑈 are the increment of future control trajectory that can be
that this pseudo code is written in the style of the Matlab M obtained by solving convex optimization problem with con-
language. straints. 𝑁𝑝 is the prediction horizon, and 𝑁𝑐 is the control
horizon.
The predicted output variables are, active set methods, finding the active constraints is a time-
consuming task, especially when there are many constraints.
𝑌 = 𝐹 ⋅ 𝑥(𝑘) + Φ ⋅ Δ𝑈 , (4) Here, the primal-dual method is used to find the active set.
A dual method is applied systematically to find the inactive
where constraints, which can then be removed in the solution. The
dual problem is written in (12), whose detailed derivation
[ ]𝑇 procedure can be found in Wang (2009).
𝐹 = 𝐶𝐴 𝐶𝐴2 ... 𝐶𝐴𝑁𝑝 (5)
( )
1 1
max − 𝜆𝑇 𝐻𝜆 − 𝜆𝑇 𝐾 − 𝐹𝑑𝑇 𝐸 −1 𝐹𝑑 , (12)
𝜆≥0 2 2
⎡ 𝐶𝐵 0 ... 0 ⎤ where 𝜆 is the Lagrange multiplier, also called dual variable.
⎢ 𝐶𝐴𝐵 𝐶𝐵 ... 0 ⎥ And,
Φ=⎢ ⎥ (6)
⎢ ... ⎥ 𝐻 = 𝑀 ⋅ 𝐸 −1 ⋅ 𝑀 𝑇 , (13)
⎢ ⎥
⎣ 𝐶𝐴𝑁𝑝 −1
𝐵 𝐶𝐴 𝑁𝑝 −2
𝐵 ... 𝐶𝐴 𝑁𝑝 −𝑁𝑐
𝐵 ⎦ 𝐾 = 𝛾 +𝑀 ⋅𝐸 −1
⋅ 𝐹𝑑 , (14)
By using (4), the cost function of MPC, 𝐽 , is then defined where 𝐸 = Φ𝑇 Φ + 𝑟𝑤 ⋅ 𝐼𝑁𝑐 ×𝑁𝑐 , 𝐹𝑑 = −Φ𝑇 (𝑅𝑠 − 𝐹 ⋅ 𝑥(𝑘))
as, From (12), it can be seen that the dual is also a quadratic
program problem with 𝜆 as the decision variable. Equation
𝐽 = (𝑅𝑠 − 𝑌 )𝑇 ⋅ (𝑅𝑠 − 𝑌 ) + Δ𝑈 ⋅ 𝑅̄ ⋅ Δ𝑈 , (7) (12) is equivalent to,
( )
where 𝑅𝑠 ∈ ℝ𝑁𝑝 ×1 is the vector of reference values. 𝑅̄ = 1 1
min 𝜆𝑇 𝐻𝜆 + 𝜆𝑇 𝐾 + 𝐹𝑑 𝑇 𝐸 −1 𝐹𝑑 , (15)
𝑟𝑤 ⋅ 𝐼𝑁𝑐 ×𝑁𝑐 (𝑟𝑤 ≥ 0), where 𝑟𝑤 is the tuning parameter that 𝜆≥0 2 2
determines the desired closed-loop performance, i.e., the cost
which is solved by the Hildreth’s quadratic programming
of actuation.
procedure. This procedure is based on an element-by-element
By using (7), the MPC problem is defined as,
search. Therefore, no matrix inversion is required.
𝑚𝑖𝑛 𝐽 (8) The active set method corresponds to Line 10 − 32 in
Δ𝑈 Algorithm 1.
𝑠𝑢𝑏𝑗𝑒𝑐𝑡 𝑡𝑜 ∶ 𝑥(𝑘 + 1) = 𝐴 ⋅ 𝑥(𝑘) + 𝐵 ⋅ Δ𝑢(𝑘) (9)
𝑀 ⋅ ΔU ≤ 𝛾 (10) 3.3. Explanation of algorithm 1
Before the execution of Algorithm 1, some variables have
where to be initialized. The following variables are set: 𝑁𝑐 = 40,
[ ] [ ] 𝑁𝑝 = 40, Δ𝑢𝑚𝑖𝑛 = −3 𝑑𝑒𝑔∕𝑠, Δ𝑢𝑚𝑎𝑥 = 3 𝑑𝑒𝑔∕𝑠, and
𝐼𝑁𝑐 ×𝑁𝑐 ΔUmax
𝑀= ,𝛾 = , (11) Δ𝑡 = 0.002. The methodology to obtain these parameters
−𝐼𝑁𝑐 ×𝑁𝑐 −ΔUmin is explained in Section 3.4 with details. These parameters,
together with the identified model parameters, 𝜉𝑣 = 0.022
ΔUmin = 𝐼𝑁𝑐 ×1 ⋅Δ𝑢min , ΔUmax = 𝐼𝑁𝑐 ×1 ⋅Δ𝑢max . The chang- and 𝑤𝑛 = 27.3 𝑟𝑎𝑑∕𝑠, are used to calculate 𝐹 , Φ, 𝑀, 𝛾,
ing rate of the command angular velocity of stepper motor 𝐻, by (5), (6), (11), and (13), respectively. Then, the fol-
has to be constrained in the range of [Δ𝑢𝑚𝑖𝑛 Δ𝑢𝑚𝑎𝑥 ], whose lowing parameters have to be initialized before the execu-
exact values are explained in Section 3.4. Equation (10) is tion of Algorithm 1: 𝑢 = 0, 𝑥𝑑 (0) = 0, 𝜆 = 02𝑁𝑐 ×1 , 𝜆𝑝 =
equivalent to ΔUmin ≤ ΔU ≤ ΔUmax . This inequality con- 02𝑁𝑐 ×1 , 𝐿0 = [1 0 ... 0]𝑁𝑐 ×1 , 𝑁1 = 100, 𝐸𝑐 = 0.001, where
straint arises from the stepper motor, whose angular acceler- 𝑢 is the controller output, 𝜆 is the Lagrange multipliers, 𝜆𝑝
ation has to be limited. Otherwise, the stepper motor would is the previous 𝜆, 𝐿0 is a vector that is used to select the
miss some steps. first element of Δ𝑈 , 𝑁1 is just a constant that determines
the number of cycles for finding 𝜆 that satisfies (15), 𝐸𝑐 is
3.2. Active set methods an error threshold that determines when the cyclic section
From (8) to (10), it can be seen that solving the MPC should be left. 𝑁1 and 𝐸𝑐 are specified by trial and error.
problem is actually solving quadratic programming problem After parameters setting and initialization, the main parts
with equality and inequality constraints. The active set method of Algorithm 1 are explained. There are three inputs in the
is one of the methods for solving the MPC problem and is algorithm, which are 𝑅𝑠 , 𝑥𝑑 (𝑘) and 𝑦(𝑘). 𝑅𝑠 is the refer-
employed in our case (Gu et al. (2009); Cannon et al. (2001); ence velocity of the elevation part. 𝑥𝑑 (𝑘) is the current state,
Bartlett et al. (2000); Lau et al. (2009)). The idea of active whose first element is the current angular velocity of the ele-
set methods is to define, at each step of the MPC algorithm, vation part, and whose second element is the current angular
a set of constraints. The set of constraints are termed the acceleration of the elevation part. 𝑦𝑑 (𝑘) is the model output
working set, which is to be treated as the active set (Wang in (2). 𝑥𝑑 (𝑘) and 𝑦𝑑 (𝑘) are used to get the state variable, 𝑥(𝑘)
(2009)). If the active set is found, the original optimization in (3), which can be found in Line 2. In Line 3, the MPC
problem with inequality constraints can be converted into without inequality constraints is solved and Δ𝑈 is obtained.
an optimization problem with equality constraints. In the From Line 4 to 9, the elements of Δ𝑈 are checked one by
this is the case, the active set method is applied to find the
5
active set, which is used to correct Δ𝑈 , shown in Line 31.
The whole procedure of the active set method corresponds 0
to Line 10 to 32. Line 33 is used to get the first element of
Δ𝑈 . As Δ𝑢 is the change of 𝑢, Line 34 is used to get the lat- -5
0.06
yd ( k ) rvd (k ) ra(k )
0.04
Figure 4: Calculation of angular acceleration
0.02
4. FPGA implementation three kinds of data types are explored for the execution of
the MPC algorithm. They are: (1) Single-precision floating-
The designed MPC algorithm is firstly verified in a sim-
point data type (32 bit), (2)Half-precision floating-point data
ulation environment in Matlab/Simulink. After successfully type (16 bit), (3) Fixed-point data type (customized bit). The
doing that, the next step is to implement the MPC algorithm half-precision floating-point data type is released in 2002
in the real hardware. This is a very challenging task, because
and has 1 sign bit, 5 bits exponent width, and 11 bits man-
the sampling rate is only 2𝑚𝑠 in our case. And the prediction
tissa width (10 explicitly stored).
horizon and control horizon are very large, 𝑁𝑝 = 𝑁𝑐 = 40.
The difficulties in the implementation of the MPC algo-
The FPGA chip is selected to execute MPC mainly be-
rithm in FPGA with different data types vary greatly. Among
cause of its parallel computational capacity. By using more them, the single-precision floating-point version is the eas-
FPGA resources, more parallel computation can be achieved. iest one. After implementing the algorithm in C code, the
This results in less time needed for the execution of the algo-
algorithm can be implemented in FPGA with the help of Vi-
rithm. For example, assume that there is one for loop with
vado and HLS software. The half-precision floating-point
30 iteration. And every iteration will cost 1 𝑚𝑠 and 3% of the
version can also be implemented. The works needed are:
FPGA resources. If no parallel mechanism is applied, the to- (1) Changing the data type from "float" into "half" in the
tal time and resources needed for finishing this for loop can variable definition in the HLS, (2) Modifying the function
be about 30𝑚𝑠 and 3%, respectively. By comparison, those parameters into array or pointer. Converting the MPC algo-
numbers would be 1𝑚𝑠 and 30 ⋅ 3% if a fully parallel mech-
rithm from a floating point to a fixed point is very difficult for
anism is applied. That is the feature of FPGA: The FPGA
a complicated algorithm, such as MPC, because of the lim-
resources can be used to save time.
ited tool support. Although the Vivado HLS software can
be used to reduce the needed time, it is still a challenging
4.1. Hardware setup
task. We need to find the suitable bit width for each vari-
The MPC algorithm is implemented on a Xilinx Zynq
able in our algorithm, according to the range and precision
chip, xc7z020, which is a low-cost SOC FPGA chip that in-
needed by that variable. This needs to be done carefully to
tegrates two Advanced RISC Machines (ARM) processors
avoid overflow and rounding that would seriously affect the
(Cortex-A9 with 866𝑀𝐻𝑧) and FPGA architectures into a
controller performance. By using fixed-point data type, the
single chip. Consequently, this chip provide higher integra-
benefit is the obvious reduction of the consumed resources
tion, lower power, smaller board size, and higher-bandwidth
and algorithm execution time. The fixed-point data types of
communication between the processor and FPGA. This chip
some important variables in Algorithm 1 are shown in Tab.
also include a rich set of peripherals, on-chip memory, an
1. The variables in Tab. 1 are only a small part of the vari-
FPGA-style logic array, and high-speed transceivers. Xc7z020
ables involved in Algorithm 1. In Algorithm 1, around 50
is called All Programmable SOC, whose software and hard-
variables are defined and all of them have to be converted
ware can all be programmed. Moreover, a kind of high-
into a fixed-point data type.
speed in-chip data bus, Advanced Extensible Interface (AXI),
The FPGA resource utilization in three different data types
is used to exchange data between ARM cores and FPGA,
are shown in Tab. 2, where LUT is Lookup Table, FF is Flip
whose transmission rate could be at least 800 MByte/sec.
Flops, DSP48E is a digital signal processing logic element
The MPC algorithm coded in C language was imported
included on FPGA, and BRAM_18K is a configurable mem-
into Xilinx Vivado High Level Synthesis (HLS) software.
ory module for data storage. The clock cycles and consumed
This software can convert C code into an intellectual prop-
time are also listed here. It can be clearly seen that, from the
erty block. This block is then used in Vivado software and
floating-point data type to the fixed-point data type, the con-
converted into a bitstream file together with other blocks.
sumed resources and time are all decreased.
The bitstream file is the one that can be downloaded into the
Besides different data types, there are other calculation
FPGA chip.
optimization mechanisms in FPGA, such as pipeline, unroll,
array partition, etc. These optimization mechanisms can fur-
4.2. MPC implementation in different data types
ther make the algorithm execution time shorter.
The resources in one FPGA chip are fixed and limited.
And every calculation operation would consume a certain
amount of resources. However, for the same operation, the 5. HIL simulation
resources consumed by different data types can vary greatly.
The HIL simulation is performed in this section to test
That is, the fewer bits occupied by the data type, the fewer
the proposed control scheme, especially the designed MPC.
resources consumed by the operation. The data types with
The diagram of the HIL simulation is illustrated in Fig.
fewer bits are preferred, and its limitation is whether the pre-
5.
cision and range of this data type are high enough for the
In Fig. 5, the "PI" block is the position loop controller,
algorithm.
which is actually a simple PI controller. The "MPC" block
The FPGA in the xc7z020 chip supports a broad range
is the velocity loop controller. The velocity model used in
of data types from binary (1 bit) to double precision (64 bit).
simulation is (2). The disturbance from ship dynamics is de-
This can provide great flexibility for optimizing resource us-
scribed as 𝐴⋅𝑠𝑖𝑛(𝜔⋅𝑡), where 𝐴 = 25 𝑑𝑒𝑔 and 𝜔 = 2𝜋∕6 𝑠𝑒𝑐.
age while meeting design performance targets. In this paper,
Table 1
Fixed-point data types of some variables
Word Fraction
Signed Range Precision
Length (bit) Length(bit)
𝑅𝑠 17 9 1 [-128,128) 0.0039
𝑥𝑑 16 8 1 [-128,128) 0.0039
𝑦𝑑 17 10 1 [-64,64) 9.7656e-04
Δ𝑈 16 9 1 [-64,64) 0.0020
Δ𝑢 18 13 1 [-16,16) 1.2207e-04
𝜆 16 11 0 [0,32) 4.8828e-04
𝜔 16 9 1 [-64,64) 0.0020
Table 2
FPGA Resources usage and Consumed time
Floating Point Half Floating Point Fixed Point
LUT 34624(65%) 26242(49%) 1952(3%)
FF 22901(21%) 22492(21%) 1528(1%)
DSP48E 203(92%) 54(24%) 11(5%)
BRAM_18K 88(31%) 60(21%) 24(8%)
Clock Cycles 185409 128435 86346
Consumed Time 1.85 ms 1.28ms 0.86ms
4
3
2
u(deg/s)
1
0
-1
-2
-3
-4
0 5 10 15 20 25 30 35 40 45 50
Time(s)
4
3
2
u(deg/s)
1
0
-1
-2
-3
-4
10 10.05 10.1 10.15 10.2 10.25 10.3 10.35 10.4 10.45 10.5
Time(s)
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ACKNOWLEDGMENT Rahman, A., Lee, J., Choi, K., 2016. Efficient fpga acceleration of convolu-
The authors would like to thank Innovation Fund Den- tional neural networks using logical-3d compute array, in: 2016 Design,
mark for financial support. Thanks also go to SpaceCom Automation Test in Europe Conference Exhibition (DATE), pp. 1393–
1398.
A/S for providing assistance.
Ramrez, R.O., Espinoza, J.R., Mel?n, P.E., Reyes, M.E., Espinosa, E.E.,
Silva, C., Maurelia, E., 2014. Predictive controller for a three-
phase/single-phase voltage source converter cell. IEEE Transactions on
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