DSDV MODULE-4

CONTENT
 Introduction to Verilog
 Structure of Verilog module,
 Operators,
 Data Types, Styles of Description.
 Verilog Data flow description
 Highlights of Data flow description,
 Structure of Data flow description.

Introduction to Verilog

 Verilog was introduced in 1980s and has gone through several iterations and
standardization by the Institute of Electrical and Electronic Engineers (IEEE), such as in
December 1995 when Verilog HDL became IEEE Standard 1364-1995.
 In 2001 when IEEE Std. 1364-2001 was introduced, and in 2005 when IEEE 1800-2005
was introduced.

Structure of Verilog module

 Verilog module has

 Declaration and
 Body.
 In the declaration, the name, inputs, and outputs of the module are entered.
 The body shows the relationship between the inputs and the outputs.

Verilog Program start with the key word module with module name and should end with
endmodule, which is represent the block shown bellow

module halfadder();
-------------------
------------------- halfadder
endmodule

Note:
 module name should never start with number and any special character except
Underscore( _ ).
 There should not be any space for the module name like half adder (Error Declaration)
 Semicolon(;) act as line separator.

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 Inside the round bracket total number of external inputs and outputs are declared and
these input outputs are called sensitivity list
A SUM
module halfadder(A, B, SUM, Carry);
input A, B;
output SUM, Carry;
B
halfadder Carry
endmodule

 Inside the body the actual function of the module is defined.

 Function is defined with different styles of description.
 Now we are writing the data flow description with assign statement.
 Each statement ends with semicolon.

Verilog Ports

 Verilog ports can take one of the following three modes:

 input: The port is only an input port. In any assignment statement, the port should appear
only on the right-hand side of the statement (i.e., the port is read).

 output: The port is an output port. In contrast to VHDL, the Verilog output port can
appear in either side of the assignment statement.

 inout: The port can be used as both an input and output. The inout port represents a
bidirectional bus.

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Operators

 HDL has an extensive list of operators.

 These functions can be classified as:
 Logical operators
 Relational operators.
 Arithmetic operators.
 Shift operators.

Verilog Logical Operators

 These operators perform logical operations such as AND, OR, and XOR.
 Verilog logical operators can be classified into three groups:
 Bitwise,
 Boolean logical, and
 Reduction.
Bitwise Operators
 Verilog has extensive logical operators.
 The bitwise operators operate on the corresponding bits of two operands.
 Example: Z= X & Y, where the AND operator (&) “ANDs” the corresponding bits of X
and Y and stores the result in Z.
 If X = 1011, and Y = 1010, then Z = 1010.

Bitwise Logical Operators.

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Boolean logical operators

 These operators operate on two operands, and the result is in Boolean: 0 (false) or 1
(true).

 Example, Z = X && Y

where && is the Boolean logical AND operator.

 If X = 1011 and Y = 0001, then Z = 1.

 If X = 1010 and Y = 0101, then Z = 0. shows the Boolean logica loperators.

 List of Boolean logical operators

Reduction Logical operator

 Reduction operators operate on a single operand, the result is in Boolean.

 Example : Y = &X, where & is the reduction AND operator,

 If X = 1010, then Y = (1 & 0 & 1 & 0) = 0.

The List of Reduction Logical operator

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Relational Operators

 Verilog has a set of relational operators, table shows Verilog relational operators

 Verilog relational operators also return Boolean values: false (0) or true (1).

if (A === B)

 This is a bit-by-bit comparison. A or B can include x or high impedance Z;

 the result is true (1) if all bits of A match that of B. Otherwise, the result is false (0).

For the conditional operator “?” the format is:

 Conditional-expression ? true-expression : false-expression ;

 The conditional expression is evaluated;

 if true, true-expression is executed

 If false, false-expression is executed.

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Arithmetic Operators

 Verilog, is not extensive type-oriented language.

 Example operator (+);

 The statement Y = (A + B) calculates the value of Y as the sum of A and B.

 If A = 1110 and B = 0011 then Y = A + B gives result as 10001

 If A = 1110 and B = 0011 then Y = {A, B} gives result as Y = 11100011

Shift Operators

 Verilog has the basic shift operators.

 Shift operators are unary operators; they operate on a single operand. To understand the
function of these operators.

 If A = 1110.

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Data Types

 Verilog supports several data types these includes

 Nets
 Register
 Vectors
 Integers
 Real
 Parameter and
 Arrays

Nets
 Nets are declared by the predefined word wire.
 Nets have values that change continuously by
the circuits that are driving them.
 Verilog supports four values for nets, as
shown in Table
 Examples
 wire sum;
 wire S1 = 1’b0;

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Register

 Register, in contrast to nets, stores values until they are updated.

 Register, as its name suggests, represents data-storage elements.
 Register is declared by the predefined word reg.
 Verilog supports four values for register, as shown in Table
 Example
 reg Sum_total;

Vectors

 Vectors are multiple bits. A register or a net can be declared as a vector.

 Vectors are declared by brackets [ ].
 Examples
 wire [3:0] a = 4’b1010;
 reg [7:0] total = 8’d12;

Integers and Real

 Integers are declared by the predefined word integer.

Example: integer no_bits;
 Real numbers are declared with the predefined word real.
 Examples: 2.4, 56.3, and 5e12.
real weight;

Parameter
Parameter represents a global constant. It is declared by the predefined word parameter.

Example
module compr_genr (X, Y, xgty, xlty, xeqy);
parameter N = 3;
input [N:0] X, Y;
output xgty, xlty, xeqy;
wire [N:0] sum, Yb;

Arrays
 Verilog, does not have a predefined word for array.
 Registers and integers can be written as arrays. Consider the following statements:
 parameter N = 4;
 parameter M = 3;
 reg signed [M:0] carry [0:N];

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 The above statements declare an array by the name carry.

 The array carry has five elements, and each element is four bits.
 The four bits are in two’s complement form.

Styles of Description.

 Several styles of code writing can be used to describe the system.

 Selection of the styles depends on the available information on the system.
 The following six styles we have
 data flow,
 behavioral,
 structural,
 switch level,
 mixed type, and
 mixed language.
Data flow
 Data flow describes how the system’s signals flow from the inputs to the outputs.
 The description is done by writing the Boolean function of the outputs, with assign
statement
 The data-flow statements are concurrent; their execution is controlled by events.

module halfadder(A, B, SUM, Carry);

input A, B;
output SUM, Carry;
assign sum = A ^ B;
assign Carry = A & B;

endmodule

The Boolean function Y = ab + cd

 module andorfn(a,b,c,d, y );
input a,b,c,d;
output y;
wire s1, s2;
assign s1 = a & b;
assign s2 = c & d;
assign y = s1 | s2;
endmodule

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Behavioral Description
 A behavioral description models the system as to how the outputs behave with the
inputs; usually, a flowchart is used to show this behavior.
 always is the Verilog behavioral statement.
 all Verilog statements inside always are treated as concurrent
 here any signal that is declared as an output or appears at the left-hand side of a
signal-assignment statement should be declared as a register (reg) if it appears
inside always.
module half_add (I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2;
always@(I1, I2)
begin
#10 O1 = I1 ^ I2;
#10 O2 = I1 & I2;
end
endmodule

Structural Description
 Verilog has a large number of built-in gates.
 Example: - xor X1 (sum, a, b);
 Describes a two-input XOR gate.
 The inputs are a and b, and the output is sum.
 X1 is an optional identifier for the gate; the identifier can be omitted as:
 xor (sum, a, b);

module Half_adder1(a,b,SUM,Carry);
input a, b;
output SUM,Carry;
andgate a1(Carry,a,b); // andgate is instantiated
xorgate x1(SUM,a,b); // xorgate is instantiated

endmodule

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