TPA6111A2

www.ti.com SLOS313B – DECEMBER 2000 – REVISED JUNE 2004

150-mW STEREO AUDIO POWER AMPLIFIER

FEATURES DESCRIPTION
• 150-mW Stereo Output The TPA6111A2 is a stereo audio power amplifier
• PC Power Supply Compatible packaged in either an 8-pin SOIC or an 8-pin
– Fully Specified for 3.3-V and PowerPAD™ MSOP package capable of delivering
150 mW of continuous RMS power per channel into
5-V Operation
16-Ω loads. Amplifier gain is externally configured by
– Operation to 2.5 V means of two resistors per input channel and does
• Pop Reduction Circuitry not require external compensation for settings of 0 to
• Internal Midrail Generation 20 dB.
• Thermal and Short-Circuit Protection THD+N, when driving a 16-Ω load from 5 V, is 0.03%
at 1 kHz, and less than 1% across the audio band of
• Surface-Mount Packaging
20 Hz to 20 kHz. For 32-Ω loads, the THD+N is
– PowerPAD™ MSOP reduced to less than 0.02% at 1 kHz, and is less than
– SOIC 1% across the audio band of 20 Hz to 20 kHz. For
• Pin Compatible With TPA122, LM4880, and 10-kΩ loads, the THD+N performance is 0.005% at 1
kHz, and less than 0.5% across the audio band of 20
LM4881 (SOIC)
Hz to 20 kHz.
D OR DGN PACKAGE
(TOP VIEW)

VO1 1 8 VDD
IN1− 2 7 VO2
BYPASS 3 6 IN2−
GND 4 5 SHUTDOWN

TYPICAL APPLICATION CIRCUIT

RF VDD 8
VDD
Audio C(S)
Input VDD/2
RI IN 1−
2 VO1 1
−
CI +
BYPASS C(C)
3

Audio C(BYP)
Input
RI IN 2−
6 VO2 7
−
CI +
C(C)

From Shutdown 5 SHUTDOWN Bias 4

Control Circuit Control
RF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS
PACKAGED DEVICES
MSOP
TA SMALL OUTLINE (1) MSOP (1) SYMBOLIZATION
(D) (DGN)
–40°C to 85°C TPA6111A2D TPA6111A2DGN TI AJA

(1) The D and DGN package is available in left-ended tape and reel only (e.g., TPA6111A2DR,
TPA6111A2DGNR).

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
BYPASS 3 I Tap to voltage divider for internal mid-supply bias supply. Connect to a 0.1-µF to 1-µF low ESR capacitor
for best performance.
GND 4 I GND is the ground connection.
IN1– 2 I IN1– is the inverting input for channel 1.
IN2– 6 I IN2– is the inverting input for channel 2.
SHUTDOWN 5 I Puts the device in a low quiescent current mode when held high
VDD 8 I VDD is the supply voltage terminal.
VO1 1 O VO1 is the audio output for channel 1.
VO2 7 O VO2 is the audio output for channel 2.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VDD Supply voltage 6V
VI Input voltage –0.3 V to VDD + 0.3 V
Continuous total power dissipation internally limited
TJ Operating junction temperature range –40°C to 150°C
Tstg Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW
DGN 2.14 W (1) 17.1 mW/°C 1.37 W 1.11 W

(1) See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(literature number SLMA002), for more information on the PowerPAD package. The thermal data was
measured on a PCB layout based on the information in the section entitled Texas Instruments
Recommended Board for PowerPAD on page 33 of the before-mentioned document.

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RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
VDD Supply voltage 2.5 5.5 V
TA Operating free-air temperature –40 85 °C
VIH High-level input voltage (SHUTDOWN) 60% x VDD V
VIL Low-level input voltage (SHUTDOWN) 25% x VDD V

DC ELECTRICAL CHARACTERISTICS
at VDD = 3.3 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOO Output offset voltage 10 mV
PSRR Power supply rejection ratio VDD = 3.2 V to 3.4 V 70 dB
IDD Supply current SHUTDOWN (pin 5) = 0 V 1.5 3 mA
IDD(SD) Supply current in shutdown mode SHUTDOWN (pin 5) = VDD 1 10 µA
Zi Input impedance >1 MΩ

AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 16 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 60 mW
THD+N Total harmonic distortion + noise PO = 40 mW, 20 Hz – 20 kHz 0.4%
BOM Maximum output power BW G = 20 dB, THD < 5% > 20 kHz
Phase margin Open loop 96°
Supply ripple rejection f = 1 kHz, C(BYP) = 0.47 µF 71 dB
Channel/channel output separation f = 1 kHz, PO = 40 mW 89 dB
SNR Signal-to-noise ratio PO = 50 mW, AV = 1 100 dB
Vn Noise output voltage AV = 1 11 µV(rms)

DC ELECTRICAL CHARACTERISTICS
at VDD = 5.5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOO Output offset voltage 10 mV
PSRR Power supply rejection ratio VDD = 4.9 V to 5.1 V 70 dB
IDD Supply current SHUTDOWN (pin 5) = 0 V 1.6 3.2 mA
IDD(SD) Supply current in shutdown mode SHUTDOWN (pin 5) = VDD 1 10 µA
|IIH| High-level input current (SHUTDOWN) VDD = 5.5 V, VI = VDD 1 µA
|IIL| Low-level input current (SHUTDOWN) VDD = 5.5 V, VI = 0 V 1 µA
Zi Input impedance >1 MΩ

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AC OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 6 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 150 mW
THD+N Total harmonic distortion + noise PO = 100 mW, 20 Hz – 20 kHz 0.6%
BOM Maximum output power BW G = 20 dB, THD < 5% > 20 kHz
Phase margin Open loop 96°
Supply ripple rejection ratio f = 1 kHz, C(BYP) = 0.47 µF 61 dB
Channel/channel output separation f = 1 kHz, PO = 100 mW 90 dB
SNR Signal-to-noise ratio PO = 100 mW, AV = 1 100 dB
Vn Noise output voltage AV = 1 11.7 µV(rms)

AC OPERATING CHARACTERISTICS
VDD = 3.3 V, TA = 25°C, RL = 32 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 35 mW
THD+N Total harmonic distortion + noise PO = 40 mW, 20 Hz – 20 kHz 0.4%
BOM Maximum output power BW G = 20 dB, THD < 2% > 20 kHz
Phase margin Open loop 96°
Supply ripple rejection f = 1 kHz, C(BYP) = 0.47 µF 71 dB
Channel/channel output separation f = 1 kHz, PO = 25 mW 75 dB
SNR Signal-to-noise ratio PO = 90 mW, AV = 1 100 dB
Vn Noise output voltage AV = 1 11 µV(rms)

AC OPERATING CHARACTERISTICS
VDD = 5 V, TA = 25°C, RL = 32 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power (each channel) THD ≤ 0.1%, f = 1 kHz 90 mW
THD+N Total harmonic distortion + noise PO = 20 mW, 20 Hz – 20 kHz 2%
BOM Maximum output power BW G = 20 dB, THD < 2% > 20 kHz
Phase margin Open loop 97°
Supply ripple rejection f = 1 kHz, C(BYP) = 0.47 µF 61 dB
Channel/channel output separation f = 1 kHz, PO = 65 mW 98 dB
SNR Signal-to-noise ratio PO = 90 mW, AV = 1 104 dB
Vn Noise output voltage AV = 1 11.7 µV(rms)

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TYPICAL CHARACTERISTICS

Table of Graphs
FIGURE
vs Frequency 1, 3, 5, 6, 7, 9, 11, 13,
THD+N Total harmonic distortion plus noise
vs Output power 2, 4, 8, 10, 12, 14
Supply ripple rejection ratio vs Frequency 15, 16
Vn Output noise voltage vs Frequency 17, 18
Crosstalk vs Frequency 19–24
Shutdown attenuation vs Frequency 25, 26
Open-loop gain and phase margin vs Frequency 27, 28
Output power vs Load resistance 29, 30
IDD Supply current vs Supply voltage 31
SNR Signal-to-noise ratio vs Voltage gain 32
Power dissipation/amplifier vs Load power 33, 34

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
VDD = 3.3 V,
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %

VDD = 3.3 V,
PO = 25 mW,
CB = 1 µF, RL = 32 Ω,
AV = −1 V/V,
RL = 32 Ω,
AV = −1 V/V CB = 1 µF
1 1
20 kHz 20 Hz

0.1 0.1
1 kHz

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 10 50 100
f − Frequency − Hz PO − Output Power − mW

Figure 1. Figure 2.

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TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
VDD = 5 V,

THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

VDD = 5 V,
PO = 60 mW,
CB = 1 µF, RL = 32 Ω,
AV = −1 V/V,
RL = 32 Ω, 20 Hz
AV = −5 V/V CB = 1 µF
1 1
AV = −1 V/V

20 kHz
AV = −10 V/V
0.1 0.1
0.05 1 kHz

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 10 100 500
f − Frequency − Hz PO − Output Power − mW

Figure 3. Figure 4.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY FREQUENCY
10 10
THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

VDD = 3.3 V, VDD = 5 V,

PO = 100 mW, PO = 100 mW,
CB = 1 µF, CB = 1 µF,
RL = 10 kΩ, RL = 10 kΩ
1 AV = −1 V/V 1
AV = −5 V/V
AV = −1 V/V

0.1 0.1 AV = −10 V/V

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 5. Figure 6.

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TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
VDD = 3.3 V,

THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

VDD = 3.3 V,
PO = 60 mW, RL = 8 Ω,
CB = 1 µF, AV = −1 V/V,
RL = 8 Ω, CB = 1 µF
1 1
AV = −1 V/V
20 Hz

20 kHz
0.1 0.1

1 kHz

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 10 100 500
f − Frequency − Hz PO − Output Power − mW

Figure 7. Figure 8.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %

VDD = 5 V, VDD = 5 V,
PO = 150 mW, RL = 8 Ω,
CB = 1 µF, AV = −1 V/V, 1 kHz
RL = 8 kΩ CB = 1 µF
1 AV = −5 V/V 1 20 kHz
AV = −1 V/V

0.1 0.1

AV = −10 V/V 0.01

0.01 20 Hz

0.001 0.001
20 100 1k 10k 20k 10 100 500
f − Frequency − Hz PO − Output Power − mW

Figure 9. Figure 10.

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TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
VDD = 3.3 V,

THD+N − Total Harmonic Distortion + Noise − %

THD+N − Total Harmonic Distortion + Noise − %

VDD = 3.3 V,
PO = 40 mW, RL =16 Ω,
CB = 1 µF, AV = −1 V/V,
RL = 16 Ω, CB = 1 µF
1 1
AV = −1 V/V 20 Hz
20 kHz

0.1 0.1 1 kHz

0.01 0.01

0.001 0.001
20 100 1k 10k 20k 10 100 500
f − Frequency − Hz PO − Output Power − mW

Figure 11. Figure 12.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %

VDD = 5 V, VDD = 5 V,
PO = 100 mW, RL = 16 Ω,
CB = 1 µF, AV = −1 V/V,
RL = 16 Ω CB = 1 µF 20 Hz
1 AV = −5 V/V 1
AV = −1 V/V 20 kHz

1 kHz
0.1 0.1

AV = −10 V/V
0.01 0.01

0.001 0.001
20 100 1k 10k 20k 10 100 500
f − Frequency − Hz PO − Output Power − mW

Figure 13. Figure 14.

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SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO

vs vs
FREQUENCY FREQUENCY
0 0
0.1 µF VDD = 3.3 V, 0.1 µF VDD = 5 V,

K SVR − Supply Ripple Rejection Ratio − dB

K SVR − Supply Ripple Rejection Ratio − dB

−10 RL = 16 Ω, −10 RL = 16 Ω,
−20 0.47 µF AV = −1 V/V −20 0.47 µF AV = −1 V/V

1 µF 1 µF
−30 −30
−40 −40
−50 −50
−60 −60
−70 −70
−80 −80 Bypass = 2.5 V
−90 Bypass = 1.65 V −90
−100 −100
−110 −110
−120 −120
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 15. Figure 16.

OUTPUT NOISE VOLTAGE OUTPUT NOISE VOLTAGE

vs vs
FREQUENCY FREQUENCY
100 100
VDD = 3.3 V,
BW = 10 Hz to 22 kHz
V n − Output Noise Voltage − µ V(RMS)

AV = −10 V/V
V n − Output Noise Voltage − µ V(RMS)

RL = 16 Ω
AV = −10 V/V

AV = −1 V/V AV = −1 V/V
10 10

VDD = 5 V,
BW = 10 Hz to 22 kHz
RL = 16 Ω,
1 1
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 17. Figure 18.

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CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
0 0
VDD = 3.3 V, VDD = 3.3 V,
−10 PO = 25 mW, −10 PO = 40 mW,
−20 CB = 1 µF, −20 CB = 1 µF,
RL = 32 Ω, RL = 16 Ω,
−30 AV = −1 V/V −30 AV = −1 V/V
−40 −40
Crosstalk − dB

Crosstalk − dB
−50 −50
−60 −60

−70 −70
−80 −80
IN2− to VO1
−90 IN2− to VO1 −90
−100 −100
IN1− to VO2
−110 IN1− to VO2 −110

−120 −120
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 19. Figure 20.

CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
0 0
VDD = 3.3 V, VDD = 5 V,
−10 PO = 60 mW, −10 PO = 60 mW,
−20 CB = 1 µF, −20 CB = 1 µF,
RL = 8 Ω, RL = 32 Ω,
−30 AV = −1 V/V −30 AV = −1 V/V
−40 −40
Crosstalk − dB

Crosstalk − dB

−50 −50
−60 −60

−70 −70
IN2− to VO1
−80 −80
IN2− to VO1
−90 −90
−100 IN1− to VO2 −100
IN1− to VO2
−110 −110

−120 −120
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 21. Figure 22.

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CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
0 0
VDD = 5 V, VDD = 5 V,
−10 PO = 100 mW, −10 PO = 150 mW,
−20 CB = 1 µF, −20 CB = 1 µF,
RL = 16 Ω, RL = 8 Ω,
−30 AV = −1 V/V −30 AV = −1 V/V
−40 −40
Crosstalk − dB

Crosstalk − dB
−50 −50
−60 −60

−70 −70
IN2− to VO1
−80 IN2− to VO1 −80
−90 −90
−100 −100
IN1− to VO2
−110 IN1− to VO2 −110

−120 −120
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz

Figure 23. Figure 24.

SHUTDOWN ATTENUATION SHUTDOWN ATTENUATION

vs vs
FREQUENCY FREQUENCY
0 0
VDD = 3.3 V, VDD = 5 V,
−10 RL = 16 Ω, −10 RL = 16 Ω,
CB = 1 µF CB = 1 µF
−20 −20
Shutdown Attenuation − dB

Shutdown Attenuation − dB

−30 −30

−40 −40

−50 −50

−60 −60

−70 −70

−80 −80

−90 −90

−100 −100
10 100 1k 10 k 1M 10 100 1k 10 k 1M
f − Frequency − Hz f − Frequency − Hz

Figure 25. Figure 26.

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OPEN-LOOP GAIN AND PHASE MARGIN OPEN-LOOP GAIN AND PHASE MARGIN
vs vs
FREQUENCY FREQUENCY
120 180 120 180
VDD = 3.3 V VDD = 5 V
150 150
100 RL = 10 kΩ 100 RL = 10 kΩ
Gain
120 120
Phase
80 90 80 90

Φm − Phase Margin − Deg

Open-Loop Gain − dB
Open-Loop Gain − dB

Φ m − Phase Margin − Deg

60 60
60 60
30 30
Gain Phase
40 0 40 0
−30 −30
20 20
−60 −60

0 −90 0 −90

−120 −120
−20 −20
−150 −150
−40 −180 −40 −180
1k 10 k 100 k 1M 10 M 1k 10 k 100 k 1M 10 M
f − Frequency − Hz f − Frequency − Hz

Figure 27. Figure 28.

OUTPUT POWER OUTPUT POWER

vs vs
LOAD RESISTANCE LOAD RESISTANCE
100 250
VDD = 3.3 V, VDD = 5 V,
THD+N = 1%, THD+N = 1%,
AV = −1 V/V AV = −1 V/V
200
75
P − Output Power − mW

P − Output Power − mW

150

50

100
O

25
O

50

0 0
8 12 16 20 24 28 32 36 40 44 45 52 56 60 64 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
RL − Load Resistance − Ω RL − Load Resistance − Ω

Figure 29. Figure 30.

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SUPPLY CURRENT SIGNAL-TO-NOISE RATIO

vs vs
SUPPLY VOLTAGE VOLTAGE GAIN
2.5 120
VDD = 5 V

100

SNR − Signal-to-Noise Ratio − dB

2
I DD − Supply Current − mA

80
1.5

60

1
40

0.5
20

0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1 2 3 4 5 6 7 8 9 10
VDD − Supply Voltage − V AV − Voltage Gain − V/V

Figure 31. Figure 32.

POWER DISSIPATION/AMPLIFIER
vs
LOAD POWER
80
VDD = 3.3 V
8Ω
70
Power Dissipation/Amplifier − mW

60

50

40 16 Ω

30

20 32 Ω

64 Ω
10

0
0 20 40 60 80 100 120 140 160 180 200
Load Power − mW
Figure 33.

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POWER DISSIPATION/AMPLIFIER
vs
LOAD POWER
180
VDD = 5 V
160 8Ω

Power Dissipation/Amplifier − mW
140

120

100
16 Ω
80

60

40 32 Ω

20 64 Ω

0
0 20 40 60 80 100 120 140 160 180 200
Load Power − mW
Figure 34.

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APPLICATION INFORMATION

GAIN SETTING RESISTORS, RF and Ri

The gain for the TPA6111A2 is set by resistors RF and RI according to Equation 1.

Gain 
 
RF
RI
(1)
Given that the TPA6111A2 is a MOS amplifier, the input impedance is high. Consequently, input leakage
currents are not generally a concern, although noise in the circuit increases as the value of RF increases. In
addition, a certain range of RF values is required for proper start-up operation of the amplifier. Taken together it
is recommended that the effective impedance seen by the inverting node of the amplifier be set between 5 kΩ
and 20 kΩ. The effective impedance is calculated in Equation 2.
R FR I
Effective Impedance 
RF
RI
(2)
As an example, consider an input resistance of 20 kΩ and a feedback resistor of 20 kΩ. The gain of the amplifier
would be –1 and the effective impedance at the inverting terminal would be 10 kΩ, which is within the
recommended range.
For high-performance applications, metal film resistors are recommended because they tend to have lower noise
levels than carbon resistors. For values of RF above 50 kΩ, the amplifier tends to become unstable due to a pole
formed from RF and the inherent input capacitance of the MOS input structure. For this reason, a small
compensation capacitor of approximately 5 pF should be placed in parallel with RF. In effect, this creates a
low-pass filter network with the cutoff frequency defined in Equation 3.
f c(lowpass)
1
2
R F CF
(3)
For example, if RF is 100 kΩ and CF is 5 pF, then fc(lowpass) is 318 kHz, which is well outside the audio range.

INPUT CAPACITOR, Ci
In the typical application, input capacitor CI is required to allow the amplifier to bias the input signal to the proper
dc level for optimum operation. In this case, Ci and RI form a high-pass filter with the corner frequency
determined in Equation 4.
f c(highpass)
1
2
R I CI
(4)
The value of CI is important to consider, as it directly affects the bass (low-frequency) performance of the circuit.
Consider the example where RI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz.
Equation 4 is reconfigured as Equation 5.
CI
1
2
R I f c(highpass)
(5)
In this example, CI is 0.40 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and
the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier
that reduces useful headroom, especially in high-gain applications (> 10). For this reason a low-leakage tantalum
or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to confirm the capacitor polarity in the application.

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APPLICATION INFORMATION (continued)

POWER SUPPLY DECOUPLING, C(S)
The TPA6111A2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF, placed as close as possible to the device VDD lead, works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the power
amplifier is recommended.

MIDRAIL BYPASS CAPACITOR, C(BYP)

The midrail bypass capacitor, C(BYP), serves several important functions. During start-up, C(BYP) determines the
rate at which the amplifier starts up. This helps to push the start-up pop noise into the subaudible range (so low it
cannot be heard). The second function is to reduce noise produced by the power supply caused by coupling into
the output drive signal. This noise is from the midrail generation circuit internal to the amplifier. The capacitor is
fed from a 230-kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship
shown in Equation 6 should be maintained.
1  1
 C
230 kΩ  C I R I
(BYP) (6)
As an example, consider a circuit where C(BYP) is 1 µF, CI is 1 µF, and RI is 20 kΩ. Inserting these values into
Equation 6 results in: 6.25 ≤ 50 which satisfies the rule. Recommended values for bypass capacitor C(BYP) are
0.1 µF to 1 µF, ceramic or tantalum low-ESR, for the best THD and noise performance.

OUTPUT COUPLING CAPACITOR, C(C)

In the typical single-supply single-ended (SE) configuration, an output coupling capacitor (CC) is required to block
the dc bias at the output of the amplifier, thus preventing dc currents in the load. As with the input coupling
capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by
Equation 7.
fc
1
2
R L C(C)
(7)
The main disadvantage, from a performance standpoint, is that the typically small load impedances drive the
low-frequency corner higher. Large values of C(C) are required to pass low frequencies into the load. Consider
the example where a C(C) of 68 µF is chosen and loads vary from 32 Ω to 47 kΩ. Table 1 summarizes the
frequency response characteristics of each configuration.

Table 1. Common Load Impedances vs Low Frequency

Output Characteristics in SE Mode
RL CC LOWEST FREQUENCY
32 Ω 68 µF 73 Hz
10,000 Ω 68 µF 0.23 Hz
47,000 Ω 68 µF 0.05 Hz

As Table 1 indicates, headphone response is adequate and drive into line level inputs (a home stereo for
example) is good.

16
 TPA6111A2
www.ti.com
SLOS313B – DECEMBER 2000 – REVISED JUNE 2004

The output coupling capacitor required in single-supply SE mode also places additional constraints on the
selection of other components in the amplifier circuit. With the rules described earlier still valid, add the following
relationship:
1  1  1
 C
230 kΩ  C R
I I
 RLC (C)
(BYP) (8)

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application. A real capacitor can be modeled simply as a
resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves
like an ideal capacitor.

5-V VERSUS 3.3-V OPERATION

The TPA6111A2 was designed for operation over a supply range of 2.5 V to 5.5 V. This data sheet provides full
specifications for 5-V and 3.3-V operation, since these are considered to be the two most common standard
voltages. There are no special considerations for 3.3-V versus 5-V operation as far as supply bypassing, gain
setting, or stability. The most important consideration is that of output power. Each amplifier in the TPA6111A2
can produce a maximum voltage swing of VDD – 1 V. This means, for 3.3-V operation, clipping starts to occur
when VO(PP) = 2.3 V as opposed when VO(PP) = 4 V while operating at 5 V. The reduced voltage swing
subsequently reduces maximum output power into the load before distortion begins to become significant.

17
 PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TPA6111A2D ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPA6111A2DG4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPA6111A2DGN ACTIVE MSOP- DGN 8 80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPA6111A2DGNG4 ACTIVE MSOP- DGN 8 80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPA6111A2DGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPA6111A2DGNRG4 ACTIVE MSOP- DGN 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPA6111A2DR ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPA6111A2DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6111A2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2009

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA6111A2DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
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