ISSCC 2019 / SESSION 3 / NYQUIST RATE ADCs / 3.

3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with In a pipelined ADC, D(VOUT) is already available in the pipeline’s digital output.
Background Monitoring of Distortion However, obtaining an accurate estimate of VX requires additional hardware and
is non-trivial due to the sensitivity of node X and the small amplitude of the signal
– on the order of ~1mV. A direct approach using a high-resolution auxiliary ADC
Benjamin Hershberg, Davide Dermit, Barend van Liempd, [5] is too complex and area-intensive to be practical for inclusion in each pipeline
Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx stage we wish to monitor.

imec, Leuven, Belgium An elegant alternative is to use a single-comparator stochastic ADC [6]. The
procedure is summarized in Fig. 3.1.4. In an initial preparation step, the
Giga-sample ADCs targeting high performance communication applications such comparator is connected to an on-chip reference ladder, its threshold offset is
as direct-RF sampling all rely on some form of residue amplification to minimize nulled, and it is provided with several scaled reference values, e.g. k·VREF/1024,
the number of interleaved channels and meet demanding specifications. Despite k = -3 to 3. The comparator output for each of these trials is used to determine
architectural efforts to reduce the total number of amplifiers in the system, the its noise distribution in absolute terms (volts per sigma). In a second preparation
challenges associated with designing them for high bandwidth and linearity has step, the comparator is re-connected to node X and its threshold offset is again
limited reported power efficiencies [1]. In this work, we show that ring nulled while sampling VX. Now the main measurement begins. As samples of VX
amplification [2] can overcome this longstanding bottleneck. In an architecture are quantized by the comparator, they are sorted with respect to D(VOUT) into
using 36 ringamps, the 3.2GS/s ADC consuming 61.3mW has a Nyquist SNDR “bins”. To reduce computational complexity, each bin processes a contiguous
of 61.7dB, SFDR of 73.3dB, Walden FoM of 19.2fJ/conv-step, and Schreier FoM range of D(VOUT) codes, rather than just one code per bin, without loss of final
of 165.9dB. Furthermore, we demonstrate a general technique whereby the signal- estimation accuracy. Sorting is simply a matter of demuxing with respect to the
to-distortion ratio (SDR) of any amplifier in the system can be independently MSBs of D(VOUT). Each bin computes the mean value of its binary input vector
monitored in the background with an analog hardware overhead of only one and converts this cumulative-distribution value to a corresponding probability-
comparator. density “sigma” with the inverse error function. The output is then multiplied by
the volts-per-sigma conversion factor acquired earlier and muxed with respect to
The top-level system details are provided in Fig. 3.1.1. The ADC input is buffered D(VOUT). The resulting output is an estimate of VX that, due to the processing
by an AC-coupled pseudo-differential class-AB push-pull source follower. A clock procedure, has been stripped of noise, but still contains a high accuracy estimate
buffer converts a differential sine into a single-ended square. The ADC core of all non-random errors. Consequently, the output of the estimator block
consists of four interleaved pipeline channels, each containing nine scaled 1.5b becomes SDR rather than SNDR.
MDAC stages followed by a 1.5b+3b backend.
In Fig. 3.1.5 we show in measurement how this estimation technique is used to
The stage 1 MDAC of the channel is shown in Fig. 3.1.2. Here, we introduce a characterize the performance of the CH0, STG1 ringamp with respect to its digital
passive-hold mode into the operation of the MDAC. In the illustrated switching bias control. For comparison, the THD of CH0, calculated from an FFT of its digital
scheme, during ϕQ the voltage at node X will be -αVIN, where α represents output, is overlaid. Considering that THD and SDR are not identical quantities,
attenuation due to parasitics. The sub-ADC is attached to node X, and uses this and that the THD also includes distortion from other stages in the channel, the
held value for quantization during ϕQ. Because the charge sampled onto the MDAC correspondence between these two curves is very close. Also notable is the broad
capacitors (CU) is used for both quantization and residue amplification, all skew range of bias codes that give near-optimal performance, indicating that the
and bandwidth related mismatch between the MDAC and sub-ADC is eliminated. ringamp is robust to variation.
This also eliminates the need for a dedicated sub-ADC sampling network, reducing
the input buffer load. To minimize its parasitic influence on analog loop The ADC is fabricated in a 16nm CMOS technology and occupies an active area
performance during ϕA, the sub-ADC comparator uses the source-shifted of 0.194mm2 (360μm × 540μm), excluding decoupling (Fig. 3.1.7). A single, fixed
programmable threshold topology of [3] which gives low decision delay even with configuration of digital settings and stage gain correction coefficients (determined
near-minimum sized input transistors. off-chip) are used in all measurements. Performance is summarized in Fig. 3.1.5
and Fig. 3.1.6. At 3.2GS/s, total power consumption is 61.3mW, with 11.2mW in
The fully differential ring amplifier is illustrated in Fig. 3.1.3. Because it is only the input buffer, 2.4mW in the clock buffer, and 11.9mW per channel. The
needed during ϕA, the structure is designed to support rapid power cycling. references are 50mV and 800mV, allowing the ringamps to utilize 88% of the
Stability is enforced with a CMOS resistor [4], which operates as a switch during available 0.85V supply. In the input frequency sweep of Fig. 3.1.5, the dip in SFDR
power-down and a tunable bias control during normal operation. The effective around 1GHz is dominated by HD3, and found to be packaging related.
resistance can be adjusted with the two charge-sharing DACs of Fig. 3.1.3. These Compression near full-scale is due to input buffer HD3.
set a trapped-charge bias voltage onto the gates of the CMOS resistor. The
common-mode feedback (CMFB) of the ringamp consists of three feedback loops. Compared to all ADCs above 1.7GS/s achieving SNDR > 51dB in [1], this work
Two of these loops operate on the trapped-charge present at floating node B1. achieves the highest reported SNDR at Nyquist and advances the Walden and
This approach ensures correct biasing in the presence of kickback due to power Schreier FoM state-of-the-art by 8× and 12dB respectively. This is made possible
cycling. Charge can only enter or exit node B1 through CSMALL, and the first CMFB not only by the direct performance advantages of ring amplifiers, but also the
loop uses this slow injection path to regulate DC biasing. Per-cycle common- indirect advantage of greater design freedom when amplification is relaxed as an
mode variations are suppressed by the fast second loop formed by CFB. architectural constraint.
Transistors MCM1 and MCM2 form the third loop, and ensure stability by increasing
phase margin. References:
[1] B. Murmann, "ADC Performance Survey 1997-2018," [Online]. Available:
To ensure optimal performance of the ringamps in the presence of PVT variation, http://web.stanford.edu/~murmann/adcsurvey.html.
a general technique for background measurement of SDR in switched capacitor [2] B. Hershberg, et al., "Ring Amplifiers for Switched Capacitor Circuits," IEEE
feedback circuits is introduced in Fig. 3.1.4. It is based on the observation that JSSC, vol. 47, no. 12, Dec. 2012.
the summing-node voltage VX is equal to the input-referred error of VOUT. A portion [3] E. Martens, et al., "Wide-tuning range programmable threshold comparator
of this error is due to the finite gain of the amplifier (AOL), and in [5] it is shown using capacitive source-voltage shifting," IET Electronics Letters, Sept. 2018.
how repeated measurements of VX and VOUT can be used to estimate and correct [4] J. Lagos, et al., “A single-channel, 600Msps, 12bit, ringamp-based pipelined
for it. However, other well-known background calibration techniques can correct ADC in 28nm CMOS," IEEE Symp. VLSI Circuits, pp. 96-97, June 2017.
not only for finite gain error but also capacitor mismatch, so we are not directly [5] A. Ali, et al., “A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background
concerned with the VOUT/AOL component of VX in this work. Rather, we are Calibration,” IEEE JSSC, vol. 45, no. 12, Dec. 2010.
interested in the remainder of VX, which contains all other noise and distortion [6] B. Verbruggen, et al., "A 60 dB SNDR 35 MS/s SAR ADC With Comparator-
components of the feedback system – that is, SNDR. As described by the Noise-Based Stochastic Residue Estimation," IEEE JSSC, vol. 50, no. 9, Sept.
equations of Fig. 3.1.4, the estimated average open loop gain ÂOL can be calculated 2015.
with a linear regression, and after its removal from VX, the SNDR can be estimated.

58 • 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE

Authorized licensed use limited to: ShanghaiTech University. Downloaded on September 09,2024 at 02:07:59 UTC from IEEE Xplore. Restrictions apply.
 ISSCC 2019 / February 18, 2019 / 1:30 PM

Figure 3.1.1: Top-level architecture. Figure 3.1.2: Merged MDAC and sub-ADC with passive hold mode.

Figure 3.1.4: Method for background estimation of signal-to-distortion ratio

Figure 3.1.3: Fully differential ring amplifier. (SDR).

Figure 3.1.5: Demonstration of SDR measurement and key performance

metrics. Figure 3.1.6: Spectrums for LF/HF inputs and performance summary.

DIGEST OF TECHNICAL PAPERS • 59

Authorized licensed use limited to: ShanghaiTech University. Downloaded on September 09,2024 at 02:07:59 UTC from IEEE Xplore. Restrictions apply.
 ISSCC 2019 PAPER CONTINUATIONS

Figure 3.1.7: Chip micrograph.

• 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE

Authorized licensed use limited to: ShanghaiTech University. Downloaded on September 09,2024 at 02:07:59 UTC from IEEE Xplore. Restrictions apply.