RS-232 TO HDLC CONVERTER

(Development of VHDL Code)

Project report submitted to

Visvesvaraya National Institute of Technology, Nagpur
in partial fulfillment of the requirements for the award of
the degree

Bachelor of Technology
In
Electronics and
Communication Engineering

by
Prasanth N. (BT15ECE062)
Snita M. (BT15ECE087)
Keerthana V. (BT15ECE094)

under the guidance of

Dr. Abhay S. Gandhi

Department of Electronics and Communication

Visvesvaraya National Institute of Technology
Nagpur 440010 (India)

2019
 © Visvesvaraya National Institute of Technology (VNIT) 2009

DECLARATION

We hereby declare that this project work titled “RS-232 to HDLC Converter” is
carried out by us in the Department of Electronics and Communication Engineering of
Visvesvaraya National of Technology, Nagpur. The work has not been submitted earlier
whole or in part for the award of any degree/diploma at this or any other
Institution/University.

Prasanth N. (BT15ECE062)
Snita M. (BT15ECE087)
Keerthana V. (BT15ECE094)

Date:
 CERTIFICATE

This is to certify that the project titled “RS232 to HDLC Converter” submitted by
in partial fulfillment of the requirements for the award of the degree of ​Bachelor of
Technology in Electronics and Communication Engineering​, VNIT Nagpur. The
work is comprehensive, complete and fit for final evaluation.

​Dr.​ ​Abhay S. Gandhi

Professor
Department of Electronics
and Communication
VNIT Nagpur

Dr. Kishor Bhurchandi

HOD
Department of Electronics
and Communication
VNIT Nagpur
 ACKNOWLEDGMENT

We are grateful to a number of people who made this thesis a worthwhile one by
their generosity and benevolence. The list may not be exhaustive, but we would like to
mention people whom we feel indebted to:

Firstly, we extend our gratitude to Professor, Dr. Abhay Gandhi, Department of

Electronics and Communication Engineering, Visvesvaraya National Institute of
Technology, Nagpur for giving us this project and for his guidance, constructive criticism
and suggestions throughout the project.

We also thank all of our friends who helped us in completing the project. We
would also like to extend our thanks to our family who has been by us throughout the
year.
 ABSTRACT

RS 232 is a standard serial communication protocol and is widely used in

industrial applications due to its simplicity. However, it cannot be used to transfer data to
longer distances. In such applications, the HDLC protocol is to be used. HDLC protocol
supports long-distance communication and has an error checking mechanism like CRC
calculation so that the errors in data can be identified. The purpose of this project is to
convert the RS-232 serial communication protocol to the HDLC protocol.

At the transmitter side, the serial asynchronous data is made synchronous with the
help of UART. Next, the HDLC frames are formed from this serial data into a 56-bit
frame. These HDLC frames are next sent into the circular buffer before transmitting
where there is a flexibility of transmitting data with the help of read and write pointers.
Finally, the data is line coded using Manchester coding technique and the 56-bit HDLC
frames are transmitted.

At the receiver, the received HDLC frames in Manchester format are decoded
using Manchester decoder. Using a clock recovery circuit, the clock for the receiver side
is recovered. From the data field of the HDLC frame, the CRC is calculated using the
same polynomial used at the transmitter side and the 16-bit CRC is verified with the
received CRC field to ensure error-free transmission. If the received data is error-free,
then the data field in the HDLC frame is converted to serial RS-232 format using a
parallel to serial converter.

In this way, at the transmitter side, RS-232 serial bits are converted to HDLC
frames and transmitted and at the receiver side, the HDLC frames are converted to
RS-232 serial bits.
 List of Figures

Figure 1.1 Pin Diagram of​ DB9 Connector

Figure​ ​1.2 RS​-​232 Standard Voltage Levels

Figure 1.3 HDLC Frame Structure

Figure 1.4 Manchester Line Encoding Principle

Figure 1.5 ​Schematic Representation of Manchester Decoder and Clock Recovery

Module
Figure​ ​1.6 Waveforms Generated by Manchester Decoder and Clock Recovery
Module

Figure 2.1 Transmitter Block Diagram

Figure 2.2 Addition of Start and Stop Bit

Figure 2.3 16-Bit CRC Calculation

Figure 2.4 Receiver Block Diagram

Figure 3.1 UART

Figure 3.2 CRC Calculation

Figure 3.3 HDLC Frame Formation

Figure 3.4 Circular Buffer

Figure 3.5 Transmitter Output

Figure 3.6 Encoder Output

Figure 3.7 Transmitter with Encoder Output

Figure 3.8 Clock Recovery and Decoding

Figure 3.9 CRC Check

Figure 3.10 Parallel to Serial Converter

Figure 3.11 Serial in Parallel Out 56-Bits

 Index

Page No

Chapter 1: Introduction

1.1 Introduction to Communication Protocols 04

1.2 RS-232: Recommended Standard 04
1.3 HDLC: High-Level Data Link 05
1.4 UART: Universal Asynchronous Receiver Transmitter 06
1.5 Circular Buffer 06
1.6 Line Encoding 06
1.7 Literature Review
1.7.1 Manchester Decoder and Clock Recovery 07
Module Using Xilinx
1.7.2 Zilog SCC™/ESCC™ User Manual 08

Chapter 2: Work Done

2.1 Transmitter Side 10

2.1.1 UART 10
2.1.2 HDLC Frame Formation 10
2.1.3 Circular Buffer 11
2.1.4 Line Coding 12
2.2 Receiver Side 12
2.2.1 Manchester Decoding 12
2.2.2 Error Checking 12
2.2.3 RS-232 Serial Data 12

Chapter 3: Results and Discussion ​14

Chapter 4: Conclusion and Future Scope

4.1 Conclusion 28

4.2 Future Scope 28

Chapter 5: Appendix

5.1 Transmitter Code 30

5.2 Receiver Code 37

Chapter 6: References

6.1 Papers 47

6.2 Links 47

6.3 Manuals/Books 47
 Chapter 1
Introduction
1.1 Introduction to Communication Protocols
A communication protocol is a set of rules that allow two or more communications
systems to transfer information between them. The protocol defines the set of rules, syntax,
and synchronization of the communication systems with error checking methods in some
cases. These protocols may be implemented by hardware, software, or a combination of
both. ​The information transfer between communication devices through a network is
controlled by these rules that can be set in protocol specifications. In this project, we focus
on two communication protocols namely RS-232 (Recommended Standard 232) and HDLC
(High-level Data Link Control) protocols.

1.2 RS-232: Recommended Standard-232

RS-232 is a standard protocol used for serial communication, it is used for
connecting the computer and its peripheral devices. This is widely used even today in
various devices due to its simplicity. In this protocol, user data is sent as a time series of
bits, where both synchronous and asynchronous transmissions are supported. ​They use
connectors known as DB9 Connector.

Fig 1.1​ Pin Diagram of ​DB9 Connector

The RS-232 standard defines specific voltage levels for logic one and logic zero.
Valid logic 0 is in the range of +3 to +15 volts and valid logic 1 is in the range of −3 to
−15 volts. The range between −3 to +3 volts is not a valid RS-232 level​. ​It is used in
serial communication up to 50 feet with a rate of 1.492 kbps. They use connectors known
as DB9 Connector.
The voltage levels for the corresponding logic levels are given below:

Fig ​1.​2​ ​RS​-​232 Standard Voltage Levels

1.3 HDLC: High-Level Data Link Control

HDLC (High-level Data Link Control) is a protocol for transmitting data between
network points. It is a bit-oriented, synchronous data link layer protocol developed by the
International Organization for Standardization (ISO). ​HDLC provides both
connection-oriented and connectionless service. ​In HDLC, data is organized into frames
and sent across a network to a destination which verifies whether the frames have arrived
successfully. The flow or pacing at which data is sent can also be controlled by this
protocol​. The frames can be transmitted over synchronous and asynchronous serial
communication links. The HDLC Frame Structure is as follows:

Fig 1.​3​ HDLC Frame Structure

The various fields constituting the HDLC frame are as follows,

Flag: It indicates the start and end of the frame. ​the flag sequence is binary "01111110",
or 0x7E in hexadecimal. Two flag fields each of 8 bits is present at the start and end of
the HDLC frame.
Address Field: It is a user defined field which contains the destination address and helps
with the proper transfer of data.
Control Field: It is a user defined field which contains various control signals for error
control.
Information: ​Information field or Data field is the user data that is to be transmitted and
is of variable length. Here we consider the data field to be of 8 bits wide.
FCS: ​Frame Check Sequence ​is a 16-bit CRC, a cyclic redundancy check, or a 32-bit
CRC computed over the Address, Control, and Information fields. Here the 16-bit CRC is
calculated only for the data field which is of 8 bits.
Hence the entire HDLC frame consists of 56 bits and one HDLC frame is to be
formed for every 8 bits of serial data in RS 232 format.

1.4 UART
The universal asynchronous receiver-transmitter (UART) takes bytes of
asynchronous data and transmits the individual bits in synchronous serial format. In this
data format and transmission, speeds are configurable. UART has a number of
advantages such as:
1. Serial transmission of digital information (bits) through a single wire or other
medium is less costly than parallel transmission through multiple wires.
2. Clock transmission is not necessary.
3. To ensure that the correct data is received it also has parity to allow for error
checking.

1.5 Circular Buffer

​Buffers are generally used in communication systems involving two or more
systems or modules operating at different speeds. The main function is to maintain proper
communication such that data is not lost due to the disparity in the operating rates/speeds.
Circular Buffers are used to maintain the proper data rate between the RS-232 and
HDLC formats. It is well-suited as a FIFO buffer, which is required in our application. It
has two pointers read and write with the help of which data can be read out and written
into the buffer. Circular buffers are widely implemented in industries for long distance
effective communication, as the data rates are variable. They also have better error
control.
1.6 Line Encoding
Here we have used Manchester line coding in which data bits are represented by
transitions from one logical state to the other. The state of a bit is determined according
to the direction of the transition. In this, we have used Manchester Encoding, as due to
the high number of transitions, clock recovery on the receiver side is made easier with the
use of Digital Phase Locked Loop. The error rate is minimized thus it is reliable. Also,
no DC component is present.

Fig 1.4​ Manchester Line Encoding Principle

1.7 Literature Review

1.7.1 Manchester Decoder and Clock Recovery Module Using Xilinx​[1]

Manjuvani. K. M, Manasa K. Chigateri, Prashanth Keni, Manjunath K. M, ​(2016)

This paper is about the building a Manchester decoder and a module which
recovers clock. In the module, using two counters, the time between consecutive edges of
Manchester encoded data is measured. The Manchester half-cycle duration is calculated
using the measured time, which is used to recover the clock. The module receives
Manchester encoded data and generates three signals. One clock of the same frequency as
the input Manchester data. The second clock of double the frequency. The third is the
sequence of decoded data bits.
 Fig 1.5 ​Schematic Representation of Manchester Decoder and
Clock Recovery Module

​Fig
1.6​ Waveforms Generated by Manchester Decoder and
Clock Recovery Module

1.7.2 Zilog SCC™/ESCC™ User Manual​[11]

From this manual, Manchester encoding has been studied. Manchester encoding
always produces a transition at the center of the bit cell. If the transition is Low to High,
the bit is 0. If the transition is High to Low, the bit is 1.
 Chapter 2
Work Done
2.1 Transmitter Side

Fig 2.1​ Transmitter Block Diagram

2.1.1 UART
First, the serial data bits in RS-232 format are given as input to the UART. The
UART appends a start bit ‘1’ and a stop bit ‘0’ for every 8 bits of serial data. Thus, the
serial data becomes synchronous along with the start and stop bits.

Fig 2.2

Addition of Start and Stop Bits

2.1.2 HDLC Frame Formation

An HDLC frame of 56 bits is to be formed from these serial bits of data. The
specifications taken for the frame are:
Flag Field: ​The flag field consists of ‘7E’ (01111110) and there is a flag at the start and
end of the HDLC frame.
Control and Address Fields: The control and address fields are of 8 bits each and are
left as user-defined inputs.
Information Field: The HDLC frame consists of an 8-bit information field. For this, the
serial data is converted to 8-bit parallel data using serial to parallel converter and this
constitutes the information field.
Frame Check Sequence: ​The HDLC frame consists of a 16-bit CRC. Using the 8 bits of
serial data and the polynomial (x​16​+x​12​+x​5​+1), a 16-bit CRC is calculated which
constitutes the FCS field of the HDLC frame. Here the bitwise representation of the
polynomial (x​16​+x​12​+x​5​+1) is ‘10001000000100001’. The 8-bit data is assumed to be
‘11111111’. The CRC calculation process involved is shown below:

Fig 2.3​ 16 Bit CRC Calculation

Finally, a 56-bit HDLC frame is formed for every 8 bits of serial data in RS-232 format.

2.1.3 Circular Buffer

In the circular buffer, the HDLC frames of 56 bits each are stored at different
address locations. Two pointers, one read, and one write are used to write data into the
buffer and read the data from the buffer. After the HDLC frame formation, the frame is
stored at the location where the write pointer is pointed. The writer pointer increments,
and the next frames are stored in the successive locations. The read pointer points to the
last location and when the buffer is full, the last frame is read out from the buffer.
Circular buffer allows flexibility in the transmission of HDLC frames using read and
write pointers.

2.1.4 Line Coding

Before the data is to be transmitted, line coding needs to be done. Here
Manchester line coding has been used. The bit ‘0’ is represented as a transition from 0 to
1 and bit ‘1’ is represented as a transition from 1 to 0. Finally, the Manchester line coded
HDLC frames is transmitted.

2.2 Receiver Side

Fig 2.4 ​Receiver Block Diagram

2.2.1 Manchester Decoding

Manchester coding has been used at the transmitter side so that the clock recovery
at the receiver side is possible without transmitting the clock separately along with data.
Manchester decoding of the entire HDLC frame is done.

2.2.2 Error Checking

The polynomial (x​16​+x​12​+x​5​+1) which is used at the transmitter side to calculate
the 16-bit CRC, is used at the receiver side also to check whether the data and CRC fields
are received without any errors. For the received data field of 8 bits, CRC is again
calculated using the same polynomial and checked with the received CRC field. If they
match, there is no error in the transmission process.
2.2.3 RS-232 Serial Data
After checking that the received HDLC frame is error-free, the 8-bit information
field in the frame, is converted to serial data of bits using parallel to serial converter and
this forms the final serial data in RS-232 format.
 Chapter 3
Results and Discussions
3.1 UART
‘Bclk’ and ‘sysclk’ are the two clocks used for the working of UART. ‘DBUS’ is
the data give to the UART. In this case, it is ‘10101010’. ‘State’ indicates the three states
of UART namely IDLE, SYNC and TDATA. In TDATA state the data is transmitted.
‘TxD’ is the final data output after adding start and stop bits. Here we can observe that a
start bit ‘1’ and a stop bit ‘0’ are added to the data.

3.2 CRC Calculation

‘Clk’ is the clock used for CRC calculation and ‘datafr’ is the data for which the
CRC is calculated. ‘size_data’ is the data size which has been taken as 8 bits in this case.
‘ctrl’ and ‘add’ are the control and address fields which are user-defined. In this case, we
assume both to be ‘10101010’. ‘crc_ready’ indicates the completion of the CRC
calculation. We can observe that after the crc_ready is high, ‘crc_out’ becomes
‘0001111011110000’ which is the 16-bit CRC required.

3.3 HDLC Frame Formation

Here ‘clk’, ‘datafr’, ‘size_data’, ‘ctrl’, ‘add’, ‘crc_ready’, ‘crc_out’ are already
defined above. ​‘datafin’ is the HDLC data frame formed which contains
‘01111110101010101010101011111111000111101111000001111110’
First 8 bits indicate the flag ‘01111110’ while the next 16 bits are of control and
address fields together which contain ‘1010101010101010’. The next 8 bits are of the
data field which contain ‘11111111’ followed by the 16-bit CRC which is
‘0001111011110000’.
The last 8 bits indicate the flag again ‘01111110’.

3.4 Circular Buffer

We can observe that the HDLC frames formed are stored at different memory
locations. ‘readptr’ and ‘writeptr’ indicate the read and write pointers through data can be
read out and written into the buffer.
3.5 Transmitter Output
In the output, ‘datafin’ and ‘datatx’ indicate the final HDLC frame and the data to
be transmitted in Manchester format.

3.6 Encoder Output

‘​datarx’ is the data which is to be manchester encoded. ‘dout’ is the manchester
encoded data with respect to the clock signal ‘clkps’. Here a high to low transition
represents ‘1’ and a low to high transition represents ‘0’.

3.7 Transmitter with Encoder Output

‘dataen’ is the final manchester encoded data which is to be transmitted.

3.8 Clock Recovery and Decoding

From Manchester data ‘MANCH’ using two counters operating on ‘CLK’, we
recover clock ‘clkrec’ and decoded data ‘Decdata’.

3.9 CRC Check

The signal ‘datarx’ indicates the received data and ‘crcout’ indicates the CRC
calculated at the receiver. We can observe that the CRCs calculated at the transmitter and
the receiver are the same which indicates error-free transmission.

3.10 Parallel to Serial Converter

Within the parallel to serial converter, ‘din’ is the parallel data input and ‘dout’ is
the serial data output.

3.11 Serial in Parallel Out 56-Bits

The decoded data is converted into parallel (56-bits) form.
 Chapter 4

Conclusion and Future Scope

4.1 Conclusion

At the transmitter, the serial data in RS-232 format ​has been converted to HDLC
frame format. For every 8 bits of serial data, an HDLC frame of 56 bits was formed
which consists of different fields like flag, address, control, data, CRC and these HDLC
frames were transmitted after encoding.

At the receiver, the Manchester encoded data has been decoded and the clock was
recovered. In the received HDLC frames, the 16-bit CRC was calculated for the data field
and checked with the CRC field of the received HDLC frame. The 8-bit data field is
converted to RS-232 serial data, confirming successful transmission of data.

4.2 Future Scope

● The control field is left as user-defined and assumed to be ‘10101010’ while when
it comes to implementation, the control field consists of control signals which are
used for error checking purpose.
● The address field also is left as user-defined and assumed to be ‘10101010’. It
generally consists of the destination address of the port to which the data frame is
to be transmitted.
● The data field we have considered is of 8 bits and which can be extended to 16 or
32 bits.
● For error detection, we have used a 16-bit CRC which can be extended to 32 bits
for better error correction.
● The circular buffer size can be increased so that the number of HDLC frames can
be stored in it increases.
Chapter 6
References
6.1 Papers

[1] Manjuvani. K. M, Manasa K. Chigateri, Prashanth Keni, Manjunath K. M,

“Manchester Decoder and Clock Recovery Module Using Xilinx”, (2016)

6.2 Links

[2] https://en.wikipedia.org/wiki/RS-232

[3] https://nptel.ac.in/courses/106105080/pdf/M3L4.pdf

[4] ​http://ecomputernotes.com/computernetworkingnotes/routing/hdlc-high level

data-link-control

[5] www.zilog.com/docs/serial/z85c30.pdf

[6] ​https://www.geeksforgeeks.org/computer-network-manchester-encoding/

[7] ​https://web.stanford.edu/class/cs140e/notes/lec4/uart-basics.pdf

[8] ​https://en.wikipedia.org/wiki/Cyclic_redundancy_check

[9] ​https://docslide.us/documents/manchesterdecoderandclockrecoveryageev.html?h=
docslide.com.br

7.3 Manual/Books

[10] Zilog SCC™/ESCC™ User manual

[11] A VHDL Primer,3rd Edition by J. Bhasker