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ISSCC 2009 / SESSION 23 / PLLs AND CLOCKS / 23.4

23.4 A 975-to-1960MHz Fast-Locking Fractional-N Ndec. The frequency counting error is 1/Tcntr, so the unit comparison time Tcntr
Synthesizer with Adaptive Bandwidth Control and should be long enough to reduce the frequency counting error. In addition, the
decoded modulus Ndec should be an integer, hence p can be selected as an
4/4.5 Prescaler for Digital TV Tuners
integer power of two, where p=16 is chosen in this design. The remaining
undecoding modulus induces the residual fractional error, which results in a
Lei Lu1,2, Zhichao Gong1,2, Youchun Liao2, Hao Min1, Zhangwen Tang1
maximum of 2-4·fref. Due to the high-speed property for counting VCO clock
Fudan University, Shanghai, China
1 directly, cascaded asynchronous divide-by-2 counters with a multiplexer is
Ratio Microelectronics, Shanghai, China
2 used. The multiplexer outputs fvco during Tcntr when hold is low, and Ncntr is
read after the last counter finishes. To save the power, the first three counters
There is a high demand for high-performance tuners to meet the digital video are realized in TSPC logic and remaining counters employ digital circuits.
broadcasting-terrestrial (DVB-T) standard. Often the DVB-T tuners employ a
double-conversion zero-IF (DZIF) architecture that demands a wideband frac- Figure 23.4.3 shows the schematic of the feedback divider which includes a
tional-N synthesizer as the first local oscillator (LO1) to cover the frequency new 4/4.5 prescaler and a double-edge-triggered retiming circuit. This
range of 975 to 1960MHz. This LO1 needs to meet a stringent phase-noise prescaler consists of 4 DFFs, 2 MUXs and 2 D-latchs, and the remaining 4
AND gates can be embedded into the DFF and the D-latch to increase the max-
requirement with an adequate target phase noise of –87dBc/Hz at a 10kHz off-
imal working frequency. DFF1 and DFF2 are triggered at the falling edge and
set and integrated rms phase error less than 1° [1]. Because of the very wide
DFF3 and DFF4 are triggered at the rising edge. The multiplexer MUX5 choos-
frequency range, the variation of loop bandwidth may affect the phase-noise
es Q2 or Q4 to output every half clock period in turn. Two latches (Dlatch6 and
performance and loop stability.
Dlatch7) and one multiplexer (MUX8) form a double-edge-triggered flip-flop
(DTFF) [4]. When the control signal mod is high, the DTFF is enabled, and the
This paper presents a wideband fractional-N synthesizer whose loop band-
prescaler works in divide-by-4.5 mode. Q8 lags half a period behind Q5 and
width is controlled adaptively. A fast automatic frequency-control (AFC) tech-
DFF1-4 and MUX5 swallow half extra period of input signal fvco due to the delay
nique which selects the subband of the VCO is proposed to reduce the resid-
ual fractional error to 1/16 of the reference frequency fref. A new 4/4.5 of Q8. To match the double-edge-triggered property of the prescaler and elim-
inate the accumulated jitter in the feedback divider, another DTFF is used to
prescaler is adopted to lower the quantization noise by reducing the quantiza-
retime the feedback signal triggered by the high-speed VCO clock. The power
tion step size to 0.5.
spectral density (PSD) of PLL phase noise contributed by the DSM is propor-
tional to the PSD of quantization noise, which is determined by the quantiza-
Figure 23.4.1 shows the block diagram of the wideband fractional-N synthe-
tion step. By using the 4/4.5 prescaler, the quantization step size is reduced to
sizer and a simplified LC-tank of the wideband VCO. Charge pump (CP) and
0.5, so a 6dB improvement of phase noise contributed from the DSM can be
VCO are both differentially configured to suppress common-mode noise from
achieved.
control lines, substrate and power supply. The loop filter (LPF) is fully inte-
grated in differential mode to save the die area. The loop bandwidth of the
The wideband fractional-N synthesizer is fabricated in a 0.18µm CMOS
fourth-order synthesizer can be expressed as
process with a total power consumption of 25mW from a 1.8V supply. The die
, FS . YFR I UHI 5& area is 1.58mm2, including LPF and PADs. Figure 23.4.4 shows the measured
Loop bandwidth =  (1)
ʌI YFR & + & + & 3dB closed-loop bandwidth and integrated rms phase error from 100Hz to
40MHz across the 1GHz tuning range. When adaptive Icp control is enabled,
where Icp is the CP current, Kvco is the VCO tuning gain, fvco is the output fre-
the closed-loop has an average 3dB bandwidth of 92.5kHz with the variation
quency, R1, C1, C2, and C3 are parameters of LPF. Two factors affect the loop
less than 10.3%. While adaptive Icp control is disabled, the bandwidth varia-
bandwidth. Firstly, the VCO gain Kvco may change greatly in the conventional
tion is about 70.4%. In calibration-enable mode, the rms phase error is from
LC-tank which employs binary-weighted switched capacitors and unchanged 0.6° to 1.05°.
varactors. In this design, the wideband VCO has a low tuning gain by dividing
the tuning range into 256 subbands. To maintain both Kvco and band steps Figure 23.4.5 shows the typical measured phase noise in fractional-N mode.
between center frequencies of two adjacent subbands, switched capacitors The phase noise is –95dBc/Hz at a 3kHz offset and –126.5dBc/Hz at a 1MHz
and switched varactors are both adjusted simultaneously with different values offset. Figure 23.4.6 shows that the synthesizer has a total locking time of
of units, where α1 to α255 and β1 to β255 are programmed coefficients and ther- 20µs with only 6.4µs for AFC, while the conventional AFC counting the signal
mometer coding is used here [2]. Secondly, 4 MSBs of the AFC output are divided by 8 from VCO consumes 42.4µs. The die micrograph and perform-
used to set the CP current Icp adaptively, thus making Icp match the selected ance summary are shown in Figure 23.4.7.
subband of VCO and proportional to the output frequency fvco. Therefore, with-
out changing LPF parameters, the loop bandwidth is adaptively controlled by Acknowledgements:
maintaining Kvco and making Icp match fvco across the whole wide frequency The work was partly supported by the National 863 Program of China Grant No.
2007AA01Z282 and the National Science Funding of China Grant No. 60876019. The
range. authors would like to thank Lee Yang at SMIC for chip fabrication.

To control the wideband multi-band VCO, the AFC technique is used to select References:
the subband of VCO whose center frequency is closest to the target frequen- [1] D. Saias, F. Montaudon, E. Andre, et al., “A 0.12µm CMOS DVB-T Tuner,” ISSCC Dig.
cy automatically. Conventional AFC compares feedback signal fdiv with refer- Tech. Papers, pp. 430-431, Feb., 2005.
ence signal fref, and shifts the subband of VCO according to the binary-search [2] L. Lu, L. Yuan, H. Min, and Z. Tang, “A Fully Integrated 1.175-to-2GHz Frequency
Synthesizer with Constant Bandwidth for DVB-T Applications,” IEEE Radio Frequency
algorithm [3]. However, AFC operates when the PLL is open, then fdiv only Integrated Circuits Symp., pp. 303-306, Jun., 2008.
comes from the signal divided by the integer modulus N of the division ratio [3] M. Marutani, H. Anbutsu, M. Kondo, et al., “An 18mW 90 to 770MHz Synthesizer with
N.F, which ignores the fractional modulus .F, thereby causing the residual Agile Auto-Tuning for Digital TV-Tuners,” ISSCC Dig. Tech. Papers, pp. 192-193, Feb.,
fractional error to amount to as high as 1·fref. Figure 23.4.2 shows the pro- 2006.
posed division-ratio-based AFC that can reduce the fractional error effectively. [4] Y.-C. Yang, S.-A. Yu, T. Tang, and S.-S. Lu, “A Quantization Noise Suppression
Technique for ΔΣ Fractional-N Frequency Synthesizers,” IEEE J. Solid-State Circuits, vol.
During the period Tcntr, the VCO clock fvco is counted to Ncntr. At the same time,
41, no. 11, pp. 2500-2511, Nov., 2006.
the target frequency relates with Ndec, and Ndec is obtained from the product of
p multiples of N.Fdec, which includes the integer modulus and 4 MSBs of frac-
tional modulus of the desired division ratio N.F. Then the subband of VCO is
shifted up or down according to the value of the difference ε between Ncntr and

396 • 2009 IEEE International Solid-State Circuits Conference 978-1-4244-3457-2/09/$25.00 ©2009 IEEE

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ISSCC 2009 / February 11, 2009 / 10:15 AM

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Figure 23.4.1: Block diagram of the fully integrated fractional-N synthesizer and sim-
plified LC-tank of the wideband VCO. Switched capacitors and varactors are adjusted Figure 23.4.2: Block diagram and principle of the presented division-ratio-based fast
to maintain VCO gain and band steps simultaneously. AFC technique.

 
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Figure 23.4.4: Measured integrated rms phase error and 3dB closed-loop bandwidth
Figure 23.4.3: Schematic of the 4/4.5 prescaler and double-edge-triggered retiming across the entire output range. Disabled calibration is to fix the Icp at the value with out-
circuit. put frequency of 1.5GHz in enabled calibration mode.

 
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Figure 23.4.6: Comparison of the measured total locking time, including AFC and PLL
Figure 23.4.5: Measured phase noise with the division ratio of 53.56. phases, between the presented and conventional architectures.

DIGEST OF TECHNICAL PAPERS • 397

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ISSCC 2009 PAPER CONTINUATIONS

Figure 23.4.7: Die micrograph and performance summary. Phase noise results repre-
sent the worst case of fractional-N performance.

• 2009 IEEE International Solid-State Circuits Conference 978-1-4244-3457-2/09/$25.00 ©2009 IEEE

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