W12 - CT173 - Integer Multiplication and Division
W12 - CT173 - Integer Multiplication and Division
and Division
CT 173
Kiến trúc máy tính
Trường CNTT & TT - ĐHCT
Khoa Mạng máy tính & Truyền thông
Outline
❖ Unsigned Multiplication
❖ Signed Multiplication
❖ Unsigned Division
❖ Signed Division
add
64-bit ALU 2. Shift the Multiplicand Left 1 bit
64 bits
write 3. Shift the Multiplier Right 1 bit
Product Control
64 bits
No
32nd Repetition?
shift right
Multiplier Yes
32 bits Multiplier[0] Done
Multiplication Example (Version 1)
❖ Consider: 11002 × 11012 , Product = 100111002
❖ 4-bit multiplicand and multiplier are used in this example
❖ Multiplicand is zero extended because it is unsigned
Iteration Multiplicand Multiplier Product
0 Initialize 00001100 1101 00000000
Multiplier[0] = 1 => ADD + 00001100
1
SLL Multiplicand and SRL Multiplier 00011000 0110
Multiplier[0] = 0 => Do Nothing 00001100
2
SLL Multiplicand and SRL Multiplier 00110000 0011
Multiplier[0] = 1 => ADD + 00111100
3
SLL Multiplicand and SRL Multiplier 01100000 0001
Multiplier[0] = 1 => ADD + 10011100
4
SLL Multiplicand and SRL Multiplier 11000000 0000
Observation on Version 1 of Multiply
❖ Hardware in version 1 can be optimized
❖ Rather than shifting the multiplicand to the left
Instead, shift the product to the right
Has the same net effect and produces the same results
❖ Reduce Hardware
Multiplicand register can be reduced to 32 bits only
We can also reduce the adder size to 32 bits
HI = HI + Multiplicand
add
32-bit ALU
33 bits
Shift Product = (HI,LO) Right 1 bit
32 bits shift right
carry Shift Multiplier Right 1 bit
HI LO Control
write
64 bits No
shift right 32nd Repetition?
Multiplier Yes
Multiplier[0] Done
32 bits
Refined Version of Multiply Hardware
❖ Eliminate Multiplier Register Start
Multiplicand
32 bits 32 bits HI = HI + Multiplicand
add
32-bit ALU Shift Product = (HI,LO) Right 1 bit
33 bits
❖ Unsigned Multiplication
❖ Signed Multiplication
❖ Unsigned Division
❖ Signed Division
❖ Refined Version:
Use the refined version of the unsigned multiplication hardware
When shifting right, extend the sign of the product
If multiplier is negative, the last step should be a subtract
Signed Multiplication (Pencil & Paper)
❖ Case 1: Positive Multiplier
Multiplicand 11002 = -4
Multiplier × 01012 = +5
Sign-extension 11111100
111100
Product 111011002 = -20
add, sub
33-bit ALU Shift Right Product = (HI, LO) 1 bit
33 bits
❖ Unsigned Multiplication
❖ Signed Multiplication
❖ Unsigned Division
❖ Signed Division
Divisor ≥0 <0
Difference?
64 bits
sub
64-bit ALU 2. Remainder = Difference
sign Set least significant bit of Quotient
Difference
write
Remainder Control
64 bits No
32nd Repetition?
shift left Yes
Quotient Done
32 bits set lsb
Division Example (Version 1)
❖ Consider: 11102 / 00112 (4-bit dividend & divisor)
❖ Quotient = 01002 and Remainder = 00102
❖ 8-bit registers for Remainder and Divisor (8-bit ALU)
Iteration Remainder Divisor Difference Quotient
0 Initialize 00001110 00110000 0000
1: SRL, SLL, Difference 00001110 00011000 11110110 0000
1
2: Diff < 0 => Do Nothing
1: SRL, SLL, Difference 00001110 00001100 00000010 0000
2
2: Rem = Diff, set lsb Quotient 00000010 0001
1: SRL, SLL, Difference 00000010 00000110 11111100 0010
3
2: Diff < 0 => Do Nothing
1: SRL, SLL, Difference 00000010 00000011 11111111 0100
4
2: Diff < 0 => Do Nothing
Observations on Version 1 of Divide
❖ Version 1 of Division hardware can be optimized
❖ Instead of shifting divisor right,
Shift the remainder register left
Has the same net effect and produces the same results
❖ Reduce Hardware:
Divisor register can be reduced to 32 bits (instead of 64 bits)
ALU can be reduced to 32 bits (instead of 64 bits)
Remainder and Quotient registers can be combined
Refined Division Hardware
❖ Observation: Start
Divisor
2. Remainder = Difference
32 bits Set least significant bit of Quotient
sub
32-bit ALU
sign No
Difference 32nd Repetition?
write Yes
Remainder Quotient Control
shift left Done
32 bits 32 bits
set lsb
Division Example (Refined Version)
❖ Same Example: 11102 / 00112 (4-bit dividend & divisor)
❖ Quotient = 01002 and Remainder = 00102
❖ 4-bit registers for Remainder and Divisor (4-bit ALU)
Iteration Remainder Quotient Divisor Difference
0 Initialize 0000 1110 0011
1: SLL, Difference 0001 1100 0011 1110
1
2: Diff < 0 => Do Nothing
1: SLL, Difference 0011 1000 0011 0000
2
2: Rem = Diff, set lsb Quotient 0000 1001
1: SLL, Difference 0001 0010 0011 1110
3
2: Diff < 0 => Do Nothing
1: SLL, Difference 0010 0100 0011 1111
4
2: Diff < 0 => Do Nothing
Next . . .
❖ Unsigned Multiplication
❖ Signed Multiplication
❖ Unsigned Division
❖ Signed Division
❖ Unsigned Multiplication
❖ Signed Multiplication
❖ Unsigned Division
❖ Signed Division