//date : 12 November , 2024; day 1 : Tuesday

//task 1

1. Write the code for half adder with all types of modelling.

//design

//data flow modellling

// module ha(a,b,sum ,carry);

// input a,b;
// output sum , carry;

// assign sum = a^b;

// assign carry = a & b;

// endmodule

//gate level
// module ha(a,b,sum,carry);
// input a,b;
// output sum,carry;

// xor s1(sum,a,b);
// and a1(carry , a,b);
// endmodule

//behavioural modelling

module ha(a,b,sum,carry);
input a,b;
output reg sum,carry;

always@(a,b)
{carry,sum} = a +b;
endmodule

//testbench

module tb;
reg a,b;
wire sum,carry;

ha dut(a,b,sum,carry);
initial begin
a=0;b=0;
#2;
a=0;b=1;
#2;
a=1;b=0;
#2;
a=1;b=1;
#2;
 end

initial begin
$monitor("a=%b, b=%b , sum=%b , carry =%b",a,b,sum,carry);
end
endmodule

2. write the code for 4 bit using structural modelling

// design
module fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum ,cout;

assign sum = a^b^cin;

assign cout = (a & b)|(b&cin)|(a&cin);

endmodule

`include "fulladder.v"

module fulladder4(a,b,cin,sum , cout);

input [3:0]a;
input [3:0]b;
input cin;

output [3:0]sum;
output cout;
wire w1,w2,w3;
fulladder fa1(.a(a[0]) , .b(b[0]) , .cin(cin) , .sum(sum[0]) , .cout(w1));
fulladder fa2(.a(a[1]) , .b(b[1]) , .cin(w1) , .sum(sum[1]) , .cout(w2));
fulladder fa3(.a(a[2]) , .b(b[2]) , .cin(w2) , .sum(sum[2]) , .cout(w3));
fulladder fa4(.a(a[3]) , .b(b[3]) , .cin(w3) , .sum(sum[3]) , .cout(cout));

endmodule

//testbench
module tb;
reg [3:0]a;
reg [3:0]b;
reg cin;

wire [3:0]sum;
wire cout;

integer i;

fulladder4 dut(a,b,cin,sum,cout);

initial begin
for(i=0;i<2**9;i++)
begin
 {a,b,cin} = i;
#2;
end
end

initial begin
$monitor("a=%b,b=%b,cin=%b , sum=%b , cout=%b",a,b,cin,sum,cout);
end
endmodule

3. Write the code for half subtractor

//design
module halfsub(a,b,dif,bor);
input a,b;
output dif,bor;

assign dif = a ^ b;
assign bor = ~a & b;

endmodule

//testbench

module tb;
reg a,b;
wire dif,bor;

integer i;

halfsub dut(a,b,dif,bor);

initial begin
for(i=0;i<4;i++)
begin
{a,b} = i;
#2;
end
end

initial begin
$monitor("a=%b,b=%b,dif =%b,bor=%b",a,b,dif,bor);
end
endmodule

4.write the code for full subtractor using structural modelling

//lower module
module halfsub(a,b,dif,bor);
input a,b;
output dif , bor;

assign dif = a ^ b;
assign bor = ~a & b;

endmodule

//design
`include "halfsub.v"
module fullsub(a,b,cin,dif,bor);
input a,b,cin;
output dif,bor;

wire w1,w2,w3;

halfsub h1(.a(a) , .b(b) , .dif(w1) , .bor(w2));

halfsub h2(.a(w1) , .b(cin) , .dif(dif) , .bor(w3));

or o1(bor,w2,w3);

endmodule

//testbench

module tb;
reg a,b,cin;
wire dif,bor;
integer i;

fullsub dut(a,b,cin,dif,bor);

initial begin
for(i=0;i<8;i++)
begin
{a,b,cin}=i;
#2;

end
end

initial begin
$monitor("a=%b,b=%b,cin=%b,dif=%b,bor=%b",a,b,cin,dif,bor);
end
endmodule

5.write the code for 2 bit comparator

//design
module comparator(a1,a0,b1,b0,g,l,e);
input a1,a0,b1,b0;
output g,l,e;

assign g = (a1 & ~b1& ~b0) |( a1 & ~b1) | (a1 & a0 & ~b0);
assign e =~(a0^b0) & ~(a1 ^ b1);
assign l =( ~a1 & b1) | (~a0 & b1 & b0) | (~a1 & ~a0 & b0);

endmodule

//testbench
module tb;
reg a1,a0,b1,b0;
wire g,l,e;

integer i;

comparator dut(a1,a0,b1,b0,g,l,e);
 initial begin
for(i=0;i<16;i++)
begin

{a1,a0,b1,b0}=i;
#2;
end
end
initial begin
$monitor("a1=%b,a0=%b,b1=%b,b0=%b,g=%b,e=%b,l=%b",a1,a0,b1,b0,g,e,l);
end
endmodule

6.write a code for 4 x 1 mux using 4 different ways

//design

//ist type
/*module mux41(i,s,y);
input [3:0]i;
input [1:0]s;
output reg y;

always@(i,s)
begin

case(s)
2'b00:y = i[0];
2'b01:y = i[1];
2'b10:y = i[2];
2'b11:y = i[3];

default :y= 1'bx;

endcase
end
endmodule*/

//2nd type

/*module mux41(i,s,y);
input [3:0]i;
input [1:0]s;
output reg y;
always@(i,s)
begin
if(s==2'b00)
y=i[0];
else if(s==2'b01)
y=i[1];
else if(s==2'b10)
y=i[2];
else if(s==2'b11)
y=i[3];
else
y=1'bx;
end
endmodule*/
//3rd type
/*module mux41(i,s,y);
input [3:0]i;
input [1:0]s;
output y;

assign y = (s[1]? (s[0] ?i[3] :i[2]) : (s[0] ? i[1] :i[0]));

endmodule*/

//4th type
module mux41(i,s,y);
input [3:0]i;
input [1:0]s;
output y;

assign y = (~s[1] & ~s[0] & i[0]) | (~s[1] & s[0] & i[1]) | (s[1] & ~s[0] & i[2])
| (s[1] & s[0] & i[3]);

endmodule

//testbench
module tb;
reg [3:0]i;
reg [1:0]s;
wire y;

integer a;

mux41 dut(i,s,y);

initial begin
for(a=0;a<2**6;a++)
begin
{i,s} = a;
#1;
end
end
initial begin
$monitor("i=%b , s=%b , y =%b",i,s,y);
end
endmodule

7.write the code for 8 x1 mux using case and if else

//design
module mux81(i,s,y);
input [7:0]i;
input [2:0]s;
output reg y;

//using if else statement

/* always@(i,s)
begin
if(s==3'b000)
y=i[0];
else if(s==3'b001)
 y=i[1];
else if(s==3'b010)
y=i[2];
else if(s==3'b011)
y=i[3];
else if(s==3'b100)
y=i[4];
else if(s==3'b101)
y=i[5];
else if(s==3'b110)
y=i[6];
else if(s==3'b111)
y=i[7];
else
y=1'bx;
end
endmodule*/

always@(i,s)
begin
case(s)
3'b000 : y = i[0];
3'b001 : y = i[1];
3'b010 : y = i[2];
3'b011 : y = i[3];

3'b100 : y = i[4];
3'b101 : y = i[5];
3'b110 : y = i[6];
3'b111 : y = i[7];

default : y=1'bx;

endcase
end
endmodule

//testbench

module tb;
reg [7:0]i;
reg [2:0]s;
wire y;

integer a;

mux81 dut(i,s,y);

initial begin
for(a=0;a<2**11;a++)
begin
{i,s} = a;
#1;
end
end

initial begin
$monitor("i=%b , s=%b , y=%b",i,s,y);
end
endmodule

8. write a code for 1 x 4 demux using 2 different ways

//design
//1st method
module demux(i,s,y);
input i;
input [1:0]s;
output reg [3:0]y;

always@(i,s)
begin
if(s==2'b00)
y= { i,3'b000};
else if(s==2'b01)
y= {1'b0 ,i, 2'b00};
else if(s==2'b10)
y= {2'b00 , i, 1'b0};
else if(s==2'b11)
y= {3'b000 , i};
else
y=4'bxxxx;
end
endmodule

//2nd method
module demux(i,s,y);
input i;
input [1:0]s;
output reg [3:0]y;
always@(i,s)
begin
case(s)
2'b00 : y= { i,3'b000};
2'b01 : y= {1'b0 ,i, 2'b00};
2'b10 : y= {2'b00 , i, 1'b0};
2'b11 : y= {3'b000 , i};

default : y = 4'bxxxx;

endcase
end
endmodule

//testbench
module tb;
reg i;
reg [1:0]s;
wire [3:0]y;

integer a;

demux dut(i,s,y);

initial begin
for(a=0;a<2**3;a++)
begin
 {i,s}=a;
#1;
end
end

initial begin
$monitor("i=%b , s=%b , y=%b",i,s,y);
end
endmodule

9. write the code for 5 x multiple of 3 bit input using behave , data , gate level?

//design
//behave modelling
module multof5(in,out);
input [2:0]in;
output reg [5:0]out;

always@(in)
out = 5*in;
endmodule

//dataflow modelling

module multof5(in,out);
input [2:0]in;
output [5:0]out;

assign out = 5*in;

endmodule

//testbench
module tb;
reg [2:0] in;
wire [5:0] out;
integer i;

multof5 dut(in,out);

initial begin
for(i=0;i<2**3;i++)
begin
{in} = i;
#2;
end
end

initial begin
$monitor("in=%d,out=%d",in,out);
end
endmodule
10. write a code for 1x8 demux using 1x2 demux

//lower module
module demux12(i,s,y);
input i ,s;
output [1:0]y;

assign y[0] = i & ~s;

assign y[1] = i & s;

endmodule

//design
`include "demux12.v"
module demux18(i,s,y);
input i;
input [2:0]s;
output [7:0] y;

wire w1,w2,w3,w4,w5,w6;

demux12 d1(.i(i) , .s(s[0] ), .y({w1,w2}));

demux12 d2(.i(w1) , .s(s[1]) , .y({w3,w4}) );
demux12 d3(.i(w2) , .s(s[1]) , .y({w5,w6}) );
demux12 d4(.i(w3) , .s(s[2]) , .y({y[0],y[1]}) );

demux12 d5(.i(w4) , .s(s[2]) , .y({y[2] ,y[3]}) );

demux12 d6(.i(w5) , .s(s[2]) , .y({y[4],y[5]}) );
demux12 d7(.i(w6) , .s(s[2]) , .y({y[6],y[7]}) );

endmodule

//testbench
module tb;
reg i;
reg [2:0]s;
wire [7:0]y;

integer a;

demux18 dut (i,s,y);

initial begin
for(a=0;a<2**4;a++)
begin
{i,s}=a;
#1;
end
end

initial begin
$monitor("i=%b, s=%b , y=%b",i,s,y);
end
endmodule
//date 14 November 2024 day thrusday

11. write the code for priority encoder & mention the advantages & priority encoder

//design
module p_enc(i,y,v);
input [3:0]i;
output reg [1:0]y;
output reg v;
assign y[1] = i[3]|i[2];

assign y[0] = i[3] | ( ~(i[2]) & i[1]);

assign v = i[3]+i[2]+i[1]+i[0];

endmodule

//testbench
module tb;
reg [3:0]i;
wire [1:0]y;
wire v;
p_enc dut(i,y,v);

initial begin

{i}= 4'b0000;
#1;
{i}= 4'b0001;
#1;
{i}= 4'b0010;
#1;
{i}= 4'b0100;
#1;
{i}= 4'b1000;
#1;
end
initial begin
$monitor("i=%b,y=%b,v=%b",i,y,v);
end
endmodule

12. write the code for gray to binary converter

//design
module btg(b,g);
input [2:0]b;
output reg [2:0]g;

always@(b)
begin
g[2] = b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
end
endmodule

//testbench
module tb;
reg [2:0]b;
wire [2:0]g;

integer i;

btg dut( b,g);

initial begin
for(i = 0; i<8 ; i++)
begin
{b} = i;
#5;
end
end

initial begin
$monitor(" b = %b , g = %b ",b,g);

end
endmodule

13. write the code for prime no. generator

//design

module prime(a,b,c,y);

input a,b,c;
output y;

assign y = (a && c) || ((~a) && b);

endmodule

//testbench

module tb;

reg a,b,c;
wire y;

prime dut (a,b,c,y);

initial begin

a=0; b=0; c=0;

#5
a=0; b=0; c=1;
#5
a=0; b=1; c=0;
#5
a=0; b=1; c=1;
#5
a=1; b=0; c=0;
#5
a=1; b=0; c=1;
#5
a=1; b=1; c=0;
 #5
a=1; b=1; c=1;

end

initial begin

$monitor("sim time =%t , a = %b , b= %b , c=%b , y =%b" , $time ,a,b,c,y);

end

initial begin

$dumpfile("dump.vcd");
$dumpvars(0,a,b,c,y);

end
endmodule

14. write the code for even no. generator

//design
module even(num,even);
input [7:0]num;
output reg even;

always@(num)
begin
if(num%2==0)
even = 1;
else
even=0;
end
endmodule

//testbench

module tb;
reg [7:0] num;
wire even;

even dut(num,even);

initial begin

$monitor("num=%d , even=%b",num,even);

num=10;
#2;
num=7;
#2;
num=13;
#2;

end
endmodule
15. write the code to count no. of zeroes from 16 bit

//design

module count_bits(vec,zeros);

parameter N=16;
input [N-1:0]vec;
output reg [N-1:0] zeros;
integer i;

always@(vec)
begin
zeros=0;

for(i=0;i<N;i++)
begin
case(vec[i])

1'b0:zeros= zeros+1;

default:;//do nothing
endcase
end
end
endmodule

//testbench

module tb;
reg [15:0]vec;
wire [15:0] zeros;

count_bits dut(vec,zeros);

initial begin
$monitor("vec=%b,zeros=%D",vec,zeros);

vec = 16'b1010xxxx_101x1111;
#10;
vec = 16'b1100zzzz_111000xx;
#10;
vec = 16'b11110000_00011xxx;
#10;
end
endmodule