Lab 1 / M1: Individual LED Kria FPGA

Author: Hammond Pearce, 2024

Overview
Every student will receive a baseline FPGA project package consisting of:
● Pre-flashed Petalinux image with configured software and example bitstreams on SD card
● Kria KV260 and power supply, ethernet cable, USB cable
● UNSW CSE Design Project A/B PMOD board
● Adafruit I2S MEMS microphone (not used in this lab)

This guide describes the steps for students to program the KV260 board with some custom
hardware. Students are required to go through this tutorial. The diagram below is an overview of
the steps of development for the Kria platform. In this guide, we will be using Ubuntu Linux as
our OS running on the host machine. You can also use Windows.

The above diagram presents the overview of programming the Kria KV260 FPGA - it is a
relatively involved process! But for this simple LED we will just focus on activating FPGA
designs, then on generating the .bit file and programming the board over USB.
Prerequisites
The software you should have installed before starting:
● Vitis Vivado 2021.1
o During installation, you need to choose to install the full Vitis package as it will
be needed later in this course.
● If Ubuntu: minicom, if Windows: Putty

Part 1: Activating existing hardware

The KV260 is made of two systems: a PS (Processor System) which has got a quad-core ARM
processor running PetaLinux, and a PL (Programmable Logic) which is an FPGA fabric where
you can deploy custom hardware.

In the first part of this tutorial you will learn about and connect to the PetaLinux installation
which is on your Kria KV260.

Set up the LED hardware

1. Take the Design Project A/B PMOD board:
 2. Insert it into the PMOD connector of the KV260.

Power up
1. Ensure your SD card is plugged in. This contains the PetaLinux boot files.

2. Connect the USB cable to the FPGA and to your computer.

3. Connect the power cable to the FPGA and to the power. This will start the FPGA up. It
should look like something this, with all your setup done:
Open your serial port:

Ubuntu instructions:

After power up when connected to the Ubuntu PC via USB, the KV260 is usually connected to
/dev/ttyUSB1.

Open minicom with:

minicom -D /dev/ttyUSB1 -b 115200 -8 -s

Use the arrow keys to go to “Serial port setup”, then press enter, then press “F” to turn Hardware
Flow Control to No

Then press “Escape” and press “Escape” again. The serial should now be opened. If instead an
error message shows up, ask a tutor for help on opening the connection to the board.
If it works, you should see something like this:

Windows instructions:
Open PuTTY and go to the terminal settings.
Enable Implicit CR in every LF
Implicit LF in every CR

Now click on Serial, and set it up as follows:

Now click on Session, and choose Serial

Now press “Open”, you should get a serial window:

BOTH UBUNTU AND WINDOWS: If there is no text in your window, likely the board has
booted in the time it takes for you to open your serial connection. However, you can check this
by pressing the “Reset” button on the board.
This should then result in the boot text appearing in the serial terminal. Wait until you see the
root@petalinux prompt. (I.e. let it autoboot). This should take approximately 30-60 seconds.

IF NO TEXT APPEARS, YOU PROBABLY NEED TO FIND YOUR SERIAL PORT.

/dev/ttyUSB1 and COM12 seem to be the defaults, but they can change. If you don’t know how
to do this, ask your tutor.

Note there is often a long delay between the last OF message and the “Starting tcf-agent:” OK.

This terminal is the root login for PetaLinux running on the PS. Try out some linux commands:

That listed all the directories in the root folder.

In the PetaLinux image baked into the SD card, there are some FPGA designs already created
that can be downloaded from the PS to the PL.

1. Run xmutil listapps to list out the available hardware (your list may differ)
root@xilinx-k26-starterkit-2021_1:~# xmutil listapps
Graph-server: new client
Accelerator Base Type #slots Active_slot

comp3601-led-blink3 comp3601-led-blink3 XRT_FLAT 1 -1

comp3601-i2s-axi comp3601-i2s-axi XRT_FLAT 1 -1
kv260-dp kv260-dp XRT_FLAT 1 0,
Socket 9 closed by client
root@xilinx-k26-starterkit-2021_1:~#

2. Unload the loaded (empty) PL logic by running xmutil unloadapp

root@xilinx-k26-starterkit-2021_1:~# xmutil unloadapp
Graph-server: new client
DFX-MGRD> REMOVE_ACCEL: removing accel at slot 0
DFX-MGRD> Removing accel kv260-dp from slot 0

Accelerator succesfully removed.

Socket 9 closed by client
root@xilinx-k26-starterkit-2021_1:~#

3. Load the default COMP3601 “blink 3 times” LED project with xmutil loadapp
comp3601-led-blink3

root@xilinx-k26-starterkit-2021_1:~# xmutil loadapp comp3601-

led-blink3
Graph-server: new client
DFX-MGRD> LOAD_ACCEL: loading accel comp3601-led-blink3

DFX-MGRD> Successfully loaded base design.

Accelerator loaded to slot

Socket 6 closed by client
root@xilinx-k26-starterkit-2021_1:~#

4. This should make the LED blink 3 times and then pause on the extra PMOD board that you
plugged in.

5. Unload the LED blinking hardware again with xmutil unloadapp

6. The hardware should stop blinking. You’re ready to progress to the next part of this lab!
Part 2: Making custom hardware
In this part of the lab you will explore designing basic custom logic and programming it to the
PL FPGA fabric of the Kria KV260.

Hardware Project Setup

Creating a new project in Vivado

1. Open Vivado. Click on Create Project and click Next.

2. Set Project name and Project location and click Next.

3. Select RTL Project. We will add the sources later so tick Do not specify sources at this
time. Click Next.
 4. In the Default Part section, click on the Boards tab and type "kv" in the search bar.
Select Kria KV260 Vision AI Starter Kit and click Next.

5. Click Finish to create your project.

Make sure the Project part shows Kria KV260 Vision AI Starter Kit.

Adding constraints to the project

1. Download the constraints file kria-constraints.xdc from teams.

2. In the Project Manager, click on + in the Sources window.
3. Add the constraint file for the Kria board into the project by choosing Add or create
constraints in Add sources.

4. Click Add Files and Navigate to the kria-constraints.xdc file. Click Finish when done.
Adding a hardware file to the project

5. In the Project Manager, click on + in the Sources window.

6. Press Add or create design sources and click Next.

7. Select Create File and call it something sensible.

8. Select OK and then Finish.

9. When the Define Module window pops up, you can add an input called ‘clk_10MHz’ and
an output called ‘led_out’.
10. This will now create a VHDL file with the following skeleton.

11. Finish the module using VHDL by implementing a clock divider/counter such that the
led_out will toggle every 1 second. (I.e., the LED will blink on/off with a period of 2
seconds).
1. You can search the internet for tutorial code to help you achieve this, but by the
end of this exercise you must be able to write this code using your own
knowledge. The Tutor will assess you on the functionality of your code so you
must be able to explain how it works.
(Optional) Add testbenches to the project

We provide you with a testbench file led_blinka_TB.vhd to simulate the behaviour of your
code. You could also write your own simulation testbench, but this will not be assessed in this
lab. Consult with your Tutor if you’d like to learn more about testbenches.

1. In the Project Manager, click on + in the Sources window.

2. Select Add or create simulation sources.

3. Click on Add Files and navigate to the testbench file.

4. Click on Finish. Note that the provided testbench file assumes students have the same
number of entity inputs/outputs, and port names as mentioned in the previous steps.
5. In the Flow Navigator, right click on Run Simulation to select Simulation Settings.

6. Set the Simulation top module name as led_blinka_TB.vhd or your own testbench file.
After applying the settings, you will expect to see the testbench file name bold under
Simulation Sources.

7. Click on Run Simulation in the Flow Navigator. Observe the behaviour of signals in your
design. The waveform should look something like this, if you let it run for 5 seconds.

8. You are now ready to proceed.

Creating a block design for Kria

Since the Kria KV260 has a processor system (PS) in conjunction with the FPGA programmable
logic (PL), we must also combine the PS with the PL in our design.
So, we need to add the Zynq MPSoC device and configure it for our hardware. To do this, we
will be using the IP INTEGRATOR tool.

1. In the Flow Navigator tab, click on Create Block Design under IP INTEGRATOR.

2. Click OK when prompted.

3. An empty Diagram should show up. Click on + and search for “zynq”. Double click on
Zynq UltraScale+ MPSoC to add the IP into your block design.

4. Click on Run Block Automation and click OK which will apply the Kria AI Starter Kit
preset to the Zynq device.
5. Right-click on the diagram and select Add Module.

6. Select your new LED module and click OK.

7. Right-click on the diagram and select Create Port. Add the following ports:
1. pmod_led_d1; Output; Other

8. Click on + to add another IP and search for “clocking wizard”. Double click to add the IP
to your block design.

9. Double click on the clocking wizard IP and navigate to the Output Clocks tab.
1. Set the clk_out1 clock to a requested 10MHz frequency.
2. Scroll down and under Enable Optional Inputs / Outputs for MMCM/PLL untick
the reset and locked ports.
3. Click OK to finish the configuration.
10. At this point your diagram should look something like this (block locations may vary):
11. Connect the ports of the clock output to the clock wizard input, and the clock wizard
output to the input of your LED module.

12. Double click on the Zync UltraSCALE+ block and go to PS-PL Configuration, then PS-
PL Interfaces > Master Interface and de-select the AXI HMP0 FPD and AXI HPM1
FPD.
13. Your design should now look like this:

14. Validate the block design by clicking on the ticked-box icon.

15. Under the Sources tab, right-click on the design_1.bd block design and click Create HDL
Wrapper. Select Let Vivado manage wrapper and auto-update and click OK.
 16. Right-click on the design_1_wrapper and click on Set as Top. Now the
design_1_wrapper should be bold and on the top in Design Sources.

Building the project

1. In the Flow Navigator window, click on Run Synthesis and launch the synthesis tasks.
2. Once the synthesis has been completed, click on Run Implementation to run
implementation tasks.
3. Once the implementation has been completed, click on Generate Bitstream to generate
the bitstream files.

Downloading the project over USB

4. Go to the Hardware Manager and select Open target, then Autoconnect.

5. It will show you the following targets:

6. Right click on xck26_0 and select Program Device. It should automatically navigate to
the .bit file you generated earlier.
 7. Your LED should start blinking! (Ask your Tutor for help if it doesn’t)

Stop - time to talk to the Tutor and get

individual sign off
This has to be done as Milestone 1 of the course, due week 2, and is individually assessed. Talk
the Tutor through your design, and the Tutor will ask questions to gauge your understanding.
The assessment includes the following aspects:

● Students can show using xmutil loadapp and unloadapp to activate/deactivate the blink3
demo hardware.
● Students can download their own custom hardware to the FPGA using Xilinx Vivado.
And the custom HW has LED blinking at required rate.
● Students explain their design to Tutor (how did you design it, process of writing the code
and how the code works, how the programming of the FPGA works).
● Answer questions from Tutor.