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CS3351- DIGITAL PRINCIPLES AND

COMPUTER ORGANIZATION LAB

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SEMESTER - III
REGULATION-
2021

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Vision and Mission - Institute

Vision
To carve the youth as dynamic competent, valued and knowledgeable Technocrats
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throughresearch, innovation and entrepreneurial development for accomplishing the global

expectations.

Mission
M1: Inculcate academic excellence in engineering education to create talented
professionals M2: Promote research in basic sciences and applied engineering among
faculty and
students tofulfill the societal expectations.
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M3: Holistic development of students through meaningful interaction with industry

and academia.
M4: Foster the students on par with sustainable development goals thereby contributing
to theprocess of nation building
M5: To nurture and retain conducive lifelong learning environment towards
professional excellence

Vision and Mission - Department of Electronics and Communication Engineering

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VI SEMESTER

Vision
To develop highly competent engineers in the field of Electronics and Communication
Engineering to meet the global standards in education, research and innovation with
professional ethics
Mission
M1: Provide quality education to the students in core and allied fields by implementing
advanced pedagogies.
M2: Create ardor among faculty as well as students to achieve excellence in emerging
research areas
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M3: Imbibe industry relevant skills to the students through industry interaction thereby
bridging the campus to corporate gap.
M4: To endow the students with broad intellectual spectra pertaining to the sustainable
evelopment goals.
M5: To instill the thirst of lifelong learning among students to excel in their field of
interest

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VI SEMESTER

Program Educational Objectives (PEO's)

The graduate of Electronics and Communication engineering will have

PEO1: To provide knowledge in mathematical, scientific and engineering concepts to
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achieve successful career path in corporate scenario.

PEO2: To enable students with the capability to analyze, design, develop, optimizeand
to implement electronic gadgets with domain knowledge of Electronics and
Communication Engineering
PEO3: To nurture and consolidate the knowledge in various domains that affords solutions
for real time problems with an understanding on its economical, environmental
and social impacts.
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PEO4: To inculcate core knowledge with ethical values to work in a multi-fascinated

environment exhibiting professionalism in career and to excel in every aspect
with leadership
PEO5: To imbibe persistent lifelong learning with amenable etiquette in emerging technologies
to proliferate their skills for professional excellence and in research and innovations

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VI SEMESTER

Program Outcomes (PO`s)

The students after successful completion of the program will acquire:

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VI SEMESTER

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and electronics and communication engineering to solve complex
problems.
PO2: Problem analysis: Identify, formulate, review research literature and analyze complex
problems in electronics and communication engineering domain to reach substantiated
conclusions using principles of mathematics, natural sciences and engineering sciences.
PO3: Design/development of solutions: Develop solutions for composite problems in
Electronics and Communication engineering and design system components or processes
that meet the specified needs with appropriate consideration for the public health and
safety, cultural, societal, and environmental considerations.
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VI SEMESTER

PO4: Investigation: Use research-based knowledge & methods of Electronics and

Communication, including design of experiments, analysis and interpretation of data, and
synthesis of information to provide valid conclusions.
PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
PO6: The Engineer and society: Apply reasoning informed by the contextual knowledge of
Electronics and Communication to assess societal, health, safety, legal and cultural issues
and consequent responsibilities relevant to the professional engineering practice.
PO7: Environment and sustainability: Understand the impact of the professional engineering
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VI SEMESTER

solutions in societal and environmental contexts and demonstrate theknowledge, and need
for sustainable development.
PO8: Ethics: Ability to have ethical principles, responsibilities and norms of the engineering
practice.
PO9: Individual and team work: The professional must visualize and function effectively as
an individual and as member or leader in diverse teams and in multidisciplinary settings.
PO10: Communications: Communicate effectively on complex engineering activities with
engineering community and able to comprehend effective reports, design documentation,
make effective presentations and give clear instructions.
PO11: Project management and finance: Demonstrate engineering knowledge and
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VI SEMESTER

understanding of management principles and apply these to manage projects in

multidisciplinary environments.
PO12: Life-long learning: Develop interest towards continuous education throughout their life.

Program specific outcome (PSO's)

PSO1 : Design and develop Electronic circuits assimilating Futuristic technologies of Signal Processing,
Communication, VLSI and Embedded Systems using Modern Hardware and software tools to cater the
expectation of solving real time problems.

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 TRICHY - 17
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DEPARTMENT OF ARTIFICIAL INTELLIGENCE AND DATA SCIENCE

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VI SEMESTER

PSO2: Instill the professional skill sets with ethical principles and tools for Networking, Communication
and integrated circuits to provide Solutions for societal benefits.

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 TRICHY - 18
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VI SEMESTER

Course Code / Course Name CS3351- Digital Principles and Computer

Organization Lab
Semester III

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VI SEMESTER

Regulation 2021

Course Code Course Outcome

Students will be able to

CS3351.1 Design various combinational digital circuits using logic gates

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CS3351.2 Design sequential circuits and analyze the design procedures

CS3351.3 State the fundamentals of computer systems and analyze the execution of an
instruction
CS3351.4 Analyze different types of control design and identify hazards

CS3351.5 Identify the characteristics of various memory systems and I/O communication

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VI SEMESTER

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Code
CS3351.1 3 2 3 2 3 0 0 0 2 2 2 2

CS3351.2 1 1 3 2 3 0 0 0 2 2 2 2

CS3351.3 1 2 3 3 3 0 0 0 2 2 2 2

CS3351.4 1 2 3 3 3 0 0 0 2 2 2 2

CS3351.5 3 2 3 3 3 0 0 0 2 2 2 2
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VI SEMESTER

CS3351 3 2 3 3 3 0 0 0 2 2 2 2

Course Code PSO1 PSO2

CS3351.1 1 1
CS3351.2 2 1
CS3351.3 2 1
CS3351.4 3 1
CS3351.5 3 1

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VI SEMESTER

CS3351 3 1

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VI SEMESTER

CS3351- Digital Principles and Computer Organization Lab

LIST OF EXPERIMENTS: TOTAL: 30 PERIODS LTPC

0 011
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DEPARTMENT OF ARTIFICIAL INTELLIGENCE AND DATA SCIENCE

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VI SEMESTER

1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates for arbitrary functions.

3. Implementation of 4-bit binary adder/subtractor circuits.

4. Implementation of code converters.

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VI SEMESTER

5. Implementation of BCD adder, encoder and decoder circuits

6. Implementation of functions using Multiplexers.

7. Implementation of the synchronous counters

8. Implementation of a Universal Shift register.

9. Simulator based study of Computer Architecture

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VI SEMESTER

INDEX

EXPT. PAGE
NAME OF THE EXPERIMENT
NO NO
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DEPARTMENT OF ARTIFICIAL INTELLIGENCE AND DATA SCIENCE

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VI SEMESTER

Study of Logic Gates

1. Verification of Boolean theorems using logic gates.

Design and implementation of combinational circuits using gates for

2. arbitrary functions.
Design and implementation of 4 bit binary Adder/
3. Subtractor Implementation of BCD adder using IC 7483

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VI SEMESTER

Design and implementation of code converters using logicgates

4.
i. Binary to gray and vice versa
ii. BCD to Excess-3 code and vice versa.

5. Implementation of Encoder and decoder

i. Study Multiplexer and De-Multiplexer

6. ii. Implementation of functions using Multiplexer

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VI SEMESTER

Implementation of the synchronous counters

i. Construction and verification of 4-bit ripple counter
7.
ii. Mod-10 / Mod-12 Ripple counters
i. Implementation of a Universal Shift register.
ii. Implementation SISO, SIPO, PISO and PIPO shiftregisters
8.
using Flip-flops
-
Simulator based study of Computer Architecture
9.

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VI SEMESTER

Content beyond Syllabus

10. Design and implementation of magnitude comparator

11.
Design and implementation of parity generator / checker using
basic gates
12. Implementation 3-bit synchronous up/downcounter

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VI SEMESTER

STUDY OF LOGIC GATES

AIM:
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VI SEMESTER

To study about logic gates and verify their truth tables.

LEARNING OBJECTIVE:

 Identify various ICs and their specification

 a. OR gate b. AND gate c. NAND gate d. NOR gate
 e. NOT gate f. Ex-OR gate

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VI SEMESTER

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

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VI SEMESTER

1. 2- I/P AND gate IC 7408 1

2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. 2- I/P NAND gate IC7400 1
5. NOR gate IC7402 1
6. EX-OR gate IC7486 1
7. IC Trainer - 1
8. Kit Patch - Few
cords

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THOERY:

Logic gates are the basic elements that make up a digital system. The gate is a digital
circuit with one or more inputs, but only one output. By connecting the different gates in
different ways, we can build circuits that perform arithmetic and other functions.
The operation of a logic gate can be easily understood with the help of “truth table”.
A truth table is a table that shows all the input-output possibilities of a logic circuit ie., the
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VI SEMESTER

truth table indicates the outputs for different possibilities of the inputs.
The types of gates available are the AND, OR, NOT, NAND, NOR, exclusive-OR
and the exclusive-NOR. Except for the exclusive-NOR gate they are available in monolithic
integrated form.

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AND gate:
The AND gates has two or more inputs. It performs a logical multiplication. The
output is HIGH (1), when both the inputs are 1; otherwise the output from the gate is LOW
(0). The output from the AND gate is written as A.B.
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OR gate:
The OR gates has two or more inputs. It performs a logical addition. The output is
HIGH (1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0.
The output from the AND gate is written as A+B.

NOT gate:
The NOT gate has only one input. It performs a basic logic function called
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inversion. The output is HIGH (1), when the input is 0; the output is LOW (0) when the
input is 1. The output from the NOT gate is written as A’.

NAND gate:
The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output
is HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs
are 1. The output from the AND gate is written as (A.B)’. It is a universal gate.

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NOR gate:
The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is
HIGH (1), when all inputs are 0; the output is LOW (0), when any of the inputs are 1. The
output from the AND gate is written as (A+B)’. It is a universal gate.

EX-OR gate:
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The EX-OR gate has two or more inputs. The output is HIGH (1), when odd number
of inputs is 1. The output from the AND gate is written as (AB).

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AND gate:

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OR gate:

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NOT gate:

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2- Input NAND gate:

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NOR gate:

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EX-OR gate:

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PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
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4. Provide the input data via the input switches and observe the output on output LEDs

RESULT:

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EX.NO :1 VERIFICATION OF BOOLEAN THEOREMS USING

DATE: LOGIC GATES

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1.1 AIM: To Verify Boolean Theorems using Logic Gates

1.2 LEARNING OBJECTIVE:

 To simplify the Boolean expression and to build the logic circuit.

 Given a Truth table to derive the Boolean expressions and build the logic circuit to realize it.

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1.3 APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

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1. 2- I/P AND gate IC 7408 1

2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. 2- I/P NAND gate IC7400 1
5. NOR gate IC7402 1
6. EX-OR gate IC7486 1
7. IC Trainer - 1
8. Kit Patch - Few
cords

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1.4 BOOLEAN THEOREMS

1. Commutative Law

The binary operator OR, AND is said to be commutative if,

1. A+B = B+A
2. A.B=B.A

2. Associative Law
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The binary operator OR, AND is said to be associative if,

1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

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3. Distributive Law

The binary operator OR, AND is said to be distributive if,

1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
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1. A+AB = A
2. A+AB =A+B

5. Idempotent Law

1. A+A = A
2. A.A = A

6. Complementary

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Law 1. A+A' =
1
2. A.A' = 0
7. De Morgan’s Theorem

The complement of the sum is equal to the sum of the product of the individual
complements

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A+B = A . B

The complement of the product is equal to the sum of the individual complements.

A.B = A + B
Logic Circuit :

1. Commutative Law

A+B = B+A
L.H.S R.H.S
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Truth Table:

Inputs Output Inputs Output

A B F=A+B B A F=B+A

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ii A.B=B.A
L.H.S R.H.S

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Truth Table:

Inputs Output Inputs Output

A B F=A.B B A F=B.A

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2. Associative Law

i) A+(B+C) = (A+B)+C
L.H.S R.H.S

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Inputs Output
Inputs Output
A B C (A+B) F=(A+B)+C
A B C (B+C) F=A+(B+C)

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ii) A.(B.C) = (A.B).C

L.H.S R.H.S

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Inputs Output Inputs Output

A B C (B.C) F=A.(B.C) A B C (B.C) F=A.(B.C)

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3. Distributive Law

i) A+(B.C) = (A+B).(A+C)

L.H.S R.H.S

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Inputs
Output
A B C (B.C) F=A+(B.C)

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Inputs Output
A B C (A+B) (A+C) F=(A+B).(A+C)

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ii)A.(B+C) = (A.B)+(A.C)

L.H.S R.H.S

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Inputs Output Inputs Output

A B C (B+C) F=A.(B+C) A B C (A.B) (A.C) F=(A.B)+(A.C)
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4. Absorption Law

i)A+AB = A ii)A.A+B = AB
L.H.S L.H.S

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Inputs LHS- Output RHS Inputs LHS- Output RHS

A B A.B F=A+A.B F=A A B A+B F=A.A+B F=AB

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5. Idempotent Law

i)A+A = A ii)A.A = A

Input Output Input Output

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6. Complementary Law

1. A+A' = 1 2. A.A' = 0

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Input Output Input Output

A A’ F=A+A’ A A’ F=A.A’

7. De Morgan’s Theorem

i)A’+B’ = (A . B)’ ii) A’. B’ = (A +B)’

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Inputs LHS- Output RHS Inputs LHS- Output RHS

A B A’ B’ F=A’+B’ F=(A.B)’ A B A’ B’ F=A’.B’ F=(A+B)

1.5 PROCEDURE:
1. Check the components for their working.
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2. Insert the appropriate IC into the IC base.

3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs

1.6 RESULT:

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EX.NO :2
DATE:
DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUI
ARBITRARY FUNCTIONS

2.1 AIM: To Implement a Boolean function using NAND & NOR gates
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2.2 LEARNING OBJECTIVE:

 To realize why NAND gate is known as the universal gate by implementation of :
a. NOT using NAND b. AND using NAND c. OR using NAND d. XOR using NAND
 To simplify the given Boolean expressions and build the logic circuit to realize it

2.3 APPARATUS REQUIRED:

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SL.NO COMPONENTS SPECIFICATION QUANTITY

1. 2- I/P AND gate IC 7408 1
2. OR gate IC 7432 1
3. NOT gate IC 7404 1
4. 2- I/P NAND gate IC7400 1
5. NOR gate IC7402 1
6. EX-OR gate IC7486 1
7. IC Trainer - 1
8. Kit Patch - Few
cords
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2.4. IMPLEMENTATION
Implement the Boolean function by using a logic gate.
F=∑(0,1,2,5,7)
Design :
Step: 1 Obtain Truth Table

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Step: 2 Simplify using K map

Step: 3 Design a Logic circuit using basic gates.

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Truth Table

Inputs Output
A B C F
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3- Variable k-map

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F=

Design a Logic circuit

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2.5 PROCEDURE:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
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 Provide the input data via the input switches and observe the output on output LEDs
 Verify the Truth Table

2.6 RESULT:

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3.1 AIM:
To Design and implement the 4-bit adder/ subtractor and BCD adder using IC 7483.

3.2 LEARNING OBJECTIVE:

 To realize the 4-bit adder/ subtractor using IC 7483.

 To design BCD adder using IC 7483 and verify its truth table

3.3 APPARATUS REQUIRED:

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SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 4-bit binary full adder IC 7483 1
3. EX-OR gate IC 7486 1
4. AND gate IC 7408 1
5. OR gate IC 7432 1
6. Patch cords - Few

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3.4 THEORY:

4- Bit binary adder/ subtractor:

The 4-bit binary adder/ subtractor circuit performs the operation of both addition and
subtraction. It has two 4-bit inputs A0, A1, A2, A3 and B0, B1, B2, B3. The mode input M
controls the operation of the circuit. When M= 0, the circuit is an adder and when M=1, the
circuit becomes a Subtractor. Each exclusive-OR gate receives input M and one of the inputs
of B.
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When M=0, the operation is B 0= B. The full adders receive the value of B and the
input carry is 0, and the circuit performs the addition operation, A+ B.
When M=1, the operation is B 1= B‟ and C0=1. The B inputs are all complemented
and a 1 is added through the input carry. Thus the circuit performs the subtraction operation,
i.e., A+ (2‟s complement of B) = A- B.

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3.5 IMPLEMENTATION

2- BIT BINARY ADDER/ SUBTRACTOR:

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PIN DIAGRAM:

LOGIC DIAGRAM FOR BINARY ADDER

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LOGIC DIAGRAM FOR BINARY SUBTRACTOR

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TRUTH TABLE:

Input data A Input data B Addition Subtraction

A3 A2 A1 A0 B3 B2 B1 B0 C S3 S2 S1 S0 B D3 D2 D1 D0
1 0 0 0 0 0 1 0
1 0 0 0 1 0 0 0
0 0 1 0 1 0 0 0
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0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 1
1 1 1 0 1 1 1 1
1 0 1 0 1 1 0 1

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BCD ADDER:

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LOGIC DIAGRAM:
4- Bit BCD Adder:
The digital system handles the decimal number in the form of binary coded decimal
numbers (BCD). A BCD adder is a circuit that adds two BCD bits and produces a sum digit
also in BCD.
In examining the contents of the table, it is apparent that when the binary sum is equal
to or less than (1001)2, the corresponding BCD number is identical, and therefore no
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conversion is needed. When the binary sum is greater than 9 (1001) 2, we obtain a non-valid
BCD representation. The addition of binary 6 (0110) 2 to the binary sum converts it to the
correct BCD representation and also produces an output carry as required.
The logic circuit to detect sum greater than 9 can be determined by simplifying the
Boolean expression of the given truth table.
The two decimal digits, together with the input carry, are first added in the top 4-bit
binary adder to provide the binary sum. When the output carry is equal to zero, nothing is
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added to the binary sum. When it is equal to one, binary (0110)2 is added to the binary sum
through the bottom 4-bit adder. The output carry generated from the bottom adder can be
ignored, since it supplies information already available at the output carry terminal. The
output carry from one stage must be connected to the input carry of the next higher-order
stage.

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TRUTH TABLE

Binary sum BCD sum Decimal

K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0
0 0 0 0 1
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0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
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0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
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1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1

3.7 PROCEDURE:

1. Connections are given as per the logic diagram.

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2. Logic inputs are given as per the truth table.

3. Observe the logic output and verify with the truth tables.

3.8 RESULT:

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EX.NO : 4
DATE:
IMPLEMENTATION OF CODE CONVERTORS

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4.1 AIM:
To design and implement 4-bit
1. Binary to Gray code Converter
2. Gray to Binary code Converter
3. BCD to Excess-3 code Converter
4. Excess-3 code to BCD Converter

4.2 LEARNING OBJECTIVE:

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 To learn the importance of non-weighted code Converter

 To learn to generate gray code & Excess-3 code Converter

4.3 APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. EX-OR gate IC7486 1
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3. NOT gate IC7404 1

4. OR gate IC7432 1
5. 2-Input AND gate IC7408 1
6. 3-Input AND gate IC7411 1
7. Patch cords - As Required

4.4 THEORY:
An availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
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between the two systems if each uses different codes for the same information. Thus, code
converter is a circuit that makes the two systems compatible even though each uses different
binary code.
The input variable are designed as B 3,B2,B1,B0 and the output variables are designed as
G3,G2,G1,G0. From the truth table, combinational circuit is designed. The Boolean functions are
obtained from K-Map for each output variable.

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4.5 IMPLEMENTATION
BINARY TO GRAY CODE CONVERTER:
TRUTH TABLE:

Binary code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

K- Map Simplification:

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Logic Diagram:

GRAY TO BINARY CODE CONVERTER:

TRUTH TABLE:

Gray code Binary code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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K-Map Simplification:

Logic Diagram:

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BCD TO EXCESS-3 CODE:

Truth table:
BCD code Excess-3 code
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1

K-Map Simplification:

UJJ

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Logic Diagram:

To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate the corresponding
bit combination of code. Each one of the four maps represents one of the four outputs of the
circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit.

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EXCESS-3 TO BCD CONVERTER:

Truth Table:
Excess-3 code BCD code
E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0

K-Map Simplification:

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Logic Diagram:

4.6 PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

4.7 RESULT:

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EX.NO : 5
DATE:
IMPLEMENTATION OF ENCODER AND DECODER

5.1 AIM:
To design and implementation encoder and decoder

5.2 LEARNING OBJECTIVE:

 To design and implement encoder and decoder using logic gates

 To study of encoder and decoder using IC7445 and IC 74147.

5.3 APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3-I/P NAND IC7410 2
3. gate NOT gate IC7404 1
4. OR gate IC7432 3
5. Encoder and IC7445 1
6. Decoder IC 74147. 1
7. Patch cords - Few

5.4 THEORY:
Encoder:
An encoder is a digital circuit that performs inverse operation of a decoder. An
encoder has 2n input lines and „n‟ output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight inputs,
one for each octal digit and three output that generates the corresponding binary code. In
encoder it is assumed that only one input has a value of one at any given time otherwise the
circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero.
The zero outputs can also be generated when D0=1.

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Decoder:
A decoder is a multiple output logic circuit which converts input into coded output
where input and output codes are different. The input code generally has few bits than the
output code. Each input code word produces a different output code word i.e., there is one to
one mapping can be expressed in truth table. In block diagram of decoder circuit the encoded
information is present as n input producing 2 n possible outputs. The 2n output values are from
0 through out 2n-1.

5.5 IMPLEMENTATION
Logic Diagram ( 2-to-4- Line Decoder with Enable Input):

Truth Table:

INPUTS OUTPUTS
E A B D3 D1 D2 D3
1 x x
0 0 0
0 0 1
0 1 0
0 1 1

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ENCODER:
Logic Diagram:

Truth Table:

INPUTS OUTPUTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0
0 1 0 0 0 0 0
0 0 1 0 0 0 0
0 0 0 1 0 0 0
0 0 0 0 1 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1

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Pin diagram of 7445

No Inputs Outputs
D C B A 0 1 2 3 4 5 6 7 8 9
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
Invali
d

1 1 0 1
1 1 1 0
1 1 1 1

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Pin diagram of 74147

Truth Table 74147

Inputs Outputs BCD Negative

logic
1 2 3 4 5 6 7 8 9 Q0 Q1 Q2 Q3
1 1 1 1 1 1 1 1 1
X X X X X X X X 0
X X X X X X X 0 1
X X X X X X 0 1 1
X X X X X 0 1 1 1
X X X X 0 1 1 1 1
X X X 0 1 1 1 1 1
X X 0 1 1 1 1 1 1
X 0 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1

5.6 PROCEDURE:
1.Connections are given as per the logic diagram.
2.Logic inputs are given as per the truth table.
3.Observe the logic output and verify with the truth tables.

5.8 RESULT:

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EX.NO : 6
DATE:
IMPLEMENTATION OF FUNCTIONS USING
MULTIPLEXER

6.1 AIM:
To design and implement functions using multiplexer

6.2 LEARNING OBJECTIVE:

 To learn multiplexer and demultiplexer using logic gates

 To learn and understand the working of IC 74153 and IC 74139
 To learn to realize any function using Multiplexer IC74150
6.3 APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. NAND GATE IC7411 2
3. NOT GATE IC7404 1
4. OR GATE IC7432 1
5. Multiplexer IC74150 1
Patch cords - Few

6.4 THEORY:
Multiplexer:
Multiplexer means transmitting a large number of information units over a small
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are
2n input line and „n‟ selection lines whose bit combination determine which input is selected.
It is called as data selector, because the output depends on the input data bit that is selected.

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Demultiplexer:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. Decoder can also be used as
Demultiplexer.

In the 1:4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

6.5 IMPLEMENTATIO
N MULTIPLEXER:
BLOCK DIAGRAM:

Function table:

S1 S0 Inputs Output
0 0 D0 S1’ S0’ D0
0 1 D1 S1’ S0 D1
1 0 D2 S1 S0’ D2
1 1 D3 S1 S0 D3

Output, Y= D0 S1’S0’ +D1 S1’S0+ D2 S1S0’ +D3 S1S0

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Logic Diagram:

Truth table:

Inputs Output
S1 S0 D0 D1 D2 D3 Y
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 0 1 0 0
1 0 0 0 0 0
1 0 0 0 1 0
1 1 0 0 0 0
1 1 0 0 0 1

1: 4 DEMULTIPLEXER:
Block Diagram

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Function Table:

S1 S0 Inputs Output
0 0 X S1’ S0’ D0
0 1 X S1’ S0 D1
1 0 X S1 S0’ D2
1 1 X S1 S0 D3

Output, Y= XS1’S0’ +XS1’S0+ XS1S0’ +XS1S0

Logic Diagram:

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Truth Table:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Implement the Boolean expression F(A, B, C) = ∑ m(2, 3, 6, 7) using a multiplexer.

Solution:

There are 3 variables in the given expression, hence 2n = 23 = 8 : 1 multiplexer. So, the mux has 8
input lines, 3 selection lines, and one output.

The inputs, corresponding to the minterms (2, 3, 6, 7) are connected to logic 1 and the remaining
terms to logic 0(grounded). The given input variables are connected as three selection lines.

Pin diagram: 74150-Mux 1

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Inputs Output
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

6.6 PROCEDURE:
 Connections are given as per the logic diagram.
 Logic inputs are given as per the truth table.
 Observe the logic output and verify with the truth tables.

6.7 RESULT:

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EX.NO : 7
DATE:
IMPLEMENTATION OF SYNCHRONOUS COUNTER

7.1 AIM:

To construct and verify 4 bit ripple counter, MOD-10 and MOD-12 ripple counter.

7.2 LEARNING OBJECTIVE:

 To learn the importance of 4 bit ripple counter

 To design 4 bit ripple counter, MOD-10 and MOD-12 ripple counter

7.3 APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer - 1
2. kit JK Flip- IC7476/7473 2
3. flop NAND IC7400 1
4. gate Patch - Few
cords

7.4 THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulse arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous, first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q‟ output of pervious stage.
A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-
flop drives the clock input of the following flip-flop. The number of flip-flops in the cascaded
arrangement depends upon the number of different logic states that it goes through before it
repeats the sequence, a parameter known as the modulus of the counter.

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In a ripple counter, also called an asynchronous counter or a serial counter, the clock
input is applied only to the first flip-flop, also called the input flip-flop, in the cascaded
arrangement. The clock input to any subsequent flip-flop comes from the output of its
immediately preceding flip-flop. For instance, the output of the first flip-flop acts as the clock
input to the second flip-flop, the output of the second flip-flop feeds the clock input of the
third flip-flop and so on.

7.5 IMPLEMENTATION

4- BIT RIPPLE COUNTER:

PIN DIAGRAM: (JK Flip-Flop)

Function Table for 7476:

Inputs Outputs
Preset Clear Clock J K Q Q’
0 1 X X X 1 0
1 0 X X X 0 1
0 0 X X X 1 1
1 1 0 0 No Change
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Toggle

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LOGIC DIAGRAM: (4-Bit Ripple Counter)

TRUTH TABLE:

CLK QA QB QC QD

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

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A four-bit ripple counter is implemented with negative edge-triggered J-K flip-flops

wired as toggle flip-flops. The output of the first flip-flop feeds the clock input of the second,
and the output of the second flip-flop feeds the clock input of the third, the output of which in
turn feeds the clock input of the fourth flip-flop. The outputs of the four flip-flops are
designated as Q0 (LSB flip-flop), Q1, Q2 and Q3 (MSB flip-flop).

LOGIC DIAGRAM: (MOD-10 Ripple Counter)

TRUTH TABLE:

CLK QA QB QC QD

0
1
2
3
4
5
6
7
8
9
10

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LOGIC DIAGRAM: (MOD-12 Ripple Counter)

TRUTH TABLE:

CLK QA QB QC QD
0
1
2
3
4
5
6
7
8
9
10
11
12

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Pin diagram of 7473

Logic Diagram

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Up/down counter

Control Outputs
inputs Control Outputs
Up / inputs
CLK QA QB QC QD
Down CLK Up / QA QB QC QD
0 Initial state Down
17 1
1 0
18 1
2 0
19 1
3 0
20 1
4 0
21 1
5 0
22 1
6 0
23 1
7 0
24 1
8 0
25 1
9 0
26 1
10 0
27 1
11 0
28 1
12 0
29 1
13 0
30 1
14 0
31 1
15 0
32 1
16 0

7.6 PROCEDURE:
1. Connections are given as per the logic diagram.
2.Logic inputs are given as per the logic diagram.
3.Observe the logic output and verify with the truth tables.

7.7 RESULT:

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EX.NO : 8
DATE:
IMPLEMENTATION OF SHIFT REGISTER

8.1 AIM:

To design and implement

 Serial in serial Out(SISO)
 Serial in parallel Out(SIPO)
 Parallel in serial Out(PISO)
 Parallel in parallel Out(PIPO)

8.2 LEARNING OBJECTIVE:

 To learn the importance of shift register

 To design and implement universal shift register

8.3 APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. D-Flip flop IC7474 2
3. AND gate IC7408 1
4. OR gate IC7432 1
5. NOT gate IC7404 1
6. Patch cords - Few

8.4 THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. A logical configuration of shift register consist of a D flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.

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SHIFT REGISTER:
PIN DIAGRAM: (D-Flip-Flop)

Function Table:

Inputs Outputs
Preset Clear Clock D Q Q’
0 1 X X 1 0
1 0 X X 0 1
0 0 X X 1 1
1 1 0 0 1
1 1 1 1 0
1 1 0 X No Change

SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:

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TRUTH TABLE:
CLK Serial IN Serial OUT
1 1
2 1
3 1
4 1
5 0
6 0
7 0
8 0

Serial IN Parallel OUT:

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA
Q3 Q2 Q1 Q0
1 1
2 0
3 0
4 1

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Parallel IN Serial OUT:

LOGIC DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUT
S/ L’ CLK
A B C D Q
0 0 1 0 0 1
1 1 1 0 0 1
1 2 1 0 0 1
1 3 1 0 0 1

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Parallel IN Parallel OUT:

Logic Diagram:
TRUTH TABLE:

DATA INPUTS OUTPUT

CLK
D3 D2 D1 D0 Q3 Q2 Q1 Q0
1 1 0 0 1
2 1 0 1 0

8.6 PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

8.7 RESULT

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EX.NO : 10
DATE:
DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR

AIM:
To design and implement
(i) 2-bit magnitude comparator using logic gates.
(ii) 8-bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit -
2. EX-OR gate IC7486 1
3. NOT gate IC7404 1
4. OR gate IC7432 1
5. AND gate IC7408 1
6. 4-bit Magnitude
Comparator IC 7485 2
7. Connecting Wires - Few

THEORY:

A magnitude comparator is a combinational circuit that compares two given numbers

(A and B) and determines whether one is equal to, less than or greater than the other. The
output is in the form of three binary variables representing the conditions A = B, A>B and
A<B, if A and B are the two numbers being compared.
The two binary numbers A and B with two digits each, written in descending order as,
A = A1A0
B = B1 B0
Each subscripted letter represents one of the digits in the number. It is observed from the bit
contents of two numbers that A = B, when A 1 = B1 and A0 = B0. When the numbers are
binary they possess the value of either 1 or 0, the equality relation of each pair can be
expressed logically by the equivalence function as,
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3-BIT MAGNITUDE COMPARATOR:

TRUTH TABLE:

Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

DESIGN:

A = A1A0
B = B1 B0
Xi = AiBi + Ai′Bi′
Xi = (Ai  Bi)′ for i = 0,1
(A = B) = X1 X0
(A>B) = A1B1′ +X1A0B0′
(A<B) = A1′B1 +X1A0′B0

Xi = AiBi + Ai′Bi for i = 1, 2, 3, 4.

Or, ′ Xi = (A  B)′ or, Xi ′ = A  B

Or, Xi = (AiBi′ + Ai′Bi)′

where
,

Xi =1 only if the pair of bits in position i are equal

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To satisfy the equality condition of two numbers A and B, it is necessary that all
Xi must be equal to logic 1. This indicates the AND operation of all Xi variables. In other
words, we can write the Boolean expression for two equal 2-bit numbers.
(A = B) = X1 X0.
The binary variable (A=B) is equal to 1 only if all pairs of digits of the two numbers are
equal.

LOGIC DIAGRAM:

2-bit Magnitude Comparator:

To determine if A is greater than or less than B, we inspect the relative magnitudes of

pairs of significant bits starting from the most significant bit. If the two digits of the most
significant position are equal, the next significant pair of digits is compared. The comparison
process is continued until a pair of unequal digits is found. It may be concluded that A>B, if
the corresponding digit of A is 1 and B is 0. If the corresponding digit of A is 0 and B is 1,
we conclude that A<B. Therefore, we can derive the logical expression of such sequential
comparison by the following two Boolean functions,
CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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(A>B) = A1B1′ +X1A0B0′

(A<B) = A1′B1 +X1A0′B0

The symbols (A>B) and (A<B) are binary output variables that are equal to 1 when A>B or
A<B, respectively.

8- BIT MAGNITUDE COMPARATOR:

Truth Table:

A B A>B A=B A<B

0000 0000 0000 0000
0001 0001 0000 0000
0000 0000 0001 0001

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables.

RESULT:

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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EX.NO : 11
DATE:
DESIGN AND IMPLEMENTATION OF 16-BIT
ODD/EVEN PARITY GENERATOR AND CHECKER

AIM:
To design and implement 16 bit odd /even parity checker generator using IC 74180.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. NOT gate IC7404 1
3. 8-bit parity generator/
checker IC74180 2
4. Patch cords - Few

THEORY:
A Parity is a very useful tool in information processing in digital computers to
indicate any presence of error in binary information. External noise and loss of signal
strength causes loss of data bit information while transporting data from one device to other
device, located inside the computer or externally. To indicate any occurrence of error, an
extra bit is included with the message according to the total number of 1s in a set of data,
which is called parity.
If the extra bit is considered 0 if the total number of 1s is even and 1 for odd
quantities of 1s in a set of data, then it is called even parity. On the other hand, if the extra bit
is 1 for even quantities of 1s and 0 for an odd number of 1s, then it is called odd parity.
The message including the parity is transmitted and then checked at the receiving end
for errors. An error is detected if the checked parity does not correspond with the one
transmitted. The circuit that generates the parity bit in the transmitter is called a parity
generator and the circuit that checks the parity in the receiver is called a parity checker.

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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8- Bit ODD/EVEN PARITY GENERATOR/ CHECKER:

PIN DIAGRAM:

FUNCTION TABLE:

INPUTS OUTPUTS
Number of Data Inputs
(D0 - D7) PE PO ∑E ∑O
EVEN 1 0
ODD 1 0
EVEN 0 1
ODD 0 1
X 1 1
X 0 0

16- Bit ODD/EVEN PARITY GENERATOR:

LOGIC DIAGRAM:

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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TRUTH TABLE:

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 PE PO ∑E ∑O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

16- Bit ODD/EVEN PARITY CHECKER:

LOGIC DIAGRAM:

TRUTH TABLE:

D7 D6 D5 D4 D3 D2 D1 D0 D7‟ D6‟ D5‟ D4‟ D3‟ D2‟ D1‟D0‟ PE PO ∑E ∑O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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The parity checker circuit produces a check bit and is very similar to the parity
generator circuit. If the check bit is 1, then it is assumed that the received data is incorrect.
The check bit will be 0 if the received data is correct. The table shows the truth table for the
even parity checker.
In even parity, the added parity bit will make the total number 1‟s even amount. In
odd parity, the added parity bit will make the total number 1‟s odd amount. The parity
checker circuit checks for possible errors in the transmission. If the information is passed in
even parity, the bits required must have an even number of 1‟s. An error occur during
transmission, if the received bits have an odd number of 1‟s indicating that one bit has
changed in value during transmission.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Logic inputs are given as per the truth table.
3. Observe the logic output and verify with the truth tables

RESULT:

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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EX.NO : 12
DATE:
DESIGN AND IMPLEMENTATION OF 3-BIT
SYNCHRONOUS COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter using JK flip-flop.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer - 1
2. kit JK Flip- IC7476 2
3. flop IC7411 1
4. 3-I/P NAND IC7404 1
5. gate NOT gate IC7432 1
6. OR gate IC7486 1
7. EX-OR gate Few
Patch Cords

THEORY:
A Counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that
is capable of progressing in increasing order or decreasing order through a certain sequence.
An up/down counter is also called bi-directional counter. Usually up/down operation of the
counter is controlled by up/down signal. When this signal high counter goes through up
sequence and when up/down signal is low counter follows reverse sequence.
The counter counts upwards when UP control are logic „1‟ and DOWN control is
logic „0‟. In this case the clock input of each flip-flop other than the LSB flip-flop is fed from
the normal output of the immediately preceding flip-flop. The counter counts downwards
when the UP controls input are logic „0‟ and DOWN control is logic „1‟. In this case, the
clock input of each flip-flop other than the LSB flip-flop is fed from the complemented
output of the immediately preceding flip-flop.

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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3- BIT SYNCHRONOUS UP/DOWN COUNTER:

STATE DIAGRAM:

TRUTH TABLE:

Input Present State Next State A B C

Up/Down’ QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 x 1 x 1 x
0 1 1 1 1 1 0 x 0 x 0 x 1
0 1 1 0 1 0 1 x 0 x 1 1 x
0 1 0 1 1 0 0 x 0 0 x x 1
0 1 0 0 0 1 1 x 1 1 x 1 x
0 0 1 1 0 1 0 0 x x 0 x 1
0 0 1 0 0 0 1 0 x x 1 1 x
0 0 0 1 0 0 0 0 x 0 x x 1
1 0 0 0 0 0 1 0 x 0 x 1 x
1 0 0 1 0 1 0 0 x 1 x x 1
1 0 1 0 0 1 1 0 x x 0 1 x
1 0 1 1 1 0 0 1 x x 1 x 1
1 1 0 0 1 0 1 x 0 0 x 1 x
1 1 0 1 1 1 0 x 0 1 x x 1
1 1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 1 0 0 0 x 1 x 1 x 1

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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EXCITATION TABLE: (JK Flip-Flop)

Q Q t+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

K-MAP SIMPLIFICATION:

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /
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LOGIC DIAGRAM:

PROCEDURE:

1. Connections are given as per the logic diagram.

2. Logic inputs are given as per the logic diagram.
3. Observe the logic output and verify with the truth tables.

RESULT

CS3351- Digital Principles and Computer Organization Lab / III SEM / AI&DS /