EEE 213

Introduction to Logic Design

Assist. Prof. Dr. Şenol GÜLGÖNÜL
2023-2024 Fall Semester
 ABOUT
• Text Book: Digital Design, Global Edition
Mano, M. Morris, Ciletti, Michael

• Grades: 20% Midterm + 40% Project + 40% Final

• Course Objectives: Boolean Algebra, implementation

using Logic Gates

• Additional Resource:
• senolgulgonul/introductiontologic: Introduction to
Logic Design Lecture Files (github.com)
• Logic Simulator (hneemann/Digital: A digital logic
designer and circuit simulator. (github.com))
• Tinkercad (https://www.tinkercad.com/)
WHY
• Electronics
• Analog: RLC, Transistors, Amplifiers, Filters, Electromagnetic, Antenna etc.
• Digital: Logic Gates, Logic IC’s, Microcontrollers, FPGA etc.
 Week Subject

SYLLABUS 1
2
Boolean Algebra and Logic Gates
Gate Level Minimization
3 Combinational Logic
4 Combinational Logic
5 Combinational Logic
6 Midterm
7 Sequential Logic
8 Sequential Logic
9 Registers Counter
10 Registers Counter
11 Memory and Programmable Logic
12 Microcontroller Architecture
13 Microcontroller Architecture
14 Final
15 Final
16
HISTORY OF LOGIC
• ‘Logic’ originates from Greek word ‘logos’, means ‘reason’

• Logic is a feature of being alive and decision making

• Most advanced form of logical reasoning is in humans (as far as we

know! excluding ChatGPT☺)

• Aristoteles can be named as the father of logic, who set rules of

logical thinking
AISTOTELES (384–322 BC)
His followers compiled the logical works of Aristotle into a
collection of six books known as the 'Organon' around 40
BC.

1. Categories
2. On Interpretation
3. Prior Analytics
4. Posterior Analytics
5. Topics
6. On Sophistical Refutations
EXAMPLES OF ARISTOTELES LOGIC
Aristotle’s central observation was to check validity of arguments based on their logical
structure. Aristotle, in his work "Sophistical Refutations," aimed to expose and
demonstrate the invalidity of various fallacies used by sophists.

• An object is what it is (Law of Identity)

• No statement can be both true and false (Law of Non-contradiction)
• Every statement is either true or false (Law of the Excluded Middle)
• Categorical Syllogism:
All humans are mortal. Socrates is a human. Therefore, Socrates is mortal.
GEORGE BOOLE (1815-1864)
The Organon, occupied a central place in the scholarly canon for
more than 2,000 years. It was widely believed that Aristotle had
written almost all there was to say on the topic. The great
philosopher Immanuel Kant commented that, since Aristotle, logic
had been “unable to take a single step forward, and therefore seems
to all appearance to be finished and complete.”

George Boole’s, "An Investigation of the Laws of Thought," published

in 1854, laid the foundation for symbolic logic. Boole’s goal was to do
free for Aristotelean logic from the limits of human intuition by
giving it a precise algebraic notation.
BOOLEAN ALGEBRA-SHANNON
Boolean algebra in ‘Laws of Thought’ defined for classes (sets), converts words to symbols.
‘All men are mortal’ can be converted as:
y=y.x
where y=‘men’, x=‘mortal’

Claude Shannon introduced the use of Boolean algebra in the analysis and design of
switching circuits in 1936 (Master Thesis).
SHANON APPLICATION OF BOOLEAN ALGEBRA
Open=1, Close=0 : X.Y

Any expression formed with the operations of addition,

multiplication, and negation represents explicitly a circuit
containing only series and parallel connections.

Open=1, Close=0 : X + Y
Cahit ARF: Can a machine think?
• Using only relays Boolean
algebra can be implemented
completely

• Turkish mathematician Cahit Arf

discusses if a machine can think
at a paper dated 1959 and show
AND, OR, NOT gates using relays
LOGIC OPERATORS to LOGIC GATES
Invention of the transistor in 1947 by William Shockley and his colleagues at Bell Labs. dramatically
improved versions of Shannon’s electrical relays—the best known way to physically encode Boolean
operations
DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number

/2
/2
/2
/2
/2
/2
DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• divide to 2 till 1 or 0, write remainders in REVERSE order
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
BINARY to DECIMAL
• While converting from binary to decimal: multiply and add binary value of bit and decimal value of
the bit position

32 16 8 4 2 1 2^x
1 0 1 0 0 1 Binary
32 0 8 0 0 1 =41
LOGIC GATES to COMPUTERS
While Claude Shannon showed how to map logic onto the physical world, Alan Turing showed how
to design computers in the language of mathematical logic. In 1945, he wrote the specification of the
EDVAC—the first stored program, logic-based computer—which is generally considered the
definitive source guide for modern computer design.
Two-Valued Boolean Algebra
One can formulate many Boolean algebras, depending on the choice of elements of
B and the rules of operation. In our subsequent work, we deal only with a two-valued
Boolean algebra (i.e., a Boolean algebra with only two elements).

A two-valued Boolean algebra is defined on a set of two elements, B = {0, 1}

two binary operators + and . as shown in the following operator tables (the rule
for the complement operator is for verification of postulate 5)

AND OR NOT
Huntington Postulates
Huntington introduced a set of postulates known as "Huntington's Postulates" that describe the
fundamental properties of Boolean algebra in 1904. These postulates provide a basis for
manipulating logical expressions and establishing the laws of Boolean algebra

Huntington postulates are valid for the set B = {0, 1} and the two binary operators + and .
Huntington Postulates
1. That the structure is CLOSED with respect to the two operators is obvious from the
tables, since the result of each operation is either 1 or 0 and 1, 0 ∈ B.

2. (a) The element 0 is an identity element with respect to +; that is, x + 0 =0 + x = x

(b) The element 1 is an identity element with respect to . ; that is, x . 1 = 1 . x = x

3. (a) The structure is commutative with respect to +; that is, x + y = y + x

(b) The structure is commutative with respect to . ; that is, x . y = y . x

4. (a) The operator . is distributive over +; that is, x . (y + z) = (x . y) + (x . z)

(b) The operator + is distributive over . ; that is, x + (y . z) = (x + y) . (x + z)

5. For every element x ∈ B, there exists an element x′ ∈ B called the complement of x such that
(a) x + x′ = 1
(b) x . x′ = 0

6. There exist at least two elements x, y ∈ B such that x ≠ y, x=1, y=0 and 1 ≠0
 Huntington Postulates
• Table 2.1 lists six theorems of Boolean algebra and four of its postulates.
• The notation is simplified by omitting ‘.’
• The theorems and postulates listed are the most basic relationships in Boolean algebra.
• The theorems, like the postulates, are listed in pairs; each relation is the dual of the one paired with it.
• The postulates are basic axioms of the algebraic structure and need no proof.
• The theorems must be proven from the postulates.
 Postulates and Theorems of Boolean Algebra
The theorems of Boolean algebra can be proven by means of
truth tables

• THEOREM 1(a): x + x = x
• THEOREM 1(b): x . x = x

• THEOREM 2(a): x + 1 = 1
• THEOREM 2(b): x . 0 = 0

• THEOREM 3: (x′)′ = x (involution)

• THEOREM 5(a): (x + y)’ = x’y’ (DeMorgan)

• THEOREM 5(b): (x y)’ = x’+y’

• THEOREM 6(a): x + xy = x (absorption)

• THEOREM 6(b): x(x + y) = x
Operator Precedence

The operator precedence for evaluating Boolean expressions is:

(1) Parentheses: (x+y)’.x+y

(2) Complement: (x+y)’.x+y
(3) AND: (x+y)’.x+y
(4) OR: (x+y)’.x+y
Algebraic Expression to Truth Table
• A truth table is a table of all possible combinations of the variables, showing the relation
between the values that the variables may take and the result of the operation
Algebraic Expression to Truth Table
• A truth table is a table of all possible combinations of the variables, showing the relation
between the values that the variables may take and the result of the operation
Algebraic Expression to Boolean Functions
A Boolean function described by an algebraic expression consists of binary variables, the
constants 0 and 1, and the logic operation symbols. For a given value of the binary variables,
the function can be equal to either 1 or 0.

As an example, consider the Boolean function

F1 = x + y′z

F2 = x′y′z + x′yz + xy′

Implementation of Boolean Functions
• Boolean functions can be realized using logic gates
• Logic gates are electronic circuits that operate on one or more physical input signals to
produce an output signal.
Function to Logic Diagrams
Boolean function can be transformed from an algebraic expression into a circuit diagram
composed of logic gates connected in a particular structure.
FUNCTION to LOGIC Gates
Given F=xz+x’y
Variables
a) implement using, AND,OR,NOT Gates
x z y
• Draw variables and their complements VERTICALLY

• Connect variables to Gates according to boolean expression Gates

• First create xz using AND

• second create x’y using AND
• connect to outputs to OR
Truth Table to Algebraic Expression (Minterms)
• A Boolean function can be expressed algebraically from a given truth table by forming a minterm for each
combination of the variables that produces a 1 in the function and then taking the OR of all those terms.

• Given the truth table of F1, Find logical expression of F1

• Minterms are combination of variables (x,y,z..etc.) and their ‘complements’ with AND operator
• Answer: Find minterms=1 (F1=1) and OR them SO EASY!!
F1=x’y’z + xy’z’ +xyz

X’ i called as :
• X’s complement,
• X prime
• not X
Truth Table to Algebraic Expression (Minterms)
• Given the truth table of F2, Find logical expression of F2

• Answer: Find minterms=1 (F2=1) and OR them SO EASY!!

F2=x’yz + xy’z +xyz’ + xyz
Truth Table to Algebraic Expression (Maxterms)
• Given the truth table of F2, Find logical expression of F2
• Maxterms= combination of variables by OR
• Answer: Find maxterms=0 (F2=0), AND them all
F2=(x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
Truth Table to Algebraic Expression (summary)
• Boolean functions expressed as a sum of minterms or product of maxterms
are said to be in canonical form

• We will prefer sum of minterms in this lecture

• F1=x’y’z + xy’z’ + xyz

DESIGN GUIDE

1. What is the requirement: Description of function

2. Create using Truth Table

3. Write logical expression using Truth Table

4. Implement logical expression using AND, OR, NOT gates

5. Minimize number of gates

 Truth Table to Algebraic Expression: TwoOne
• Create logic circuit with 3 input and gives 1 if two or more 1’s

F = x’yz + xy’z + xyz’ + xyz

x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Truth Table to Algebraic Expression (catch odd)
• design a logic which catches odd decimal numbers (1,3,5,7), 3-bit input

F=x’y’z + x’yz + xy’z + xyz

Dec x y z F
0 0 0 0 0
1 0 0 1 1
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1
ANALOG to DIGITAL Converters (ADC)

• ADC convert continuous analog signals into discrete digital values

• Example 0-5V range with 8bit (=255) resolution
• 5V/255=0.02V resolution
 Design Example
• 3 bit ADC, 0-5V Volt x y z F
0.0 0 0 0 0
• if analog volt is above 3V F=1
0.7 0 0 1 0
otherwise F=0 1.4 0 1 0 0
2.1 0 1 1 0
2.8 1 0 0 0
• resolution 3bit=7, 5V/7=0.7V 3.5 1 0 1 1
4.2 1 1 0 1

• above 3V, 3.5, 4.2, 5.0 volts 5.0 1 1 1 1

F=xy’z + xyz’ + xyz

• we are loosing some analog
information due to resolution
 Design Example
• 3 bit ADC, 0-5V
• if analog volt is above 3V F=1 otherwise F=0
• resolution 3bit=8, 5V/8=0.6V
• above 3V means 3bit is above 5=101

x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0 F=xy’z + xyz’ + xyz
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
 2.7. Other Logical Operations
• We are not limited to AND OR NOT Gates, other Gates are also may help to reduce
number of gates
• Let us evaluate all possible truth table combinations of two variable functions

• AND, OR, NOT

• NAND, NOR
• XOR, XNOR
2.7. Logic Gates
2.7. Logic Gates (multiple input)
3. Gate Level Minimization
• Gate-level minimization is the design task of finding an optimal gate-level implementation of the
Boolean functions describing a digital circuit.

• This task is well understood, but is difficult to execute by manual methods when the logic has more
than a few inputs.

• Fortunately, this dilemma has been solved by computer-based logic synthesis tools that minimize a
large set of Boolean equations efficiently and quickly.

• Nevertheless, it is important that a designer understands the underlying mathematical description

and solution of the gatelevel minimization problem.
 Huntington Postulates
• Table 2.1 lists six theorems of Boolean algebra and four of its postulates.
• The notation is simplified by omitting ‘.’
• The theorems and postulates listed are the most basic relationships in Boolean algebra.
• The theorems, like the postulates, are listed in pairs; each relation is the dual of the one paired with it.
• The postulates are basic axioms of the algebraic structure and need no proof.
• The theorems must be proven from the postulates.
Algebraic Manipulation
 Minimization of Number of Gates
Finding the most economic representation of the logic is an important
design task. By reducing the number of terms, the number of literals,
or both in a Boolean expression, it is often possible to obtain a simpler
circuit. The manipulation of Boolean algebra consists mostly of
reducing an expression for the purpose of obtaining a simpler circuit
Algebraic Manipulation (Shannon Paper)
 Algebraic Manipulation
• To reach minimum number of Gates using algebraic manipulation using analytical methods is not
an easy way

• Thus we need to find a better way (Karnaugh Map)

Karnaugh Map
• Boolean expressions may be simplified by algebraic means as discussed in Section 2.4. However,
this procedure of minimization is awkward, because it lacks specific rules to predict each
succeeding step in the manipulative process.
• The map method presented in this section provides a simple, straightforward procedure for
minimizing Boolean functions. This method may be regarded as a pictorial form of a truth table. The
map method is also known as the Karnaugh map or K-map method presented in 1954 by Maurice
Karnaugh (1924-2022)
 Truth Table to Karnaugh Map
• Karnaugh Map is more compact form of representation of truth table
• F=xy’z’ + xy’z + xyz’ + xyz has four terms
• find the location of terms on Karnaugh map and set to 1
• adjacent cells can be combined to a shorter common term
• F=x

x y z F F=xy’z’ + xy’z + xyz’ + xyz

0 0 0 0
0 0 1 0 y’ y
0 1 0 0 x’
0 1 1 0 x 1 1 1 1
1 0 0 1 z’ z z’
1 0 1 1
1 1 0 1
1 1 1 1
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES

y’ y y’ y
x’ x’ 1 1 1 1
x 1 1 1 1 x
z’ z z’ z’ z z’

• F1=x • F2=x’
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES

y’ y
y’ y
x’ 1 1
x’ 1 1
x 1 1
x 1 1
z’ z z’
z’ z z’

• F1=y • F2=y’
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES

y’ y y’ y

x’ 1 1 x’ 1 1

x 1 1 x 1 1

z’ z z’ z’ z z’

• F1=z • F2=z’
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES

y’ y y’ y
x’ 1 1 x’
x x 1 1
z’ z z’ z’ z z’

• F1=x’y’ • F2=xy
Three Variable Karnaugh Map
• FIND THE COMMON VARIABLE(S) OF ADJACENT SQUARES

y’ y y’ y
x’ 1 x’ 1
x 1 x 1
z’ z z’ z’ z z’

• F1=y’z’ • F2=y’z
Three Variable Karnaugh Map
• Simplify the Boolean function F =x’yz’ + x’yz + xy’z’ + xy’z
• Focus on only 1’s

• FIND ADJACENT SQUARES

x y z F • Any two adjacent squares in the map differ by only one variable
• Find the common variable of adjacent cell
0 0 0
• intersect with x
0 0 1
F= x’yz’+x’yz+xy’z’+xy’z
0 1 0 1
0 1 1 1 y’ y
1 0 0 1 x’ 1 1
1 0 1 1 x 1 1 F=xy’+x’y
1 1 0 z’ z z’
1 1 1
Three Variable Karnaugh Map
• Consider, for example, the truth table that defines the function F in Table 3.1. In sum-of-minterms
form, this function is expressed as F = x’z + xz’
Three Variable Karnaugh Map

x y z F
F = x’y’z’ + x’yz’ + xy’z’ + xy’z +xyz’
0 0 0 1
0 0 1
0 1 0 1 y’ y
0 1 1 x’ 1 1
1 0 0 1 x 1 1 1 F = z’ + xy’
1 0 1 1 z’ z z’
1 1 0 1
1 1 1
Three Variable Karnaugh Map

if expression is given we dont need to create to the truth table we can fill Karnaugh Map

F = x’z + x’y + xy’z +yz

y’ y
x’ 1 1 1
x 1 1
F = z + x’y
z’ z z’
Karnaugh Map (above 3V)

x y z F F = xy’z + xyz’ + xyz

0 0 0 0
0 0 1 0 y’ y
0 1 0 0 x’
0 1 1 0 x 1 1 1 F = xz + xy
1 0 0 0 z’ z z’
1 0 1 1
1 1 0 1
1 1 1 1
Karnaugh Map (catch odd)
• design a logic which catches odd decimal numbers (1,3,5,7), 3-bit input

x y z F F=x’y’z + x’yz + xy’z + xyz

0 0 0 0
0 0 1 1
y’ y
0 1 0 0
x’ 1 1
0 1 1 1 F=z
x 1 1
1 0 0 0
z’ z z’
1 0 1 1
1 1 0 0
1 1 1 1
Karnaugh Map: TwoOne
• Create logic circuit with 3 input and gives 1 if two or more 1’s

x y z F
0 0 0 0
0 0 1 0
F = x’yz + xy’z + xyz’ + xyz
0 1 0 0 y’ y
0 1 1 1 x’ 1
1 0 0 0 x 1 1 1
F = yz + xz + xy
1 0 1 1 z’ z z’
1 1 0 1
1 1 1 1
Dont Care Conditions
• In practice, in some applications the function is not specified for certain combinations of the
variables
• These don’t-care conditions can be used on a map to provide further simplification of the Boolean
expression. So you can assume 1 or 0 as you like for further simplification
• Consider following example

x y z F
F =x’y’z’ + x’y’z + x’yz’ +x’yz + xy’z’ + xy’z
0 0 0 X=1
0 0 1 X=1
y’ y
0 1 0 1 if X=0 F=xy’+x’y but if Xdontcare=1 we
x’ X X 1 1
0 1 1 1 can further sımplify to
x 1 1
1 0 0 1
z’ z z’ F=y’+x’y
1 0 1 1
1 1 0 0
1 1 1 0
Four Variable Karnaugh Map
• Maps for more than three variables are difficult to use and will not be considered in the lecture.
NAND Gate
• The NAND gate is said to be a universal gate because any logic circuit can be implemented with it.
To show that any Boolean function can be implemented with NAND gates, we need only to show
that the logical operations of AND, OR, and complement can be obtained with NAND gates alone
NAND Gate: Implementation
• The implementation of two-level Boolean
functions with NAND gates requires that
the functions be in sum-of-products form
• F=AB + CD

• The function it implements can easily be

converted to sum-of-products form by
DeMorgan’s theorem:
• F = ((AB)′(CD)′)′ = AB + CD
 XOR Function

Exclusive-OR functions are very useful in systems requiring

error detection and correction codes. As discussed in Section
1.7, a parity bit is used for the purpose of detecting
errors during the transmission of binary information. A parity
bit is an extra bit included with a binary message to make the
number of 1’s either odd or even.
 XOR Function: Parity Generation and Checking
• Exclusive-OR functions are very useful in systems
requiring error detection and correction codes.
• A parity bit is an extra bit included with a binary
message to make the number of 1’s either odd or even.
• The message, including the parity bit, is transmitted and
then checked at the receiving end for errors.

• make P=0 or 1 to have EVEN number of 1’s

RS-232 settings 8N1= 8 data, No parity, 1 stop

8E1: 8bit, Even Parity, 1 stop
 XOR Function: Parity Generation and Checking

The three bits in the message, together with the parity bit,
are transmitted to their destination, where they are
applied to a parity-checker circuit to check for possible
errors in the transmission. Since the information was
transmitted with even parity, the four bits received must
have an even number of 1’s. An error occurs during the
transmission if the four bits received have an odd number
of 1’s, indicating that one bit has changed in value during
transmission

C=1 means ERROR

Buffer / Three State Buffer
• buffer produces the transfer function, but does not produce a logic operation, since the binary value of the
output is equal to the binary value of the input. This circuit is used for power amplification of the signal and is
equivalent to two inverters connected in cascade.
• three-state buffer gate is shown in Fig. 4.29. It is distinguished from a normal buffer by an input control line
entering the bottom of the symbol. The buffer has a normal input, an output, and a control input that
determines the state of the output. When the control input is equal to 1, the output is enabled and the gate
behaves like a conventional buffer, with the output equal to the normal input. When the control input is 0, the
output is disabled and the gate goes to a high-impedance state, regardless of the value in the normal input.
this is important for BUS connections. listener has to go high impedance not to disturb others
Logic Simulator ( GitHub - hneemann/Digital: A digital logic designer and circuit simulator. )
Digital is an easy-to-use digital logic designer and circuit simulator designed for educational
purposes.
Logic Simulator-Manual
if Boolean expression is given circuit can be implemented using components and connections
Logic Simulator-Synthesis
We can create the circuit automatically using logical Expression
Careful about the syntax : *=AND, +=OR , !=NOT
Remember the circuit for above 3V: F=xy’z + xyz’ + xyz
x*!y*z + x*y*!z + x*y*z
Logic Simulator-Truth Table
We can create the circuit automatically using truth table
Minimization done automatically using Karnaugh Map
 Logic Simulator-Shannon Paper
• Lets have a look to the expression in Shannon
paper
• write the expression in syntax
• create the circuit
• look at truth table and minimized expression
• We have the same results as in Shannon Paper
Logic Circuit Implementation: above 3V

F = xz + xy
Inside of Logic Gate
Logic Gates Applications (AND gate)
Logic Gates Applications (AND gate)
Logic Gates Applications (OR gate)
Logic Gates Applications (XOR gate)
Logic Gates Applications (XOR gate)
Logic Gates Applications (XOR gate)
Logic Gates Applications (XOR gate)
Inside of Logic Gate
Voltage Levels
Voltage Levels

What happens if input is in middle gray region Vt?

Voltage Levels
You will also notice that there is cushion of 0.7 V between the
output of one device and the input of another. This is
sometimes referred to as noise margin.

What happens if you have a voltage that is in between 0.8 V

and 2 V? Well, your guess is as good as mine. Honestly, this
range of voltages is undefined and results in an invalid state,
often referred to as floating. If an output pin on your device is
“floating” in this range, there is no certainty with what the
signal will result in. It may bounce arbitrarily between HIGH
and LOW.

Logic Levels - SparkFun Learn

 Schmitt Triggers
• It is important to remember (Vt+ max) = Vih and
(VT– min) = Vil. In the specs, multiple limits are
related to the Schmitt trigger inputs. All of the limits
are important for different reasons.
• On the input rising edge, the part will switch
between (Vt+ min) and (Vt+ max).
• On the falling edge, the part will switch between
(Vt– max) and (Vt– min).
• The part will not switch between (Vt– max) and
(Vt+ min). This is important for noise rejection.
TTL vs CMOS Logic
Positive and Negative Logic

• Choosing the high-level H to represent logic 1 defines a

positive logic system.
• Choosing the low-level L to represent logic 1 defines a negative
logic system
Active-Low and Active-High
When working with ICs and microcontrollers, you'll likely encounter pins that are active-low and pins that
are active-high. Simply put, this just describes how the pin is activated. If it's an active-low pin, you must
"pull" that pin LOW by connecting it to ground. For an active high pin, you connect it to your HIGH voltage
(usually 3.3V/5V).

For example, let's say you have a shift register that has a chip enable pin, CE. If you see the CE pin anywhere
in the datasheet with a line over it like this, 𝐶𝐸, then that pin is active-low. The CE pin would need to be
pulled to GND in order for the chip to become enabled. If, however, the CE pin doesn't have a line over it,
then it is active high, and it needs to be pulled HIGH in order to enable the pin.

Many ICs will have both active-low and active-high pins intermingled. Just be sure to double check for pin
names that have a line over them. The line is used to represent NOT (also known as bar). When something
is NOTTED, it changes to the opposite state. So if an active-high input is NOTTED, then it is now active-low.
Simple as that!

Active low can be considered as if the signal is inverted inside the IC

4.2. Combinational Logic Circuits
• A combinational circuit consists of an interconnection of logic gates. Combinational logic gates
react to the values of the signals at their inputs and produce the value of the output signal,
transforming binary information from the given input data to a required output data

• The logic diagram of a combinational circuit has logic gates with no feedback paths or memory
elements.
Logic Diagram to Expression
Starting from input to output, construct the expression

F = ABC + (A+B+C)(AB+AC+BC)’
ABC

A+B+C

AB (AB+AC+BC)’
AC AB+AC+BC

BC
Logic Diagram to Expression
DESIGN GUIDE

1. Description of function

2. Create using Truth Table

3. Write logical expression using Truth Table

4. Implement logical expression using AND, OR, NOT gates

5. Minimize number of gates

DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Coverting integer numbers to binary
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Coverting integer numbers to binary
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number

/2
/2
/2
/2
/2
/2
DECIMAL to BINARY
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• divide to 2 till 1 or 0, write remainders in REVERSE order
• LEFTMOST BIT is the MOST SIGNIFICANT BIT of the number
BINARY ARITHMETIC
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Converting integer numbers to binary
• Arithmetic operations with numbers in base 2 follow the same rules as for decimal numbers.
• full adder with carry, augend and addend

carry 𝑐𝑘+1 𝑐𝑘 … 𝑐3 𝑐2 𝑐1
5 𝑎𝑘 … 𝑎3 𝑎2 𝑎1 𝑎0
augend 1 0 1 2 𝑏𝑘 … 𝑏3 𝑏2 𝑏1 𝑏0
addend 0 1 0 +___ +______________________
sum 1 1 1 7 𝑐𝑘+1 𝑠𝑘 … 𝑠3 𝑠2 𝑠1 𝑠0
BINARY ARITHMETIC

carry 1 4 𝑐𝑘+1 𝑐𝑘 … 𝑐3 𝑐2 𝑐1
augend 1 0 0 𝑎𝑘 … 𝑎3 𝑎2 𝑎1 𝑎0
5 𝑏𝑘 … 𝑏3 𝑏2 𝑏1 𝑏0
addend 1 0 1
sum 1 0 0 1 +____ +______________________
𝑐𝑘+1 𝑠𝑘 … 𝑠3 𝑠2 𝑠1 𝑠0
9
carry 1 1 1
7
augend 1 1 1 5
addend 1 0 1 +____
sum 1 1 0 0
12
HALF ADDER = 2bit adder
• A combinational circuit that performs the addition of two bits is called a half adder

DEC
0
1
1
2
Full Adder = 3bit adder
• A full adder is a combinational circuit that forms the arithmetic sum of
three bits.
• It consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y, represent the two
significant bits to be added. DEC
• The third input, z, represents the carry from the previous lower
0
significant position.
1
• The two outputs are designated by the symbols S for sum and C for
1
carry.
2

3
Electric Adder to the Base Two
• We can convert numbers to binary 0,1 and perform arithmetic operations using logic gates.
• Idea has been presented in Shannon 1938 thesis
Full Adder (three bits adder)
• A full adder is a combinational circuit that forms the arithmetic sum of three bits.
• It consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y, represent the two significant bits to be added.
• The third input, z, represents the carry from the previous lower significant position.
• The two outputs are designated by the symbols S for sum and C for carry.

DEC
0
1
1
2
1
2
2
3
FULL ADDER
• One that performs the addition of three
bits (two significant bits and a previous
carry) is a full-adder.
Half Adder → Full Adder
• It can also be implemented with two half adders and one OR gate, as shown in Fig. 4.8.
 4-bit Binary Adder
• 4-bit binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
• It can be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of the next full adder in the chain

𝑐𝑘+1 𝑐𝑘 … 𝑐3 𝑐2 𝑐1
𝑎𝑘 … 𝑎3 𝑎2 𝑎1 𝑎0
𝑏𝑘 … 𝑏3 𝑏2 𝑏1 𝑏0
+______________________
𝑐𝑘+1 𝑠𝑘 … 𝑠3 𝑠2 𝑠1 𝑠0
Full Adder
• Full adder implementation from truth table
Comparison of Different Implementations
• Full adder implementation from truth table
 4-bit Binary Adder
• 4-bit binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
• It can be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of the next full adder in the chain
 4-bit Binary Adder
• To demonstrate with a specific example, consider the two binary numbers A = 1011 and B = 0011.
Their sum S = 1110 is formed with the four-bit adder as follows:
• Co=0

carry 1 1 11
augend 1 0 1 1
3
addend 0 0 1 1
sum 1 1 1 0 +____
14
 4-bit Binary Adder
• To demonstrate with a specific example, consider the two binary numbers A = 1011 (11) and B =
0011 (3). Their sum S = 1110 (14) is formed with the four-bit adder as follows:
• Co=0, C4=0

carry 1 1 11
augend 1 0 1 1
3
addend 0 0 1 1
sum 1 1 1 0 +____
14
 4-bit Binary Adder
• if sum exceeding 4bits=15, overflow will occur C4=1, and 4 bit sum will be wrapped around

• so we need to stay within number of bits, otherwise unexpected results may seen

carry 1 1 1 0 11
augend 1 0 1 1
9
addend 1 0 0 1
sum 1 0 1 0 0 +____
4
 4-bit Binary Adder
• if sum exceeding 4bits=15, overflow will occur C4=1, and 4 bit sum will be wrapped around

• so we need to stay within number of bits, otherwise unexpected results may seen

carry 1 1 1 0 11
augend 1 0 1 1
9
addend 1 0 0 1
sum 1 0 1 0 0 +____
4
 8-bit Binary Adder in Arduino with overflow
• if sum exceeding 4bits=15, overflow will occur C4=1, and 4 bit sum will be wrapped around

• so we need to stay within number of bits, otherwise unexpected results may seen
 Carry Propagation
• C2 waits for C1, C3 waits for C2, C4 waits for C3, this causes a propagation delay which directly
defines performance of the adder.
• The most widely used technique employs the principle of carry lookahead logic.
• C3 does not have to wait for C2 and C1 to propagate;
 Carry Propagation
Gi is called a carry generate.
Pi is called a carry propagate
• first number input A1,A2,A3,A4
• second number input B1,B2,B3,B4
• C0 is carry input
• S1,S2,S3,S4 are output
• C4 is resultant carry output
• NOTE: Input conditions at A1, B1, A2, B2, and C0 are used to
determine outputs Σ1and Σ2 and the value of the internal carry C2.
• The values at C2, A3, B3, A4, and B4 are then used to determine
outputs Σ3, Σ4, and C4
• Can be connected cascade to create higher bit adders (8,16,32)
• Fast Carry means carry lookahead. We can observe ‘carry lookahead’ part in
the datasheet

• input parts are different

4-Bit Adder Implementation
Cin is grounded to zero
Cascade 4-Bit Adders
4-bit Binary Subtractor
• The circuit for subtracting A - B consists of an adder with inverters placed between each data input B
and the corresponding input of the full adder.
• The input carry Co must be equal to 1 when subtraction is performed. (add 1)
• The addition and subtraction operations can be combined into one circuit with one common binary
adder by including an exclusive-OR gate with each full adder
• When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor

• notice that:
• M=0; B XOR 0=B
• M=1; B XOR 1=B’ (1’s complement, add 1=C0=M)
• A-B=A + (B XOR 1) +1
 Binary Subtractor (2’s Complement)
• The subtraction of unsigned binary numbers can be done most conveniently by means of complements
• subtraction A - B can be done by taking the 2’s complement of B and adding it to A
• The 2’s complement can be obtained by taking the 1’s complement and adding 1.

• Second way of 2’s complement: start from left to the first 1. copy/paste. invert other numbers to the right

dec=6 0 1 1 0 C 1 1 10
1’s comp 1 0 0 1 10 1 0 1 0 -6
add 1 1 -6 1 0 1 0 -____
2’s comp=-6 1 0 1 0 4 1 0 1 0 0 4
 Binary Subtractor (2’s Complement)
• if A>B, A-B is positive and no overflow can occur

9 1 0 0 1 C 1 1 12
1’s comp 0 1 1 0 12 1 1 0 0 -9
add 1 1 -9 0 1 1 1 -____
2’s comp=-9 0 1 1 1 3 1 0 0 1 1 3
 Binary Subtractor (2’s Complement)
• if B>A, A-B will result a negative number, which is 2’s complement of a positive number

9 1 0 0 1
1’s comp 0 1 1 0
add 1 1
2’s comp=-9 0 1 1 1 C 1 1
2-9=-7 (=9) 2 0 0 1 0
7 0 1 1 1 -9 0 1 1 1
1’s comp 1 0 0 0 -7 or 9 1 0 0 1
add 1 1
2’s comp=-7 1 0 0 1
Overflow
• When two numbers with n digits each are added and the sum is a number occupying n + 1 digits, we
say that an overflow occurred.

• When two unsigned numbers are added, an overflow is detected from the end carry out of the most
significant position
Overflow Examples in Arduino
4.7. Binary Multiplier
• Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers.
• The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit.
• Each such multiplication forms a partial product.
• Successive partial products are shifted one position to the left.
• The final product is obtained from the sum of the partial products.
• The multiplication of two bits such as A0 and B0 produces a 1 if both bits are 1; otherwise, it produces
a 0. This is identical to an AND operation.

X 1 1 0 1
Y 1 1 0
multiply 0 0 0 0
1 1 0 1
1 1 0 1
sum 1 0 0 1 1 1 0
4.7. Binary Multiplier A0 x B3B2B1B0
A1 x B3B2B1B0
• The multiplicand is multiplied by each bit of the
multiplier, starting from the least significant bit.
• Each such multiplication forms a partial product.
• Successive partial products are shifted one position to
the left.
• The final product is obtained from the sum of the partial
products.
A2 x B3B2B1B0

B3B2B1B0 1 1 0 1
A2A1A0 1 1 0
A0x 0 0 0 0
A1x 1 1 0 1
A2x 1 1 0 1
sum 1 0 0 1 1 1 0
ARITHMETIC LOGIC UNIT
ARITHMETIC LOGIC UNIT
ARITHMETIC LOGIC UNIT
ARITHMETIC LOGIC UNIT
• M=L for Arithmetic, Cn=1 no carry
• S0=1, S3=1 for addition: A plus B
ALU_EEE213
• Lets develop an 16-bit ALU_EEE213 with 4 functions: add, sub, increment, decrement
• SEL is 2-bits. the first bit is Carry inputs of add or sub
• SEL second bit is selection of add or sub functions 0=add, 1=sub
• if SEL=10 add=A+B+1 if SEL=11, sub=A-B-1, increment, decrement
• Cout is carry of add or sub functions
• MUX select results of add or sub according to the first bit of SEL 0=add, 1=sub
• Example: SEL=00 for addition, 4 + 7= 11 = B

SEL FUNCTION INSTRUCTION

00 A+B ADD
01 A+B+1 INC
10 A-B SUB
11 A-B-1 DEC
Comparator
• A magnitude comparator is a combinational circuit that compares two numbers A and B and
determines their relative magnitudes.
• The outcome of the comparison is specified by three binary variables that indicate whether A > B, A =
B, or A < B.

• XNOR logic gate gives 1 if two inputs are the same

• so equivalence check is easy by AND and XNOR gates
• E=(A0 ⊙ B0)(A1 ⊙ B1)(A2 ⊙ B2)(A3 ⊙ B3)
Comparator
• To determine whether A is greater or less than B, we inspect the relative magnitudes of pairs of
significant digits, starting from the most significant position.
• to check if A3>B3, only case is A3=1 > B3=0, A3B3’=1 must be 1
• If the two digits of a pair are equal (x3, A3=B3 condition), we compare the next lower significant pair of
digits.
• by OR gate above conditions can be evaluated

• Xi=Ai ⊙ Bi
Comparator
• (A=B) = (A0 ⊙ B0)(A1 ⊙ B1)(A2 ⊙ B2)(A3 ⊙ B3)
 Comparator
• The outcome of the comparison is specified by three binary variables that indicate whether A > B, A =
B, or A < B.

cascade inputs are for cascade connections of higher bits

Comparator
• is this XNOR in the logic diagram?

• x2=(A2’B2+A2B2’)’=(A2+B2’)(A2’+B2)=A2A2’+A2B2+B2’A2’+B2’B2=A2B2+A2’B2’

• YES
Two-bit Comparator using digital sw
• design using Digital sw, starting from truth map
Two-bit Comparator using digital sw
• design using Digital sw, starting from truth map
DECODER
• Decoder is a combinational circuit that converts
binary information from n input lines to a maximum
of 2^n unique output lines.
• As an example, consider the three-to-eight-line
decoder circuit of Fig. 4.18

• Do=x’y’z’, D1=x’y’z …
DECODER-APPLICATIONS
• The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory
decoding or data-routing applications
 DECODER/DEMULTIPLEXER
• A decoder with enable input can function as a
demultiplexer—a circuit that receives information
from a single line and directs it to one of 2^n
possible output lines.
• The selection of a specific output is controlled by the
bit combination of n selection lines.
• The decoder of Fig. 4.19 can function as a one-to-
four-line demultiplexer when E is taken as a data
input line and A and B are taken as the selection
inputs.
• For example, if the selection lines AB = 10, output D2
will FOLLOW the input value E, while all other
outputs are maintained at 1
DEMULTIPLEXER Applications
DECODER APPLICATIONS
 BCD to 7 SEGMENT DECODER

BCD decoder are widely used to display

binary number in decimal format
4.10 Encoders
• encoder is a digital circuit that performs the inverse operation of a decoder.
• encoder has 2^n (or fewer) input lines and n output lines.
• An example of an encoder is the octal-to-binary (8 to 3) encoder whose truth table is given in Table 4.7.
• It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary
number.
• It is assumed that only one input has a value of 1 at any given time. WHAT WILL HAPPEN IF NOT ?
4.10 Encoders
• If two inputs are active simultaneously, the output produces an undefined combination.
• For example, if D3 and D4 are 1 simultaneously, the output of the encoder will be 111 because all three
outputs are equal to 1. The output 111 does not represent either binary 3 or binary 4.
• To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is
encoded
4.10 Encoders
• The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence
• The truth table of a four-input priority encoder is given in Table 4.8.
• In addition to the two outputs x and y, the circuit has a third output designated by V; this is a valid bit indicator
that is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input, and V is
equal to 0
decoders are used to reduce
number of inputs for microcontroller
 4.11 Multiplexer
• A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• Normally, there are 2^n input lines and n selection lines whose bit combinations determine which input is
selected.

• A two-to-one-line multiplexer connects one of

two 1-bit sources to a common destination, as
shown in Fig. 4.24.
• The circuit has two data input lines, one output
line, and one selection line S.
• When S = 0, the upper AND gate is enabled and
I0 has a path to the output.
• When S = 1, the lower AND gate is enabled and
I1 has a path to the output.
• The multiplexer acts like an electronic switch
that selects one of two sources.
4.11 Multiplexer

• A four-to-one-line multiplexer is shown in Fig. 4.25.

• Each of the four inputs, I0 through I3, is applied to one input
of an AND gate.
• Selection lines S1 and S0 are decoded to select a particular
AND gate.
• The outputs of the AND gates are applied to a single OR gate
that provides the one-line output
 MUX
• using MUX we can create AND OR NOT

• MEANS we can create any combinatorial circuit using only MUX

• remember that in FPGAs

Implementation of Logic Functions using MUX
LUT, Lookup Table, FPGA
• MUX architecture is fixed according to number of input bits
• input is coming from the truth table
F=A’B + B’A
A B F
0 0 0
0 1 1
1 0 1
1 1 0
Implementation of Logic Functions using MUX
LUT, Lookup Table, FPGA • MUX architecture is fixed according to
number of input bits
• input is coming from the truth table
 Implementation of Logic Functions using LUT
• Suppose we want to realize a
Boolean Function of four input
variables A, B, C and D using a 4-
input LUT
• While realizing this function using an
FPGA, A, B, C, and D will be the
inputs to LUT.
• Next, the values of the output
variable for each of their
combination (available in the last
column of the truth table) will
be stored in the Flash RAM
• if ABCD = 0101, then the output of
the LUT, Y, will take the value of 1 as
the content of the sixth memory cell
makes its way to the output pin (as
shown by the red discontinuous line
in Figure 3).
 LUT in FPGA
• there are thousands of LUT in FPGA
• Tang Nano 9K has 8640 LUT4

• LUT5-LUT8 can be constructed from LUT4 LUT3

• example LUT2, and LUT3

• Truth Table is calculated inside FPGA, A,B is

input to LUT

LUT2
4.11 Multiplexer
• A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• Normally, there are 2^n input lines and n selection lines whose bit combinations determine which input is
selected.
Applications: Multiplexer
4.11 Multiplexer
• A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• Normally, there are 2^n input lines and n selection lines whose bit combinations determine which input is
selected.
3-State Gates
• Two of the states are signals equivalent to logic 1 and logic 0 as in a conventional gate.
• The third state is a high-impedance state (Z) in which the logic behaves like an open circuit, which means that
the output appears to be disconnected
• Because of this feature, a large number of three-state gate outputs can be connected with wires to form a
common line without endangering loading effects
ALU+COMPARATOR+DECODER/DEMUX
• decoder inside MCU takes the instruction bits,
decode it and route to control lines
5.2. Sequential Circuits
• Combinational circuits are ONE WAY, no loop
• It consists of a combinational circuit to which memory elements are connected to form a feedback path
• The memory elements are devices capable of storing binary information
• The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs
but also of the present state of the storage elements.
• The next state of the storage elements is also a function of external inputs and the present state.
• Thus, a sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
• In contrast, the outputs of combinational logic depend on only the present values of the inputs
5.2. Sequential Circuits
• There are two main types of sequential circuits, and their classification is a function of the timing of their
signals
• A synchronous sequential circuit employs signals that affect the storage elements at only discrete instants of
time. Synchronization is achieved by a timing device called a clock generator, which provides a clock signal
having the form of a periodic sequence of clock pulses. The clock signal is commonly denoted by the
identifiers clock and clk
• The behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and
the order in which the inputs change.
5.3. Storage Elements: Latches
• A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to
the circuit), until directed by an input signal to switch states.
• Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches;
those controlled by a clock transition are flip-flops.
• Latches are said to be level-sensitive devices; flip-flops are edge-sensitive devices.
• The two types of storage elements are related because latches are the basic circuits from which all flip-flops
are constructed.
SR Latch
• When output Q = 1 and Q′ = 0, the latch is said to be in the set state. S=1, R=0
• When Q = 0 and Q′ = 1, it is in the reset state. S=0, R=1
• However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0
(rather than be mutually complementary) occurs.
• If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state
or a metastable state.
• Consequently, in practical applications, setting both inputs to 1 is forbidden
SR Latch (SN74279)
• three state of output 1,0,KEEP
• S’=0, R’=0 is not allowed, non stable
D Latch (Transparent Latch)
• One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that
inputs S and R are never equal to 1, S’R’=00 at the same time. This is done in the D latch, shown in Fig. 5.6.
• The binary information present at the data input of the D latch is transferred to the Q output when the enable
input is asserted.
• The output follows changes in the data input as long as the enable input is asserted. This situation provides a
path from input D to the output, and for this reason, the circuit is often called a transparent latch
D Latch
• D latch is a 1-bit register
• First EN=1, then write D-data to register, either 1 or 0
• then EN=0, keeps the value in Q like write protection
Problems of Latches
• Clock signal used for Enable
• While clock is ON if D changes then Y output will be changed which is NOT something we want
• Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational
logic to the input of the same or another latch when all the latches are triggered by a common clock source.
D Flip Flops (Falling Edge)
• Flip-flop circuits are constructed in such a way as to make them operate properly when they are part of a
sequential circuit that employs a common clock
• The construction of a D flip-flop with two D latches and an inverter is shown in Fig. 5.9.
• a change in the output of the flip-flop can be triggered only by and during the transition of the clock from 1 to
0 (Falling Edge)
• The slave latch is enabled, and its output Q is equal to the master output Y. The master latch is disabled
because Clk = 0.
• When the input (Clk) pulse changes to the logic-1 level, the data from the external D input are transferred to
the master. The slave, however, is disabled
• like two doors entrance, only one person=D can pass, if you are inside the first door is closed
• There are Rising Edge D Flip-Flops, too.
D Flip Flops (Falling Edge)
• D flipflop is constructed by two Dlatch, En signal became Clock
• Q takes the value of D at falling edge of Clk
D Flip Flops: Applications
• to the Q output on the low to high transition, Rising Edge of the CLOCK input (CP).
• The MR=‘Master Reset’ input, when low, sets all outputs to a low state.
JK Flip Flops
• With only a single input, the D flip-flop can set or reset the output,
• the JK flip-flop has two inputs and performs three functions : Set it to 1, reset it to 0, or complement its
output
• The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is
complemented.
• This can be verified by investigating the circuit applied to the D input:
• D = JQ′ + K′Q
T Flip Flops
• The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K
are tied together. This is shown in Fig. 5.13(a).
• When T = 0 (J = K = 0), a clock edge does not change the output. When T = 1 (J = K = 1), a clock edge
complements the output. The complementing flip-flop is useful for designing binary counters.
6.1. Registers with Parallel Load
• A register is a group of flip-flops, each one of which shares a common clock and is capable of storing
one bit of information
• Registers with parallel load are a fundamental building block in digital systems
• If all the bits of the register are loaded simultaneously with a common clock pulse, we say that the
loading is done in parallel
• Performing logic with clock pulses inserts variable delays and may cause the system to go out of
synchronism
6.1. Registers
• A four-bit data-storage register with a load control
input that is directed through gates and into the D
inputs of the flip-flops is shown in Fig. 6.2.
• The additional gates implement a two-channel mux
whose output drives the input to the register with
either the data bus or the output of the register
• The load input to the register determines the
action to be taken with each clock pulse.
• When the load input is 1, the data at the four
external inputs are transferred into the register
with the next positive edge of the clock. Write
enable
• When the load input is 0, the outputs of the flip-
flops are connected to their respective inputs
• The feedback connection from output to input is
necessary because a D flip-flop does not have a “no
change” condition
6.1. Registers
• Load=1, write enable, input transferred into
register at rising edge of clock
• Load=0 write protect. register values are
kept
6.1. Registers
• Load=1, write enable, input transferred into
register at rising edge of clock
• Load=0 write protect. register values are
kept
• The MC14076B 4−Bit Register consists of four D−type flip−flops
operating synchronously from a common clock.
• OR gated output−disable inputs force the outputs into a
high−impedance state for use in bus organized systems.
• OR gated data−disable inputs cause the Q outputs to be fed back
to the D inputs of the flip−flops.
• Thus they are inhibited from changing state while the clocking
process remains undisturbed
6.2. Shift Registers
• A register capable of shifting the binary information held in each cell to its neighboring cell, in a selected
direction, is called a shift register
• The logical configuration of a shift register consists of a chain of flip-flops in cascade, with the output of one
flip-flop connected to the data input of the next flip-flop. All flip-flops receive common clock pulses, which
activate the shift of data from one stage to the next.
• Each clock pulse shifts the contents of the register one bit position to the right
6.2. Shift Registers
• Si=1 reaches So after 4 clock cycle
• Serial input 4-bit Parallel output
6.2. Shift Registers
Applications: Shift Registers
Applications: Shift Registers

• Arduino Motor Shield uses 74HC595 to

control H-Bridge L293D.

• Serial to parallel conversion

6.2. Shift Registers (74HC595)
Ripple Counters
• A binary ripple counter consists of a series connection of complementing flip-
flops, with the output of each flip-flop connected to the input of the next
higher order flipflop
• A third possibility is to use a D flip-flop with the complement output connected
to the D input. In this way, the D input is always the complement of the present
state, and the next clock pulse will cause the flip-flop to complement
Ripple Counters: Downcounter - Upcounter
• 4bit down counter 15,14,13… • 4bit up counter 0,1,2,3…
• It contains two independent counter circuits in one package, so that counting or frequency division of 8
binary bits can be achieved with one IC.
• This device changes state on the negative going transition of the CLOCK pulse.
• The counter can be reset to “0” (Q0–Q3 = “L”) by a HIGH at the CLEAR input regardless of other inputs
• It contains two independent counter circuits in one package, so that
counting or frequency division of 8 binary bits can be achieved with one
IC.
• This device changes state on the negative going transition of the CLOCK
pulse.
• The counter can be reset to “0” (Q0–Q3 = “L”) by a HIGH at the CLEAR
input regardless of other inputs
4 Bit Binary Counter
BCD Counter
Synchronous Counter
Synchronous counters have common clock
faster, no cascade connection
Jhonson Ring Counter
• ring counter is a circular shift register with only one flip-flop being set at any particular time;
• Standard 2, 3 or 4-stage Johnson Ring Counters can also be used to divide the frequency of
the clock signal by varying their feedback connections and divide-by-3 or divide-by-5
outputs are also available.
Program Counter
• Program counter is the ADRESS OF THE NEXT INSTRUCTION to be executed
• it is a binary counter increments at each clock
• jumping up/down is possible
Memory
• A memory unit is a device to which binary information is transferred for storage and from which
information is retrieved when needed for processing.
• When data processing takes place, information from memory is transferred to selected registers in the
processing unit.
• Intermediate and final results obtained in the ALU processing unit are transferred back to be stored in
memory.
• Binary information received from an input device is stored in memory, and information transferred to an
output device is taken from memory
• There are two types of memories that are used in digital systems: random-access memory (RAM) and read-
only memory (ROM).
• RAM stores new information for later use. The process of storing new information into memory is referred
to as a memory write operation. The process of transferring the stored information out of memory is
referred to as a memory read operation. RAM can perform both write and read operations.
• ROM can perform only the read operation.
Read-Only Memory (ROM)
• A read-only memory (ROM) is essentially a memory device in which permanent binary information is stored
• it stays within the unit even when power is turned off and on
• electrically erasable PROM (EEPROM). programmed data can be erased with an electrical signal
• Flash memory devices are similar to EEPROMs, but have additional built-in circuitry to selectively program
and erase the device in-circuit, without the need for a special programmer
Read-Only Memory (ROM)
• Consider, for example, a 2 * 4 ROM. The unit consists of 2 words of 4 bits each.
• The two inputs are decoded into 4 distinct outputs by means of a 2 * 4 decoder
• connections to OR gates performed (programmed) according to the truth table for each address line
• open connection are connected to ground (logic0)
• address is input, ROM will give output in truth table at selected address

Address Output
A1 A0 F3 F2 F1 F0
0 0 0 0 1 1
0 1 0 1 1 0
1 0 1 1 0 0
1 1 1 1 1 1
Read-Only Memory (ROM)
• We can represent any combinatorial circuit with truth table MEANS that we can represent any combinatorial
circuit with ROM
• lets have a look half adder

Address Output
A1 A0 C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Read-Only Memory (ROM)

the device is organized as a

single block of 128 x 8-bit
memory with a 2-wire serial
interface.
Read-Only Memory (ROM)
• A read-only memory (ROM) is essentially a memory device in which permanent binary information is stored
• it stays within the unit even when power is turned off and on
• electrically erasable PROM (EEPROM). programmed data can be erased with an electrical signal
• Flash memory devices are similar to EEPROMs, but have additional built-in circuitry to selectively program
and erase the device in-circuit, without the need for a special programmer
Random Access Memory (RAM)
• A memory unit is a collection of storage cells, together with associated circuits needed to transfer
information into and out of a device.
• time it takes to transfer information to or from any desired random location is always the same—hence the
name random-access memory, abbreviated RAM
• A memory unit stores binary information in groups of bits called words. A group of 8 bits is called a byte.
• Most computer memories use words that are multiples of 8 bits in length. Thus, a 16-bit word contains two
bytes, and a 32-bit word is made up of four bytes. The capacity of a memory unit is usually stated as the
total number of bytes
Random Access Memory (RAM)
• This RAM consists of four words of four bits each and has a total of 16 binary cells.
• The small blocks labeled BC represent the binary cell with its three inputs and one output
• A memory with four words needs two address lines. The two address inputs go through a 2 * 4 decoder to select
one of the four words
• When the memory enable is 0, all outputs of the decoder are 0 and none of the memory words are selected
• During the read operation, the four bits of the selected
word go through OR gates to the output terminals
Random Access Memory (RAM)
• memory cell is 1 bit register
Random Access Memory (RAM)
• 4x4 RAM
• SRAM: Static RAM with SR Latch
• DRAM: RAM with capacitors
Random Access Memory (RAM)
• We can read or write to RAM, giving Adress and Data inputs
• RAM is empty power on
• write: load data and adress, at clock cycle it will write data to the adress
• read: reads the adress transfers to the output
Microcontroller (MCU)
Arduino MEGA Microcontroller (MCU)
• We almost covered boxes of an Arduino MEGA ATMEGA640 MCU
• NOW we can design our own microcontroller
 EEE207 MCU DESIGN
• 8 INSTRUCTIONS, 16bit DAT
• 5-bits for instructions and 16 bits for DATA
• RA, RB, RAM enable has to be controlled

INSTRUCTION ROM SC FUNCTION RA MUXA RB STS

xyz xy xyz’ xy’z xy’z’
LDA 1 1000 0004=180004 LOAD A 1 1
ADD 1 1100 XXXX=1CXXXX 00 A+B 1 INSTRUCTION ROM

SUB 1 1110 XXXX=1EXXXX 10 A-B 1

LDA 0X180004
INC 1 1101 XXXX=1DXXXX 01 A+B+1 1
LDB 0X140002
DEC 1 1111 XXXX=1FXXXX 11 A-B-1 1
ADD RA RB 0X1CFFFF
LDB 1 0100 0002=140002 LOAD B 1
SUB RA RB 0X1EFFFF
STS 1 0000 XXXX=10XXXX STS 0x00 RA 1
STS RA 0X10FFFF
NOP 0 0000 XXXX=00XXXX
EEE207 MCU DESIGN
• General Architecture of MCU
• Program Counter PC
• ROM
• LOGIC CONTROL Gates for RAEn, RBEn, MUX, RAMstr
• RA,RB registers
• ALU
• RAM
EEE207 MCU DESIGN
• TURN ON
• PC=0, ROM address 0 is 0x180004 loaded
• RAEn=1, Mux=1 ready to take the value into RA in next cycle
EEE207 MCU DESIGN
• 1st clock cycle
• PC=1 ROM address 1 is 0x140002 loaded
• RA=4 loaded
• RBEn=1, ready to take the value into RB in next cycle
EEE207 MCU DESIGN
• 2st clock cycle
• PC=2 ROM address 2 is 0x1CFFFF loaded
• RB=2 loaded
• ALU=4+2=6
• RAEn=1, ready to take the ALU value into RA in next cycle
EEE207 MCU DESIGN
• 3rd clock cycle
• PC=3 ROM address 3 0x1EFFFF loaded
• ALU=6-2=4
• RAEn=1, ready to take the ALU value into RA in next cycle
EEE207 MCU DESIGN
• 4th clock cycle
• PC=4 ROM address 4 0x10FFFF loaded
• RA=4 loaded
• RAMstr=1, ready to take RA the value into RAM in next cycle
EEE207 MCU DESIGN
• 5th clock cycle
• PC=5 ROM address 5 0x0 loaded
• RAM address=0x0 loaded with RA=4
EEE207 MCU DESIGN
• 6th clock cycle
• PC=6 ROM address 6 0x0 loaded
• RA, RB, RAM inputs are disabled
• RA,RB,RAM values are kept as it is
• NOP instruction
 EEE207 MCU DESIGN
• Similar instructions in Arduino Assembly Language

volatile byte a=0;

void setup() {
Serial.begin(9600);
asm (
"ldi r26, 4 \n"
"ldi r27, 2 \n"
"add r26, r27 \n"
"sub r26, r27 \n"
"sts (a), r26 \n"
);
Serial.print("a = ");
Serial.println(a);
}
void loop() { }