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Vlsi Expt 1

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6 views

Vlsi Expt 1

Uploaded by

devipriya1474
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 24

Expt.

No: 1
IMPLEMENTATION OF ADDERS AND
Date: SUBTRACTORS
31.1.24

AIM :
To implement half adder, full adder, half subtractor, and full
subtractor using Verilog code and Basys-3 board.
REQUIREMENTS:
SOFTWARE: VIVADO 2017.4
HARDWARE: BASYS 3
PROCEDURE:
1. Open Vivado application and click “Create new project” to start the
implementation. Click next in a dialogue box that appears.
2. Enter the program name and a project location and click Next.
3. Select the project type as “RTL project” and click Next.
4. Select “Create file” to create a new file.
5. Give the file name as module name, then check whether the project
name is same as filename and click Next.
6. In the default part, select the board and among the options, click
Basys-3 and click Next.
7. In the “Define module” tab, give the module name and set the input
and output parameters.
8. Open the “filename.v” in sources to code the required design.
9. Select the symbol “+” to create a file in the Source
TO CREATE TEST BENCH:
1) Select “Add or create simulation sources”.
2) Select “create file” and for the filename, name the file
as “file name.tb” under simulation sources, select
“filename.v” and code file to test all possible cases in
“filename.v”
HALF ADDER

TRUTH TABLE:
LOGICAL EXPRESSION:

Sum[i] = A[i] ⊕ B[i]


Carry[i] = A[i]&B[i]

CIRCUIT DIAGRAM:

CODE:

HALF ADDER:

GATE LEVEL:
module halfaddergate(input a,b, output s,c);
xor (s.a.b);
and (c,a,b);
endmodule

DATAFLOW:
module halfadderdataflow(output s,c, input a,b);
assign s=a^b;
assign c=a&b;
endmodule

BEHAVIORAL MODEL:

module halfadder(input a,b,output reg s,c);


always@(*)begin
s=a^b;
c=a&b;
end
endmodule

SIMULATION OUTPUT:
RTL SYNTHESIS:

TESTBENCH:

module twoinput_tb();
reg a,b;
wire s,c;
halfadder uut(.a(a),.b(b),.s(s),.c(c));

initial begin

a = 1'b0;
b = 1'b0;

#10
a = 1'b0;

b = 1'b1;

#10

a = 1'b1;

b = 1'b0;

#10
a = 1'b1;

b = 1'b1;

#10

$finish;

end

endmodule

POWER ANALYSIS:

DESIGN UTILISATION:
DELAY ANALYSIS:
Setup delay:

Hold delay:
FULL ADDER
TRUTH TABLE:

LOGICAL EXPRESSION:
S[i] = A[i]⊕B[i]⊕Cin[i]

Cout[i] = A[i]&B[i] + B[i]&C[i] +C[i]&A[i]

FULL ADDER:

module full_adder(input a,b,c, output reg sum,carry );


always@(a or b or c)
begin
sum= a^b^c;
carry= a&b | b&c | c&a;
end
endmodule

CIRCUIT DIAGRAM:
SIMULATION OUTPUT:

RTL SYNTHESIS:

TESTBENCH:
module test_full();
reg a,b,c;
wire sum,carry;
full_adder uut(.a(a),.b(b),.c(c),.sum(sum),.carry(carry));
initial begin
a=0;b=0;c=0;
end
always
#40 a<=~a;
always
#20 b<=~b;
always
#10 c<=~c;
always
#80
$finish;
endmodule

POWER ANALYSIS:
DESIGN UTILISATION:

DELAY ANALYSIS:
Setup delay:

Hold delay:
HALF SUBTRACTOR

TRUTH TABLE:
LOGICAL EXPRESSION:
Difference[i] = A[i]⊕B[i]
Borrow[i] = ~A[i]&B[i]

CIRCUIT DIAGRAM:

HALF SUBTRACTOR:

module halfsub_rd(input a,b, output reg diff, borrow);


always@(*)begin
diff = a ^ b;
borrow = (~a) && b;
end
endmodule

SIMULATION OUTPUT:
RTL SYNTHESIS:

TESTBENCH:

module twoinput_tb();
reg a,b;
wire s,c;
halfsub_rd uut(.a(a),.b(b),.s(s),.c(c));

initial begin
a = 1'b0;

b = 1'b0;

#10
a = 1'b0;

b = 1'b1;

#10

a = 1'b1;

b = 1'b0;

#10
a = 1'b1;

b = 1'b1;

#10

$finish;

end

endmodule

POWER ANALYSIS:
DESIGN UTILISATION:

DELAY ANALYSIS:
Setup delay:

Hold delay:
FULL SUBTRACTOR

TRUTH TABLE:
LOGICAL EXPRESSION:
D = A⊕B⊕Bin
Bout = (~A&B) + (~A+B)Bin
CIRCUIT DIAGRAM:

FULL SUBTRACTOR
module fullsub_rd(input a,b,c, output reg diff, borrow);
always@(a or b or c)
begin
diff = a ^ b ^ c;
borrow = (~a && b) || (~a && c) || (b && c) ;
end
endmodule

SIMULATION OUTPUT:

RTL SYNTHESIS:
POWER ANALYSIS:

TESTBENCH:
module test_fullsub_rd();
reg a,b,c;
wire diff,borrow;
fullsub_rd uut(.a(a), .b(b), .c(c), .diff(diff), .borrow(borrow));
initial begin
a=0;b=0;c=0;
end
always
#40 a<=~a;
always
#20 b<=~b;
always
#10 c<=~c;
always
#80
$finish;
endmodule

DESIGN UTILISATION:

DELAY ANALYSIS:
Setup delay:
Hold delay:

RESULT:
Thus, design and simulation of adders and subtractors has been
implemented in simulation (vivado) and hardware (basys 3) successfully.

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