The Code Segment and the Instruction Pointer

 The code segment is the area of memory where code alone is stored.
 The offsets within the code segment are referenced using the Instruction
Pointer (IP), which is a 16-bit register.
 The IP sequences the instructions, and always points to the next
instruction to be executed.
 This 20-bit address is then placed on the address bus and the instruction
byte is fetched.
 Thus the logical address for an instruction bye is of the form CS : IP.
The Stack Segment and the Stack Pointer
 The stack is an area of memory that is used in a special case.
 Data is generally pushed in and popped out of the stack.
 The 8086 is a last-in-first-out (LIFO) stack, which means that the last
data that was pushed in, is the first one that can be popped out.
 However the ‘stack top’ changes as data is put in or taken out.
 A 16-bit register called Stack Pointer which points to the top of the stack.
 The stack segment is like any other segment, and the upper 16 bits of its
base address is available in the SS register.
 Thus the logical address for an instruction bye is of the form SS : SP.
Stack and physical address of the top of stack
The Data Segment and Extra Segment
 Both these segments store data, but in certain special cases (string
instructions), it may be necessary to list them separately.

 An Extra Segment (ES) register to store the upper 16 bits of the base
address of the extra segment.

 An Data Segment (DS) register to store the upper 16 bits of the base
address of the extra segment.

 The effective address calculation depends on the mode of addressing,

while use of these segments.
Segments and Corresponding Registers Used for Specifying Offsets
Advantages of Segmentation
 All address registers are only 16 bit long.

 Though the physical address is calculated 20 bits.

 All addresses are re-locatable.

 All processors in the x86 family have this kind of segmentation.

Memory organization
 Data is stored in memory as bytes, each byte location has an address.

 If a two bytes is to be stored, two locations of consecutive addresses.

 Intel’s processors use two ways of storing the data in memory i.e.
i. little endian format
ii. big endian format
Endian formats
In the case of a bytes of data stored
In the case of a bytes of data stored
in memory, if the higher byte is
in memory, if the lower byte is in
stored at the lower memory
the lower address and the higher
address, and the lower byte is
byte is in the higher address is
stored at higher memory addresses
called the little endian format
is called the big endian format.
Consider that the number 34E6 is Consider that the number 34E6 is
to be stored. to be stored.

Address Address
60088H E6 60088H 34
60089H 34 60089H E6
Example

 DS contains the number 345BH.

 Th e base address of the segment is 345B0H.
 The last address will have an offset of 12K from the base address.
 1K = 1024 bytes.
 12K = 12 × 1024 = 12288D = 3000H.
 The last address of the segment = 345B0H + 3000H = 375B0H.
 Hence, the data segment occupies the memory addresses from
345B0H to 375B0H.
Tutorial Question
PIN Signal description of 8086
 The 8086 is a 16-bit CPU available in three
clock rates, i.e. 5, 8 and 10 MHz, packaged in a
40 pin package.
 The 8086 operates in single processor or
multiprocessor configurations to achieve high
8086
performance.
 The pin configuration is shown in Figure.
 Some of the pins serve a particular function in
minimum mode (single processor mode) and
others function in maximum mode
(multiprocessor mode) configuration.
PIN Signal description of 8086
 The 8086 signals can be categorized in three groups.

➢ The first are the signals having common functions in

minimum as well as maximum mode,
➢ The second are the signals which have special functions for
minimum mode
➢ The third are the signals having special functions for
maximum mode.
PIN Signal description of 8086
The following signal descriptions are common for both the minimum and maximum modes.

 AD 15-AD0 These are the time multiplexed memory I/O address and data
lines.
➢ Address remains on the lines during T₁ state, while the data is
available on the data bus during T2,T3, Tw and T4.
➢ Here T1,T2,T3,T4 and Tw are the clock states of a machine cycle.
Tw is a wait state.
➢ These lines are active high and float to a tristate during interrupt
acknowledge and local bus hold acknowledge cycles.
PIN Signal description of 8086
 A19/S6A18/S5,A17/S4, A16/S3 These are also time multiplexed address
and status lines.
 During T₁, these are the most significant address lines for memory
operations, during I/O operations these lines are low.
 The S4 and S3 together indicate which segment register is presently
being used for memory accesses, as shown in Table.

 The address bits are separated from the status bits using latches con-
trolled by the ALE signal
PIN Signal description of 8086
 BHE/S7 (Bus High Enable/Status) The bus high enable signal is used to
indicate the transfer of data over the higher order (D15 - D8) data bus
as shown in Table.

 It goes low for the data transfers over D15 - D8, and is used to derive chip
selects of odd address memory bank or peripherals.
 BHE is low during T1 for read, write and interrupt acknowledge cycles,
whenever a byte is to be transferred on the higher byte of the data bus.
 S7 is currently not used.
PIN Signal description of 8086
 RD-Read: Read signal, when low, indicates the peripherals that the
processor is performing a memory or I/O read operation. RD is active
low and shows the state for T2, T3, Tw of any read cycle. The signal re-
mains tristate during the 'hold acknowledge’.

 READY This is the acknowledgement from the slow devices or memory

that they have completed the data transfer. The signal made available by
the devices is synchronized by the 8284A clock generator to provide
ready input to the 8086. The signal is active high.
 PIN Signal description of 8086
 INTR-Interrupt Request: This is a level triggered input. If any interrupt request
is pending, the processor enters the interrupt acknowledge cycle. This can be
internally masked by resetting the interrupt enable flag. This signal is active high
and internally synchronized.

 NMI-Non-maskable Interrupt: This is an edge-triggered input which causes a

Type2 interrupt. The NMI is not maskable internally by software. A transition
from low to high initiates the interrupt response at the end of the current
instruction.

 TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
 PIN Signal description of 8086
 RESET This input causes the processor to terminate the current activity and start
execution from FFFFOH. The signal is active high and must be active for at least
four clock cycles. It restarts execution when the RESET returns low.

 CLK-Clock Input The clock input provides the basic timing for processor
operation and bus control activity. It's an asymmetric square wave with 33% duty
cycle. The range of frequency for different 8086 versions is from 5MHz to 10MHz.

 MN/MX The logic level at this pin decides whether the processor is to operate in
either minimum (single processor) or maximum (multiprocessor) mode.
PIN Signal description of 8086
The following pin functions are for the minimum mode operation of 8086:

 M/I/O-Memory/IO When it is low, it indicates the CPU is having an I/O

operation, and when it is high, it indicates that the CPU is having a
memory operation. This is a status line logically equivalent to S2 in the
maximum mode.

 INTA-Interrupt Acknowledge This signal is used as a read strobe for

interrupt acknowledge cycles. In other words, when it goes low, it means
that the processor has accepted the interrupt.
PIN Signal description of 8086
 ALE-Address Latch Enable This output signal indicates the availability
of the valid address on the address/data lines, and is connected to latch
enable input of latches. This signal is active high and is never tristate.

ഥ
 DT/R-Data Transmit/Receive This output is used to decide the direction
of data flow through the transreceivers (bidirectional buffers). When the
processor sends out data, this signal is high and when the processor is
receiving data, this signal is low. Its timing is the same as M/I/O This is
tristate during 'hold acknowledge'.
PIN Signal description of 8086
 DEN-Data Enable This signal indicates the availability of valid data over
the address/data lines. It is used to enable the transreceivers to separate
the data from the multiplexed address/data signal.

 HOLD, HLDA-Hold/Hold Acknowledge When the HOLD line goes

high, it indicates to the processor that another master is requesting the
bus access. The processor, after receiving the HOLD request, issues the
hold acknowledge signal on HLDA pin, in the middle of the next clock
cycle after completing the current bus (instruction) cycle.
PIN Signal description of 8086
The following pin functions are for the maximum mode operation of 8086:
 S2, Sഥ𝟏 , Sഥ𝟎 -Status Lines These are the status lines which indicate the
type of operation, being carried out by the processor. Any change in
these lines during T3 indicates the starting of a new cycle, and return to
passive state indicates end of the bus cycle. These status lines are
encoded in Table.
PIN Signal description of 8086
 LOCK This output pin indicates that other system bus masters will be
prevented from gaining the system bus, while the LOCK signal is low. The
LOCK signal is activated by the 'LOCK' prefix instruction and remains
active until the completion of the next instruction. This floats to tri-state
off during "hold acknowledge".

 QS1, QS0-Queue Status These lines give information about the status of
the code-prefetch queue. These are active during the CLK cycle after
which the queue operation is performed. These are encoded as shown in
Table.
PIN Signal description of 8086
 RQ / GT0., RQ / GT1, -Request/Grant These pins are used by other local
bus masters, in maximum mode, to force the processor to release the local
bus at the end of the processor's current bus cycle. Each of the pins is
bidirectional, The request/grant sequence is as follows:
 A pulse one clock wide from another bus master requests the bus access to 8086.
 During T4 (current) or T₁ (next) clock cycle, a pulse one clock wide from 8086 to
the requesting master, indicates that the 8086 has allowed the local bus to float
and that it will enter the "hold acknowledge“
 A one clock wide pulse from the another master indicates to 8086 that the 'hold'
request is about to end and the 8086 may regain control of the local bus at the
next clock cycle.
General Bus Operation
I/O ADDRESSING CAPABILITY
 The 8086 processor can address up to 64K I/O byte registers.

 The limitation is that the address of an I/O device must not be greater
than 16 bits in size, i.e. a maximum number of 216, i.e. 64KB I/O devices
may be accessed by the CPU.

 The I/O address appears on address bus A0 to A15 for one clock cycle (T₁).

 The 16-bit register DX is used as 16-bit I/O address pointer, with full
capability to address up to 64K devices.
 I/O ADDRESSING CAPABILITY
➢ Even addressed bytes are transferred
on D7-D0 and odd addressed bytes
are transferred on D8-D15 lines.

➢ While designing any 8-bit I/O system

around 8086, care must be taken that
all the byte registers in the system
should be even addressed.
DERIVING SYSTEM BUS
 The 8086 has a multiplexed
16-bit address/data bus (ADo-
AD15) and a multiplexed 4-bit
address/status bus A16/S3-
A19/S6.
 The address can be latched
using signal ALE, as shown in
Figure.
 Commercially available latch
chips contain eight latches.
DERIVING SYSTEM BUS
 The data can be separated from the
address and buffered using two
bidirectional buffers 74245.
 The signals DNE and DT/R ഥ indicate the
presence of data on the bus and the
direction of the data, i.e. to / from the
microprocessor.
 They are used to drive the chip select
(enable) and direction pins of the buffers
as indicated below in Figure.
DERIVING SYSTEM BUS
 For deriving control bus from the available control signals RD, WR and
M/IO in case of minimum mode of operation any combinational logic
circuit may be used as shown in Fig. (a) and Fig. (b).

 In case of maximum mode of operation a chip bus controller derives all

the control signals using status signals So, S1 , and S2.
MINIMUM MODE 8086 SYSTEM AND TIMINGS
 In a minimum mode, the microprocessor 8086 is operated in minimum
mode by strapping its MN/MX pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor
chip itself.
 The remaining components in the system are latches, transreceivers, clock
generator, memory and I/O devices.
 Some type of chip selection logic may be required for selecting memory or
I/O devices, depending upon the address map of the system.
READ CYCLE TIMING DIAGRAM
WRITE CYCLE TIMING DIAGRAM
MAXIMUM MODE 8086 SYSTEM AND TIMINGS
READ CYCLE TIMING DIAGRAM
WRITE CYCLE TIMING DIAGRAM
ADDRESSING MODES
 The computations in assembly language, it needs an opcode and
operands.
 In the 8086, an instruction can have either one, or two operands (not
more).
 The way in which operands are specified in an assembly language
instruction is called its addressing mode .
 Let us attempt to get a clear understanding of the different addressing
modes allowed for this processor.
ADDRESSING MODES
 For a move instruction ,the format is

Opcode Destination, Source

MOV AX, FFFFH

Addressing modes- basic assumptions
 The operands can be in registers, in memory ,or may be in the instruction
itself .

 In the case of two operands, one of them can be in memory ,but the other
will have to be placed in a register .

 Data types should match –i.e. the source and destination should both be
either bytes or words
Type of addressing modes
i. Immediate vii. Based indexed

ii. Direct viii. Relative based indexed

iii. Register ix. Intrasegment direct mode

iv. Register indirect x. Intrasegment indirect mode

v. Indexed xi. Intersegment direct mode

vi. Register relative xii. Intersegment indirect mode

Immediate Addressing
In this type of addressing, immediate data is a part of instruction, and appears in the form of
successive byte or bytes.

 Here, the source will be a constant data

 MOV AL, 45H

 MOV BX, 34E3H
 MOV PRICE,40
 MOV NUMS, 0FC6H

 Segment registers are not allowed to use this mode of addressing.

Direct Addressing
A 16-bit memory address (offset) or an IO address is directly specified in the instruction
as a part of it. Here either the source or the destination will be a memory address

 MOV AX,[2345H]
 IN 80H
 MOV [1089H],AL

 The effective address is 10H*DS+2345H, 80H is IO address

 Exercise
 Show the location of data in memory, after the execution of each of these instructions, if the content
of registers are as given DS = 1112H, AX = EE78H
i) MOV [0422H], AL ii) MOV [0424H], AX
Register Addressing
In the register addressing mode, the data is stored in a register and it is referred using the
particular register. All the registers, except IP, may be used in this mode.

 MOV AL, AH
 MOV CH, BL
 MOV SI, BX
 MOV ES, AX

 MOV AX, BL ;gives an error as AX is 16 bit and BL is 8 bit

Register Indirect Addressing
In this addressing mode, the offset address of data is in either BX or SI or DI register.
The default segment is either DS or ES.

 In this mode , the address of the data is held in a register (Effective address)
 The address registers allowed are BX, SI and DI.

 MOV [SI], CL

 MOV AX, [BX]

 The content of the AL, AH will be [BX], [BX+1]

 MOV [DI], AX
 The content of AH will be moved to the address [DI + 1].
Exercise
Show the location of data in memory, after the execution of instruction, if the content of
registers are as given DS = 1112H, AX = EE78H and BX = 3400H (i) MOV [BX], AX

This is a case of register indirect addressing. BX is a pointer to the address 3400H,

which is an off set. The corresponding physical address is
11120H +
3400H
14520H
Register relative addressing
The data is available at an effective address formed by adding an 8-bit or 16-bit displacement with
the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment.

 In relative addressing mode , a number or displacement is part of the effective

address
 EA ={[BX] /[DI] /[SI] /[BP]} + 8 bit or 16 bit displacement

 MOV AX, 50H[BX]

 MOV 10H[SI]. DX
 Here, the effective address is given as 10H*DS+50H+[BX] and 10H+DS+10H+[SI].

 MOV AX, [BX + 50] ; instruction can also be written as

Indexed addressing
 Offset of the operand is stored in one of the index registers.
 DS is the default segment for index registers SI and DI.
 In case of string instructions DS and ES are default segments for SI and DI.
 This mode is a special case of the register indirect addressing.

 MOV AX, [SI]

 MOV CX, [DI]

 Here, data is available at offset address stored in SI & DI, The EA is computed
as 10H*DS+[SI]
Based Indexed Mode
In this addressing mode, by adding content of a base register (any one of BX or BP) to the
content of an index register (any one of SI or DI). The default segment register may be ES or DS.

 In this mode ,an index register and a base register together carry the
effective address .
 The content of these two registers are added and called the EA.

 MOV AL, [BX][SI]

 MOV [BX][DI], CX

 The effective address is computed as 10H*DS+[BX]+[SI]

Relative Based Indexed Mode
The effective address is formed by adding an 8 or 16-bit displacement with the sum of contents of
any one of the base registers (BX or BP) and any one of the index registers, in a default segment.

 The ‘effective address is the sum of the two registers and a displacement.

 MOV DL ,50[BX][DI]
 MOV 5[BP][SI], AX

 The effective address is computed as 10H*DS+50+ BX + DI

Example
Find the address of physical memory for the following instructions if the content of the required
registers are given as SS =2344 H, DS =4022H , BX =0200H, BP=1402H , SI=4442H
(i) MOV CL,1234H[SI] (i) MOV AL, 5[SI[[BP]

This is a case of register relative addressing. The effective address is obtained from the
instruction, to be the sum of the displacement and SI
Effective address = 1234H +
4442H
5676H
The segment base address is obtained from DS to be 40220H
The physical address is the sum of the segment base address and the effective address.
i.e., 40220H +
5676H
45896H
Find the address of physical memory for the following instructions if the content of the required
registers are given as SS =2344 H, DS =4022H , BX =0200H, BP=1402H , SI=4442H
(i) MOV CL,1234H[SI] (i) MOV AL, 5[SI[[BP]
Effective Address and Referred Segments for Various Memory
Based Addressing Modes
Control transfer instructions addressing
 The addressing modes depend upon whether the destination location
is within the same segment or in a different one.

 It also depends upon the method of passing the destination address to

the processor.

 Basically, there are two addressing modes for the control transfer
instructions, i.e. intersegment and intrasegment addressing modes.
Control transfer instructions addressing
 Basically, there are two addressing modes for the control transfer
instructions, i.e. intersegment and intrasegment addressing modes.

 If the location to which the control is to be transferred lies in a different

segment other than the current one, the mode is called intersegment
mode.

 If the destination location lies in the same segment, the mode is called
intrasegment mode.
Control transfer instructions addressing

Figure: Addressing modes for control transfer Instructions

Intrasegment Direct Mode
✓ In the same segment in which the control transfer instruction lies and appears directly in the
instruction as an immediate displacement value.
✓ In this addressing mode, the displacement is computed relative to the content of the
instruction pointer IP.

 JMP SHORT/LONG LABEL

 LABEL lies within -128 TO +127 from the current IP content. Thus SHORT LABEL
is 8-bit signed displacement.
 A 16-bit target address of a LABEL indicates that it lies within -32768 to +
32767.
Intrasegment Indirect Mode
✓ The displacement to which the control is to be transferred, is in the same segment in which the control
transfer instruction lies, but it is passed to the instruction indirectly.

✓ Here, the branch address is found as the content of a register or a memory location.

 JMP [BX] :Jump to effective address stored in BX.

 JMP [ BX + 5000H]
Intersegment Direct Mode
The address to which the control is to be transferred is in a different segment. This addressing
mode provides a means of branching from one code segment to another code segment. Here, the
CS and IP of the destination address are specified directly in the instruction.

 JMP 5000H 2000H

 Jump to effective address 2000H in segment 5000H.
Intersegment Indirect Mode
the address to which the control is to be transferred lies in a different segment and it is passed to
the instruction indirectly, i.e. contents of a memory block containing four bytes, i.e. IP(LSB),
IP(MSB), CS(LSB) and CS(MSB) sequentially.

 JMP [2000H];

 Jump to an address in the other segment specified at effective address

2000H in DS, that points to the memory block as said above.
Segment Override
✓ Segment can be overridden by a segment override prefix.

✓ The format of this override prefix is shown below.

✓ MOV AL, ES:[BX] overrides the fact that an instruction of this sort implies that the
data segment is to be used.

 MOV AL , ES: [BX] ;ES to be used instead of DS

 MOV DS:[BP+7], BL ;DS to be used instead of SS
 MOV AX, CS:[BX ] ;CS to be used instead of DS
Tutorial 1
The contents of different registers are given below, find the effective addresses
for different addressing modes.
Offset (displacement) = 5000H
[AX]-1000H, [BX]-2000H, [SI]-3000H, [DI]-4000H, [BP]-5000H,
[SP]-6000H, [CS]-0000H, [DS]-1000H, [SS]-2000H, [IP]-7000H.
(i) MOV AX, [5000H]
(ii) MOV AX, [BX]
(iii) MOV AX, 5000[BX]
(iv) (iv) MOV AX, [BX][SI]
(v) MOV AX, 5000[BX][SI]
Tutorial 2
Suppose the main program resides in the code segment where CS = 1000H. The
main program calls a subroutine which resides in the same code segment. The
base register contains offset of the subroutine, i.e. BX = 0050H. Find the
effective address, which addressing mode?

Since the offset is specified indirectly, as the content of BX, this is indirect
addressing. The instruction CALL [BX] calls the subroutine located at an
address 10H*CS + [BX] = 10050H, i.e. in the same code segment. Since the
control goes to the subroutine which resides in the same segment, this is an
example of intrasegment indirect addressing mode.
Tutorial 3
Let us now assume that the subroutine resides in another code segment, where
CS = 2000H. Now CALL 2000H:0050H, since the control now goes to different
segment and the address is directly specified in the instruction. In this case, find
the addressing mode and effective address.

The address of the subroutine is 20050Н, is an example of intersegment

direct addressing mode
Thank You