Executive Program on Analog and Power

Management IC Design
An Initiative of
by DRIIV, IIT Delhi (CART) & Zenith Railway Academy

PROGRAM BROCHURE

Blended Program
For Future ESDM Leaders
About the Stakeholders

The Centre for Automotive Research and Tribology (CART) was established in May
2019 with a vision to promote interdisciplinary research in the area of Electric Vehicle
(EV), energy storage and other relevant areas. The centre envisages strong networking
and collaboration among various academia, industries, edge search labs in India and
abroad to carry out cutting research things.

Delhi Research Implementation and Innovation (DRIIV),

DRIIV Foundation, is the umbrella body for the Delhi NCR science and technology
(S&T) cluster. The S&T clusters are a flagship programme of the Office of the Principal
Scientific Adviser to the Government of India, established upon the recommendation
of the Prime Minister’s Science, Technology and Innovation Advisory Council (PM-
STIAC) to create an Atmanirbhar Bharat through S&T. DRIIV is an ecosystem of
academic institutions, institutes of national importance, national and state research
laboratories, relevant ministries, industry partners (PSUs and corporates), state
governments, philanthropic foundations, international institutions, MSMEs, tech
startups and other such interested participants in the science and technology space.
The objective of DRIIV is to leverage the strength of the network to address
environmental and societal problems of regional and national relevance.

About Zenith Railway Academy

A leading railway training company with credentials of delivering training to 5000+

railway sector professionals across Signaling, RAMS, CBTC, ETCS, Rolling Stock,
ERTMS, CTC, Project Management, Functional Safety, EMI /EMC and many more. Our
world class online learning platform for rail companies brings best courses and
training to empower future rail leaders
 About the program

This course has been designed to cover very important basics of Analog Integrated
Circuit design. This course covers everything from MOSFET modelling to Complex Analog
Block designs. It focuses mainly on giving hands-on practical exposure in doing circuit
design for a given analog & mixed signal product. By the end of the course you will learn
circuit design in EDA tool, simulation, design verification of typical analog circuits such as
Opamp, PLL, Bandgap, LDO. This Course focus on giving insights of the design and
simulation of I/O’s, Memory as well. After the completion of the course, you will get
opportunity to move into domains such as Analog & Mixed Signal Design, Memory
Design, Standard Cell Design, and I/O Design.

Who should attend

- B.E/B.Tech in ECE/EEE.
- M.E/M.Tech/M.S in VLSI System
Design/Embedded Systems/Digital Electronics.
 This Decade will be the decade of
semiconductors
Opportunity Overview
The microelectronics and semiconductor industry in India
is poised for substantial growth, with the government's
PLI (Production Linked Incentive) scheme targeting an
investment of $1.45 billion in semiconductor
manufacturing over five years. India's electronics market
is projected to reach $400 billion by 2025, offering vast
opportunities for engineers. With over 200 R&D centers
and the presence of major players like TSMC and
Samsung, India is emerging as a global hub for
semiconductor design and manufacturing. Additionally,
initiatives like the National Electronics Policy and Make in
India further bolster the sector, ensuring a bright future
for young engineers.

Goals of the program are

- Deep understanding MOSFETs W.r.t Modelling, Noise, Matching & Non- Linearity
- Understand Analog Circuit Basics of Single Stage Amps, Differential Amps, Current Mirrors,
Two Stage Opamp Design, Feedback Theory & Frequency Compensation
- Understand Critical Analog Blocks such as Band Gap reference Design, Oscillators, Phase Lock
Loop Designs
- Critical Industry standard project execution under the guidance of 15+ year’s industry expert.
- 24×7 Lab Support with classroom practice handouts and course material.
- Soft skills development, job oriented analog design training with 100% placement assistance.

Learning Outcomes
•Deep understanding of semiconductor device working; MOSFET Model and working analysis
of Noise Models, and other important Circuit Design Parameters.

•Understanding of Component & System level issues of Power Management and

implementation as integrated chip.

•Understanding of various architectures of Power Management, their comparative study;

Understanding the basic building blocks & components of Power Management.

•Deep understanding of Design & simulation of Analog Integrated Circuits and Power
Management IC Components.
 Program Highlights

01 02
CERTIFICATION FROM IIT INDIA’S TOP FACULTIES
DELHI & PM-STIAC)
You get to learn from some of
Opportunity to earn certificate the best faculties and experts
of Completion from Indian who, by bringing their
Institute of Technology Delhi( prospects into the mix, help
DOEE) & PM STIAC learners grow.

03 04
WEEKEND ONLINE & INSIGHTS INTO GROWING
INTERACTIVE CLASSES INDUSTRY & MANAGEMENT
Classes are held on weekend so This course is full of hands-on
that learning and work can go exercises to get an in-depth
side by side and it's easy for understanding of ESDM that
working professionals to attend can help the participant to grow
lectures. as ESDM leaders

05
INDUSTRY INTERACTIONS
Interact with experts and
leaders from ESDM industry to
network and understand the
upcoming industry trends
06
CASE-BASED SESSIONS
Real life case-based study
pedagogy to enhance
implementation of theoretical
concepts to real life problems.
07
CAMPUS VISIT
2 days IIT DELHI Immersion
Program at the end of course
so that students can interact
with their faculties at the
campus in the most innovative
ways possible.
 PROGRAM OUTLINE
50 hours Online Live Sessions and two days bootcamp in IIT DELHI

MODULE 1 :
Basics of Semiconductors, MOSFETS, Characterization & Modeling, Noise, Matching
& Non-Linearity, Passive Components.

MODULE 2 :
Basics of Power Management Circuits (PMIC), Application, Need for Power
Management, Discrete Vs. Integrated PMIC; Performance Parameters - Efficiency,
Accuracy, Line & Load regulations.

MODULE 3 :

Architecture of Power Management ICS & Building Blocks of Power Management ICS.

MODULE 4 :

Detailed Design & Simulation of Building Blocks of Power Management ICS :

1. Spec Design.
2. MOS Amplifiers.
3. OP - Amp Design.
4. Comparator Design.
5. Ramp Generator.
6. Band Gap Reference using PTAT & CTAT.
7. LDO Design.
8. Feedback Theory
- Bode Plots.
- Loop Gain Analysis.
- Frequency Compensation.
- Stability Criterion & Phase Margin.

Certification
Upon successfull completion of the course a caertificate
of compeltion shall be awarded through Centre of
Automotive Research & Tribology and Office of the
Principal Advisor to the Government of India
EMINENT FACULTY PANEL FROM INDUSTRY

SANTANU K. MISHRA
Professor, Center for Automotive Research and Tribology (CART),
Indian Institute of Technology Delhi
Prior to joining CART, he worked with Infineon Technologies, Rhode
Island, USA from 2004 to 2008. He was a faculty at IIT Kanpur from
2008 to 2023. Currently, he is a Professor with CART, IIT Delhi.

VARUN RAJ
Varun Raj is an accomplished professional with over 15 years of
experience in Semiconductor IC Design & Deep Tech/AI-ML research
and development. A distinguished alumnus of IIT Delhi, he has held
key positions, including senior scientist at the Government of India
Defense Research Labs and senior design engineer roles at renowned
global semiconductor chip design MNCs. Beyond his corporate
achievements, Varun has also made substantial contributions to
education, dedicating time to teach and upskill professionals in the
ever-evolving landscape of technology.

COURSE DELIVERY COURSE SCHEDULE

Duration: 5 months blended Every Sunday at 9:00 AM to 12:15 PM

Delivery mode: Zoom/MS Teams (Break Time - 15 minutes)
Frequency: Once in a week Commencement Date: 9th November,
2024
 The course will be taught through online platforms.
Instructor’s notes, data and scripts will be shared via Google
Classroom.
COURSE Participants will be evaluated continuously through
assignments.
PEDAGOGY There will be (multiple choice based questions) MCQ exams
for each module.
Course material is solely meant for recipients and should
not be distributed/shared elsewhere.

B.E/B.Tech in ECE/EEE.
M.E/M.Tech/M.S in VLSI System Design/Embedded
Systems/Digital Electronics. ELIGIBILITY

There are periodic evaluations built in throughout the duration

of the course. These maybe in the form of a quiz, assignment,
Capstone Project, Main business plan, case study or other
ASSESSMENT
objective/subjective assessment. The evaluations are designed
CRITERIA to ensure continuous student engagement with the course and
encourage practical learning. Students who successfully clear
the same along with the requisite attendance criteria will be
awarded a Certificate from IIM Kashipur as appropriate.

The selection will be based on candidate’s ADMISSION

profile evaluation, subject to meeting
eligibility criteria. PROCESS
 Fee Structure & EMI Plan
Program Fee:
For Indian Residents INR 55,000+ GST*
*Application Fee of 2000- INR to be paid at the time of registration

Installment Schedule:
1st INR 15,000 + GST* Payment Deadline - Immediately
2nd INR 20,000 + GST* Payment Deadline - within 45 days from class commencement
3rd INR 20,000 + GST* Payment Deadline - within 90 days from class commencement
No Cost 10 Months EMI Option available by our loan partner:
Pay as Low as 5500 + GST* per month.
(INR 5500 + GST* x 10 = 55,000 + GST*)

INR 10,000 Fee discount for academic, government officials and students upon valid
documentation

Online payment or DD in favor of “Zenith Rail Edvarsity Private

Limited” payable at “Faridabad”.

PAYMENT
MODE
SCAN QR CODE TO APPLY

HOW TO APPLY

To apply, working professionals can register at https://www.railwayacademy.org or call at

.+91 95994 69435

Loan option with interest available in 9 & 12 EMIs

* EMI dates may vary on a case to case basis
* 1% + GST* processing fees will be charged by loan partner in 6/9/12 months EMI.
THANK YOU, AND WE LOOK
FORWARD TO SEE YOU IN CLASS

CONTACT US SCAN TO CONNECT

Zenith Rail Edvarsity Pvt Ltd
GSTIN 06AABCZ8413E1ZF
Address: 19th floor, Berger one towers,
Sector16A, Noida 201301
Email: [email protected]
Website: www.railwayacademy.org Contact
No: +91 95994 69435

Office of the Principal Scientific Adviser

to the Government of India
Vigyan Bhavan Annexe, Maulana Block II, IIT Delhi Main Rd, IIT Campus,
Azad Road, New Delhi - 110011 Indian Institute of Technology Delhi, Hauz
Khas, New Delhi, Delhi 110016
Phone: 011 2659 6102