ECE102: Semiconductor

Devices
Dr. Venkatnarayan Hariharan
Dept of Electrical Engg., Shiv Nadar Univ., Delhi NCR

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 Agenda
• Transistor (Xtor):
• Basics
• Family of curves, Load line
• MOSFET: Metal Oxide Semiconductor
Field Effect Transistor
• Overview
• Operation
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 Transistor (Xtor) Basics
• The xtor’s main operation involves three terminals, its main feature
being that the current through two terminals is controlled by small
changes in the current or voltage at the third terminal (gate). This
feature allows one to amplify small AC signals or to switch the device ON
and OFF. These two operations, amplification and switching, are the
basis of most electronic circuits. Two main types of xtors:
• FET (Field Effect Transistor) is a majority carrier device (carrier of only one type
takes part in operation), hence called a unipolar device. Two main types:
• MOSFET (Metal Oxide Semiconductor FET): The gate electrode is separated from the
semiconductor by an insulator. The gate voltage varies the conductivity of a sheet of
inversion layer, which modulates current flow between two other terminals (Source and
Drain)
• JFET (Junction FET): The voltage on the Gate terminal varies the depletion width of a
reverse-biased p-n junction, due to which current flow between two other terminals
(Source and Drain) is modulated
• BJT (Bipolar Junction Transistor) is a minority carrier device (both electrons and
holes take part in operation), hence called a bipolar device
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 Family of Curves, Load line
• Consider a 3-terminal xtor with control
voltage 𝑣𝐺 and the voltage between 2 other
terminals being 𝑣𝐷 , biased using source 𝐸
1
• From KVL, it is clear that 𝑖𝐷 = 𝐸 − 𝑣𝐷 . This
is a straight line in the 𝑖𝐷 − 𝑣𝐷𝑅plot, and is
called the load line
• The xtors itself has a 𝑖𝐷 = 𝑓(𝑣𝐺 , 𝑣𝐷 ) model
(which can be arbitrarily complex in general),
which is plotted as a family of curves for
various values of the control voltage 𝑣𝐺
• The intersection of the family of curves with
the load line gives the operating point, for a
given control voltage 𝑣𝐺
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 MOSFET Overview
• The MOSFET is a ubiquitous semiconductor device of choice that makes
an overwhelming majority of integrated circuits work, that are used in
everyday consumer goods that we use in our daily lives (computer,
mobile phone, car engine ECU, TV remote control, etc)
• The MOS transistor is particularly useful in digital circuits, in which it is
switched from the “off” state (no conducting channel) to the “on” state.
The control of current between 2 terminals (source S and drain D) is
done by a gate electrode G, which is insulated from the rest of the
structure by an insulating oxide. Thus the DC input impedance of a MOS
circuit can be very large
• Both n-channel and p-channel MOS xtors are in common usage, whose
structure and operation we’ll next see
• The n-channel xtor is generally preferred because it takes advantage of the
fact that the electron mobility in Si is larger than the hole mobility
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Structure and Schematic Symbols
• Left figure shows schematic symbols, right figure shows the structure of a n-channel
MOSFET (NMOS device) along with two key dimensions, viz. channel length 𝐿 and width
𝑊 (𝐿 & 𝑊 being the dimensions along & across the channel, respectively)
• In a PMOS device, the S and D regions are p+ while the body is of n-type. The gate material is also
suitably different. In either device, body terminal B is sometimes referred to as substrate terminal
• The thick SiO2 is for isolating from other nearby devices (ie. xtors). The body is usually
connected to a suitable power rail (not always though)
P-channel
(aka PMOS
xtor, ie.
body is n-
type)

N-channel W
(aka NMOS
xtor, ie.
body is p-
type)

Enhancement- Body connection implied (ie. Depletion-

mode for connected to appropriate mode
power rail). The notation on L
the left/right is commonly
used in digital/analog
circuits respectively
Schematic symbols 3D structure of a N-channel MOSFET (NMOS)
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 Operation: Band Diagrams
NMOSFET (assuming 𝜙𝑚 = 𝜙𝑠 ): Very similar to
band diagram of NMOSCAP across the channel

Equilibrium: That is, Accumulation: Negative Depletion: Small positive Inversion: Large positive
0 gate voltage gate voltage causes gate voltage depletes gate voltage, after
accumulation of holes holes from p-type maximal depletion,
in p-type semicon semicon causes inversion, ie.
creation of a sheet of
Notice that the Fermi levels in M and S are separated in electrons on surface of
p-type semicon!
non-equilibrium, but are yet spatially flat due to 0 current
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 Operation
• For a MOSFET device, when a suitable voltage is applied to the gate G
wrt the source S, charges are induced in the underlying Si body by the
formation of a depletion region and eventually a thin inversion layer of
mobile carriers is formed just below the oxide-silicon interface, very
similar to the MOSCAP that we discussed earlier in inversion regime
• For a NMOS device with source and substrate grounded, when a positive
voltage of suitable magnitude 𝑽𝒈𝒔 > 𝑽𝒕 is applied to the gate, positive charges
are deposited on the gate metal and a thin inversion layer of mobile electrons
is formed sub-surface. These electrons form the channel of the NMOS device,
and allow current to flow from D to S (comprising electrons, flowing from S to
D)
• For a PMOS device with source and substrate connected to positive supply rail
𝑽𝑫𝑫 , when a gate voltage 𝑽𝒈𝒔 < 𝑽𝒕 of suitable magnitude is applied, negative
charges are deposited on the gate metal and a thin inversion layer of mobile
holes is formed sub-surface. These holes form the channel of the PMOS device,
and allow current to flow from S to D (comprising holes, flowing from S to D)
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 Operation
• The threshold voltage 𝑉𝑡 is the minimum gate voltage required to
induce the channel. In general, the positive gate voltage of an n-
channel device must be larger than some value 𝑉𝑡 before a
conducting channel is induced. Similarly, a p-channel device (made
on an n-type substrate with p-type source and drain implants or
diffusions) requires a gate voltage sufficiently negative to induce
the required positive charge (mobile holes) in the channel
• Exceptions: Some n-channel devices have a channel already with zero gate
voltage, and in fact a negative gate voltage is required to turn the device
off. Such a “normally on” device is called a depletion-mode xtor, since gate
voltage is used to deplete a channel which exists at equilibrium. The more
common MOS transistor is “normally off” with zero gate voltage, and
operates in the enhancement-mode by applying gate voltage large enough
to induce a conducting channel
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 Pinch-off
• For a NMOS xtor with S and B grounded and some
D voltage 𝑉𝐷𝑆 > 0, as the magnitude of 𝑉𝐺𝑆 is
increased the voltage difference between the gate
and the channel reduces, from 𝑉𝐺 near the source
to 𝑉𝐺 – 𝑉𝐷 near the drain end. Once the drain bias
𝑉𝐷 is increased to the point that 𝑉𝐺 – 𝑉𝐷 reduces to
𝑉𝑡 , then threshold is barely maintained near the
drain end, and the channel is said to be pinched-
off. The pinch-off concept applies for PMOS devices
also
• NMOS device in different operating regimes:
a) Linear regime: 𝑉𝐺𝑆 > 𝑉𝑡 and 𝑉𝐺𝐷 > 𝑉𝑡
b) Onset of pinch-off (saturation): 𝑉𝐺𝑆 > 𝑉𝑡 and 𝑉𝐺𝐷 =
𝑉𝑡 (ie. 𝑉𝐺 − 𝑉𝐷 = 𝑉𝑡 ⇒ 𝑉𝐷 = 𝑽𝑮 − 𝑽𝒕 ≜ 𝑽𝑫𝑺𝒂𝒕 )
c) Post-pinch-off: 𝑉𝐺𝑆 > 𝑉𝑡 and 𝑉𝐺𝐷 < 𝑉𝑡
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END OF LECTURE

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