MARWADI UNIVERSITY

Subject Code:01CE0509
Subject Name: Fundamental of Processors
B.Tech. Year–III

Unit- 4
 Outline
Looping
• Introduction
• Flow chart
• Programming steps
• Programmable Peripheral IC:
• Intel 8255,
• Intel 8255A Pin Description,
• 8279 Keyboard and Display Controller,
• 8259A Programmable Interrupt Controller,
• DMA and 8237 DMA Controller
Syllabus

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Flowchart
Flow chart is graphical representation of a flow of data and
sequence of events during the execution of program.

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Flowchart
Advantages of using flowchart:

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Flowchart
Limitations of using flowchart:

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Programming steps
1. Define the Problem to be solved: the problem for which you
are preparing the program, the different terms must be
clearly mentioned such as,
1. What are the inputs to your program?
2. What is the operation you are expecting?
3. Where you want the output?
2. Solution Plan: The plan to solve the program should be
prepared like
1. How are you taking input data?
2. Which method you are using to solve the problem and steps?
3. How will you output the results?
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Programming steps
3. Flowchart: Prepare the flowchart for the plan you have
decide to give the exact idea of how program should flow to
be flow to get correct result.
4. Program: Go on putting the Instructions in the place of
flowchart blocks.
5. Check the result: Now find the codes for instructions
Processor and execute the program. It will give you result.
If the result is correct, the program you have prepared is
correct.

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8279- Keyboard and Display Controller
8279 programmable keyboard/display controller is designed by
Intel that interfaces a keyboard with the CPU.
The 8279 first scans the keyboard and identifies if any key has
been pressed.
It then sends their relative response of the pressed key to the
CPU and vice-a-versa.

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8279- Keyboard and Display Controller
How Many Ways the Keyboard is Interfaced with the CPU?
The Keyboard can be interfaced either in the interrupt or the
polled mode. In the Interrupt mode, the processor is requested
service only if any key is pressed, otherwise the CPU will
continue with its main task.
In the Polled mode, the CPU periodically reads an internal flag
of 8279 to check whether any key is pressed or not with key
pressure.

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8279- Keyboard and Display Controller
How Does 8279 Keyboard Work?
The keyboard consists of maximum 64 keys, which are
interfaced with the CPU by using the key-codes.
These key-codes are de-bounced and stored in an 8-byte FIFO
RAM, which can be accessed by the CPU.
If more than 8 characters are entered in the FIFO, then it means
more than eight keys are pressed at a time.
This is when the overrun status is set.

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8279- Keyboard and Display Controller
How Does 8279 Keyboard Work?
If a FIFO contains a valid key entry, then the CPU is interrupted
in an interrupt mode
else the CPU checks the status in polling to read the entry.
Once the CPU reads a key entry, then FIFO is updated,
and the key entry is pushed out of the FIFO to generate space
for new entries.

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8279- Keyboard and Display Controller
Architecture and Description:

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8279- Keyboard and Display Controller
Architecture and Description:
Let us understand the operation of this architecture by
considering its 4 separate sections.
1. Keyboard Section:
➢ This section is composed of Return Buffer and Keyboard De-
bounce and Control.
➢ It holds the 8 return lines denoted by RL0 to RL7 that forms
the column of the keyboard matrix.
➢ Shift and Control/Strobe are the two additional inputs
provided to this unit.
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8279- Keyboard and Display Controller
Architecture and Description:
It has 8*8 FIFO RAM that works on the First–In–First–
Out approach and can store 8 keycodes (code of pressed key)
at a time in a sequential manner.
The status of two additional input keys i.e., shift and control are
also stored within FIFO RAM.

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8279- Keyboard and Display Controller
Architecture and Description:
In scan keyboard mode,
8 keycodes are stored and anytime whenever an entry is made
in the FIFO RAM then 8279 generates an interrupt signal that
tells the processor to perform FIFO read operation till the time
everything within FIFO is serviced.
While in sensor matrix mode, the FIFO RAM holds the condition
of 64 switches within it regarding whether these are open or
closed. Whenever the condition of any switch is changed then
8279 generates an interrupt request for the processor.
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8279- Keyboard and Display Controller
Architecture and Description:
2. Display Section: This section is constituted by display
address registers and display RAM.
This section contains 8 output lines i.e., A0-A3 and B0-B3 and
these are connected to the 7-segment LEDs.
There is a 16*8 display RAM and the processor simply performs
read and write operations within this RAM.
The display address registers contain the address of that word
on which the processor is currently performing the read/write
operation.
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8279- Keyboard and Display Controller
Architecture and Description:
3. Scan Section: The scan counter and four scan lines (SL0 to
SL3) are part of this section.
There are two modes of scan counter namely, encode and
decode.
In encode mode, a binary count will be obtained as the output of
scan lines and this requires external decoding to give rise to
decoded output.
These output scan lines are the same for the keyboard and
display and 4 scan lines can drive up to 16 displays.
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8279- Keyboard and Display Controller
Architecture and Description:
However, in decode scan mode, internal decoding is performed
that will provide a decoded 1 out of 4 scan lines and thus can
drive up to 4 displays.
Through scan lines, rows of the matrix keyboard are formed,
and also it forms the connection to the drivers of the display
unit.

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8279- Keyboard and Display Controller
Architecture and Description:
4. CPU Interface Section:
This section is composed of I/O control and Data Buffers along
with Timing and Control Registers.
The timing and control unit is also a part of this unit.
This section is responsible for data transfer between 8279 and
the CPU and hence consists of bidirectional data lines DB0 to
DB7.

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8279- Keyboard and Display Controller
Architecture and Description:
There are two internal addresses whose specified value i.e.,
either 0 or 1 makes the selection for either data buffer or
control register.
Here we have pins A0, CS, RD, and WR that are used for
command, status, read and write operations.
The IRQ is an interrupt request line that is specified for data
transfer that is associated with generated interrupt requests.

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8279- Keyboard and Display Controller
Architecture and Description:
It operates on an internal clock frequency of 100 kHz. The
RESET signal provided to the 8279 is responsible for setting its
16-character display. The control and timing register holds the
modes and operating conditions which program the CPU.

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8279- Keyboard and Display Controller
PIN DESCRIPTION:
• A0: Selects data (0) or control/status (1) for reads and
writes between micro and 8279.

Output that blanks the displays.

• CLK: Used internally for timing. Max is 3 MHz.

• CN/ST: Control/strobe, connected to the control key on

• Chip select that enables programming, reading the

• DB7-DB0: Consists of bi-directional pins that connect

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8279- Keyboard and Display Controller
PIN DESCRIPTION:
• IRQ: Interrupt request, becomes 1 when a key is
pressed, data is available.
• OUT A3-A0/B3-B0: Outputs that sends data to the most
significant/least significant nibble of display.
• : Connects to micro's IORC or RD signal, reads
data/status registers.
• RESET: Connects to system RESET.
• RL7-RL0: Return lines are inputs used to sense key
depression in the keyboard matrix.
•Shift: Shift connects to Shift key on keyboard.
• SL3-SL0: Scan line outputs scan both the keyboard and
displays.

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8279- Keyboard and Display Controller

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DMA and 8237 DMA Controller.
 Introduction: DMA stands for Direct Memory Access.
It is designed by Intel to transfer data at the fastest rate.
It allows the device to transfer the data directly to/from
memory without any interference of the CPU.
Suppose any device which is connected to input-output port
wants to transfer data to memory,
first of all it will send input-output port address and control
signal, input-output read to input-output port,
then it will send memory address and memory write signal to
memory where data has to be transferred.
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DMA and 8237 DMA Controller.
 In normal input-output technique the processor becomes busy
in checking whether any input-output operation is completed or
not for next input-output operation, therefore this technique is
slow.
This problem of slow data transfer between input-output port
and memory or between two memory is avoided by
implementing Direct Memory Access (DMA) technique.
This is faster as the microprocessor/computer is bypassed and
the control of address bus and data bus is given to the DMA
controller.
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DMA and 8237 DMA Controller.
8237 is a high-performance programmable DMA controller.
Some of the important features of 8237 DMA controllers are
mentioned below:
Features of 8237 DMA Controller:
It provides various modes of Direct memory access (DMA).
It provides on-chip four independent DMA channels. The
number of channels can be increased by cascading DMA
controller chips.
Each channel can be used in auto initialization mode.

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DMA and 8237 DMA Controller.
It can transfer data between two memory blocks in DMA mode
i.e. memory to memory transfer.
In memory-to-memory transfer, a single word can be written into
all locations of memory blocks.
The address of memory is either incremented or decremented
after each DM cycle depending upon the mode.
The clock frequency is 3 MHz (8237 DMA C0ntroller) or 5 MHz
(8237-2 DMA Controller).
The data transfer rate is very high i.e. 1.6 Mbytes/second for
8237-2 at 5 MHz.
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DMA and 8237 DMA Controller.
Directly expandable to any number of channels. It doesn’t
require any additional chip for cascading. There are no
limitations in cascading.
The DMA can be requested by setting an appropriate bit for the
request register.
It provides compressed timings to improve the throughput of
the system. It can compress the transfer time to two cycles
(2s).

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DMA and 8237 DMA Controller.
Pin Configuration:
CLK: This is the clock input line.
The data transfer rate depends upon the
frequency of this signal.
CS: Select the 8237 chip for
communication between the CPU and
8237
Reset: It is an asynchronous input line.
This signal clears the command, status,
request, and temporary register
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DMA and 8237 DMA Controller.
Pin Configuration:
READY: this signal is used to add wait
states into the DMA cycle.
HRQ: It is a hold request output line. It is
connected to hold the input of the CPU. it
is used to request control of the system
bus.
HLDA: It is a hold acknowledge input line.
This signal is generated by the CPU.

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DMA and 8237 DMA Controller.
Pin Configuration:
IOR:It is an active low bi-directional
tristate line.
This signal is generated during the DMA
cycle to read data from the I/O device.
IOW: It is an active low bi-directional
tristate line.
This signal is generated during the DMA
read cycle to write data into the I/O
device.
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DMA and 8237 DMA Controller.
Pin Configuration:
A0 – A3These are bi-directional, address
lines. the 8237 provides lower bits of
memory address on these lines.
A4 – A7These are tristate address output
lines.
the 8237 transfers higher bits of memory
addressed on these lines.

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DMA and 8237 DMA Controller.
Pin Configuration:
MEMR: It is an active low tristate output
line.
during memory to memory transfer cycle
to read the contents of source memory.
MEMWIt is an active low tristate output
line.
during the memory-to-memory transfer
cycle to write data into destination
memory.
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DMA and 8237 DMA Controller.
Pin Configuration:
DB0 – DB7These are bi-directional tristate
buffered data lines.
these lines are used to transfer data
between the CPU and 8237 registers.
DREQ0 –DREQ3 :These are asynchronous
DMA channel request lines used by the
peripheral. these lines can be used as
either active high or active low input. –

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DMA and 8237 DMA Controller.
Pin Configuration:
DACK0–DACK3:These are DMA
acknowledge output lines.
The signal indicates that the requesting
peripheral has been granted for the DMA
cycle.
EOP: End of Process: It is an active low
bi-directional signal.
 This line is also used to terminate the
DMA cycle.
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DMA and 8237 DMA Controller.
Block Diagram:

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Thank You